IEEE Transactions on Electron Devices最新文献

{"title":"Operation Voltage Reduction of Silicon Based Light Sources by Surface Texturing","authors":"O. Pérez-Díaz;A. A. González- Fernández;D. Estrada-Wiese;M. Aceves-Mijares","doi":"10.1109/TED.2025.3556107","DOIUrl":"https://doi.org/10.1109/TED.2025.3556107","url":null,"abstract":"Silicon-rich oxide (SRO) light-emitting capacitors (LECs) have proven to be good candidates to be monolithically integrated in electrophotonic (Eph) circuits due to their complementary metal-oxide–semiconductor (CMOS) fabrication compatibility and broadband emission spectra. However, their relatively high operating voltage (i.e., the voltage required to emit detectable light) limits their use in applications where portability and low energy consumption are imperative. Among the strategies to overcome this problem, the interlayering of SRO films with different electrical and light-emitting properties has been explored besides the use of metal-assisted chemical etching (MACE)-textured Si substrates to improve carrier injection into the active material. In this study, a combination of both the strategies is analyzed by fabricating LECs featuring SRO multilayer (ML) structures on top of Si textured substrates to reduce the operating voltage of the LECs even farther. The textured Si surfaces were studied to determine an improved arrangement of different SRO layers to ensure complete coverage of Si peaks formed during texturing of the substrate. For comparison, the same LEC structures were fabricated on polished substrates showing an increased operating voltage of around <inline-formula> <tex-math>${V} _{text {op}} =50$ </tex-math></inline-formula> V in contrast to the new proposed LECs, which presented light emission at only <inline-formula> <tex-math>${V} _{text {op}} =15$ </tex-math></inline-formula> V. These results open promising application opportunities to monolithically integrate Si-based light emitters in photonic and electronic devices and circuits.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2179-2186"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultralow Contact Resistivity of <0.13 Ω · mm for Normal Ti/Al/Ni/Au Ohmic Contact on Non-Recessed i-AlGaN/GaN","authors":"Xiao Wang;Zhiyu Lin;Yumin Zhang;Jianfeng Wang;Ke Xu","doi":"10.1109/TED.2025.3555265","DOIUrl":"https://doi.org/10.1109/TED.2025.3555265","url":null,"abstract":"By utilizing a traditional Ti/Al/Ni/Au metal stack on i-AlGaN/GaN, we achieved an ultralow contact resistivity of <inline-formula> <tex-math>$lt 0.13~Omega ~cdot $ </tex-math></inline-formula> mm through a combined annealing process, which includes holding at <inline-formula> <tex-math>$550~^{circ }$ </tex-math></inline-formula>C for 20 s, followed by a 60-s annealing at <inline-formula> <tex-math>$840~^{circ }$ </tex-math></inline-formula>C with an optimized ramp-up rate of <inline-formula> <tex-math>$10~^{circ }$ </tex-math></inline-formula>C/s. The formation of TixAlyAuz alloy spikes directly contacting the 2DEG is identified as the primary mechanism for the ultralow contact resistance, which we attribute to the severity of Al transitioning into a molten state during the process.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2246-2251"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of a Low-Loss Transmission Structure for W-Band TWT","authors":"Zhiyu Chen;Jingrui Duan;Yuan Zheng;Hao Li;Yubin Gong","doi":"10.1109/TED.2025.3556048","DOIUrl":"https://doi.org/10.1109/TED.2025.3556048","url":null,"abstract":"A low-loss transmission structure for W-band traveling wave tube (TWT) is proposed in this article. It converts the rectangular waveguide fundamental TE10 mode into the corrugate waveguide HE11 mode with a quasi-Gaussian energy distribution, thereby reducing ohmic loss on the waveguide walls. The sections maintaining and generating the HE11 mode are theoretically analyzed. The simulation results show that the <inline-formula> <tex-math>${S} _{{11}}$ </tex-math></inline-formula> of the converter is less than −20 dB in the frequency range of 80–100 GHz, and the mode conversion purity reaches 99.66%. Compared with a conventional rectangular waveguide with a 4.5 dB/m transmission loss, the insertion loss of novel structure has successfully been reduced by 3.1 dB/m to as low as 1.4 dB/m Furthermore, the same length W-band low-loss transmission structure and rectangular waveguide have been fabricated and cold-tested, the results reveal a reduction in insertion loss of 2.5 dB per meter, verifying the simulation predictions. A burned spot experiment was conducted to verify the energy distribution of the HE11 mode. The experimental results confirm the feasibility of the proposed low-loss transmission structure for low-loss transmission in W-band TWT input-output structures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2611-2617"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extremely High ESD Failure Voltage of RESURF LDMOS Devices for ESD Resilient Driver Applications","authors":"Aakanksha Mishra;M. Monishmurali;B. Sampath Kumar;Shaik Ahamed Suzaad;Shubham Kumar;Kiran Pote Sanjay;Amit Kumar Singh;Avinash Singh;Ankur Gupta;Mayank Shrivastava","doi":"10.1109/TED.2025.3556114","DOIUrl":"https://doi.org/10.1109/TED.2025.3556114","url":null,"abstract":"This work reports an extremely high ESD failure voltage in the transmission line pulse (TLP) characteristics of the laterally diffused metal-oxide-semiconductor (LDMOS) devices, while investigating a correlation between the critical voltage and filament formation. A high failure voltage enables an additional immunity to ESD damage by providing extra protection against the overvoltage stress in high-voltage (HV) I/O applications. The ESD behavior of LDMOS devices in the presence of reduced surface field (RESURF)-implant in the drift region is investigated in detail. Furthermore, an approach to drift region design and electric field engineering that affects this high failure voltage in RESURF LDMOS devices is discussed, using measurement and 3-D TCAD simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2187-2194"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of 1-MeV Equivalent Neutron Irradiation on the Electrical Characteristic of NiOx/β-Ga2O3 p-n Diode","authors":"Yahui Feng;Hongxia Guo;Wuying Ma;Xiaoping Ouyang;Jinxin Zhang;Fengqi Zhang;Dinghe Liu;Xiaohua Ma;Yue Hao","doi":"10.1109/TED.2025.3554746","DOIUrl":"https://doi.org/10.1109/TED.2025.3554746","url":null,"abstract":"In this article, the impact of 1-MeV equivalent neutron irradiation on the electronic properties of NiOx/beta-phase gallium oxide (<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2<inline-formula> <tex-math>${mathrm {O}}_{{3}}text {)}$ </tex-math></inline-formula> p-n diode has been investigated. After neutron irradiation with a fluence of <inline-formula> <tex-math>$1times 10^{{14}}$ </tex-math></inline-formula> n/cm2, the forward current density (<inline-formula> <tex-math>${J}_{F}text {)}$ </tex-math></inline-formula> decreased by 23%, the leakage current density (<inline-formula> <tex-math>${J}text {)}$ </tex-math></inline-formula> was reduced by 45.6%, and the breakdown voltage (<inline-formula> <tex-math>${V}_{text {br}}text {)}$ </tex-math></inline-formula> increased by approximately 216 V, as measured by current − voltage (I–<inline-formula> <tex-math>${V}text {)}$ </tex-math></inline-formula> analysis. The capacitance− voltage (C–<inline-formula> <tex-math>${V}text {)}$ </tex-math></inline-formula> measurement shows that the carrier concentration in the lightly doped n-type <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 drift layer decreased from <inline-formula> <tex-math>$1.96times 10^{{16}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$1.74times 10^{{16}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{3}}$ </tex-math></inline-formula> after neutron irradiation. The effect of neutron irradiation on the trap states was studied using frequency-dependent conductivity techniques. It is revealed that the density of trap states at NiOx/<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 increases significantly from 1.12 to <inline-formula> <tex-math>$1.49times 10^{{12}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}cdot $ </tex-math></inline-formula>eV<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula> to 3.76-<inline-formula> <tex-math>$5.80times 10^{{12}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}cdot $ </tex-math></inline-formula>eV<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>, accompanied by a slight decrease in trap activation energy from 0.091 to 0.187 eV to <inline-formula> <tex-math>$0.086-0.185$ </tex-math></inline-formula> eV after neutron irradiation. Additionally, deep-level transient spectroscopy (DLTS) measurements indicate that the trap at an energy level of <inline-formula> <tex-math>${E}_{C}$ </tex-math></inline-formula>–<inline-formula> <tex-math>${E}_{T} =0.75$ </tex-math></inline-formula> eV, induced by neutron irradiation, is likely the primary cause of the degradation in NiOx/<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 p-n diode properties. These findings can offer significant theoretical insights for the design of future anti-radiation hardening.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2240-2245"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Amorphous Indium Oxide Channel FEFETs With Write Voltage of 0.9 V and Endurance >1012 for Refresh-Free Embedded Memory","authors":"Sharadindu Gopal Kirtania;Hyeonwoo Park;Omkar Phadke;Eknath Sarkar;Dyutimoy Chakraborty;Faaiq G. Waqar;Jaewon Shin;Asif Khan;Shimeng Yu;Suman Datta","doi":"10.1109/TED.2025.3554471","DOIUrl":"https://doi.org/10.1109/TED.2025.3554471","url":null,"abstract":"This work presents, for the first time, a back-end-of-the-line (BEOL)-compatible W-doped indium oxide (IWO) ferroelectric field-effect transistor (FEFET) with a record-low operating voltage below 0.9 V and a write speed of 20 ns while achieving a transient read current window (CW) ratio (<inline-formula> <tex-math>${I}_{text {LVT}}/{I}_{text {HVT}}$ </tex-math></inline-formula>) greater than <inline-formula> <tex-math>${10}^{{4}}$ </tex-math></inline-formula>. The device also exhibits exceptional reliability characteristics such as: 1) measured bipolar write endurance up to <inline-formula> <tex-math>${10}^{{12}}$ </tex-math></inline-formula> cycles; 2) a fast read speed of 50 ns; 3) read endurance surpassing <inline-formula> <tex-math>${10}^{{12}}$ </tex-math></inline-formula> cycles; and 4) retention exceeding <inline-formula> <tex-math>${10}^{{4}}$ </tex-math></inline-formula> s at <inline-formula> <tex-math>$85~^{circ } $ </tex-math></inline-formula>C. Furthermore, a physics-based numerical model has been developed to investigate the nanoscale characteristics of BEOL FEFET devices, leveraging nucleation-limited switching in HfO2 ferroelectrics and dc characterization to extract material and channel parameters for accurate device simulation. The simulation uncovers the stochastic switching behavior of BEOL amorphous oxide semiconductor (AOS) FEFETs and demonstrates an intrinsic switching time as low as 1 ps, highlighting the potential of BEOL AOS FEFETs for ultrafast memory applications. These results establish AOS FEFETs as a compelling candidate for high-density embedded memory applications for last-level cache (LLC) (L4) in advanced CMOS technology nodes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2691-2699"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10957818","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-Long Disturb-Free Read Operation With Low Resistance Drift in Phase Change Memory","authors":"Ruoqin Wang;Jia Zheng;Ruobing Wang;Chenchen Xie;Li Xie;Xi Li;Zhitang Song;Xilin Zhou","doi":"10.1109/TED.2025.3555276","DOIUrl":"https://doi.org/10.1109/TED.2025.3555276","url":null,"abstract":"Compute-in-memory requires long endurance in reading of memory device orders of magnitude higher than writing. Variations in resistance of memory cells caused by read disturbance is a critical challenge for neural networks applications of emerging memory technology. Current generated by read voltage causes localized heating in the phase change memory (PCM) cell, which results in structural displacement of active phase change volume and thus appreciable variation in cell resistance. In this work, the effects of reading on both high and low resistance states (HRS and LRS) of PCM after various writing cycles are investigated. A disturb-free read scheme is demonstrated up to 1012 read cycles (~28 h) on the memory cells that experienced 108 write cycles both at <inline-formula> <tex-math>$27~^{circ }$ </tex-math></inline-formula> C and <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula> C. The reduced resistance drift by increasing the read voltage up to 0.5 V is observed which further improves the speed and accuracy of reading. This work shows that carbon-doped Ge2Sb2Te5-based PCM is a promising candidate for compute-in-memory application that requires enormous reading with high-precision.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2633-2639"},"PeriodicalIF":2.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Three-Dimensional Modeling of BEOL TDDB: Variability Specs for Sub-20 nm Half-Pitch Interconnects","authors":"Yu Fang;I. Ciofi;Ph. J. Roussel;A. Lesniewska;V. M. Blanco Carballo;R. Degraeve;I. De Wolf;K. Croes","doi":"10.1109/TED.2025.3554474","DOIUrl":"https://doi.org/10.1109/TED.2025.3554474","url":null,"abstract":"A pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2165-2172"},"PeriodicalIF":2.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultrahigh Frequency and Multichannel Output Skyrmion-Based Nano-Oscillator","authors":"Saumya Gupta;Abhishek Sharma;Debasis Das;Ashwin A. Tulapurkar;Bhaskaran Muralidharan","doi":"10.1109/TED.2025.3554473","DOIUrl":"https://doi.org/10.1109/TED.2025.3554473","url":null,"abstract":"Spintronic-based skyrmion nano-oscillators can generate tunable microwave signals that find a wide range of applications in the field of telecommunication to modern neuromorphic computing systems. Skyrmions within a single ferromagnet (FM) material encounter an undesired Magnus force, which imposes limitations on the oscillator’s frequency, typically reaching only a few gigahertz. However, for applications requiring higher data transmission speeds, oscillator frequencies must be elevated to tens of GHz. Conversely, a bilayer device featuring two FM layers coupled in a synthetic anti-ferromagnetic (SAF) configuration can effectively neutralize the Magnus force. Utilizing the bilayer device concept, we propose a multichannel oscillator design, and using micromagnetic simulations, we demonstrate that our proposed device could achieve an ultrahigh frequency of 41 GHz. The ultrahigh operational frequency represents a <inline-formula> <tex-math>$sim 342times $ </tex-math></inline-formula> improvement compared to the monolayer single skyrmion oscillator. We demonstrate the effectiveness of our proposed multichannel oscillator design by introducing multichannel nanotracks along with multiple skyrmions for enhanced frequency operation. The ultrahigh operational frequency and multichannel output are attributed to three key factors: 1) higher spin-flip length of the spacer (such as Ru) material, separating two FM layers; 2) tangential velocity, proportionality on input spin current along with weak dependence on the radius of rotation of the skyrmion-pair; and 3) skyrmion interlocking in the channel enabled by the multichannel high anisotropy rings and skyrmion-skyrmion repulsion.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2618-2624"},"PeriodicalIF":2.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3-D Vertical Resistive Switching Random Access Memory (3D-VRRAM) With Multilevel Programming for High-Density, Energy-Efficient In-Memory Computing","authors":"D. Bridarolli;C. Zucchelli;P. Mannocci;S. Ricci;M. Farronato;G. Pedretti;Z. Sun;D. Ielmini","doi":"10.1109/TED.2025.3554472","DOIUrl":"https://doi.org/10.1109/TED.2025.3554472","url":null,"abstract":"Resistive random access memory (RRAM) devices offer a broad range of attractive properties for in-memory computing (IMC) applications, such as nonvolatile storage, low read current, and high scalability. IMC allows to overcome the memory bottleneck of data-intensive workloads, such as deep learning on the edge. In this context, 3-D vertical RRAM (3D-VRRAM) is a promising option to achieve high memory cell capacity with low fabrication cost. In this work, we present an HfOx-based 3D-VRRAM crossbar array (CBA) capable of IMC with precise multilevel programming. We show an extensive experimental demonstration of both matrix-vector multiplication (MVM) and inverse/pseudoinverse matrix calculation via IMC on 3D-VRRAM. To further support the parallel IMC application in real-life scenarios, the work also reports a demonstration of relatively large-size problems adopting 2D-RRAM and SRAM-based memory arrays. These results support 3D-VRRAM for high-density, energy-efficient IMC for edge computing applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2677-2684"},"PeriodicalIF":2.9,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10949642","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}