IEEE Transactions on Electron Devices最新文献

{"title":"Enhanced Hole Accumulation Effect in P-GaN HEMTs With Al(Ga)N Gate-Insertion-Layer Under Heavy Ions Irradiation","authors":"Jianggen Zhu;Fukang Yang;Shuting Huang;Xin Zhou;Huan Gao;Keping Wu;David Zhou;Bo Zhang;Qi Zhou","doi":"10.1109/TED.2026.3701684","DOIUrl":"https://doi.org/10.1109/TED.2026.3701684","url":null,"abstract":"In this work, the mechanism of single-event effects (SEEs) in a 100-V p-GaN gate high electron mobility transistor (HEMT) featuring an Al(Ga)N gate-insertion-layer (GIL) in the p-GaN gate is investigated. The irradiation experiments were conducted using Kr ions with a linear energy transfer (LET) of 37.9 MeV <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{{2}} cdot $ </tex-math></inline-formula> mg<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>. Distinct single-event burnout (SEB) phenomena were observed under zero- and negative-gate bias conditions. The device under zero bias exhibits recoverable behavior after an SEB-like event, while permanent failure occurs under negative gate bias, yet the SEB threshold is higher. Enhanced hole accumulation in the p-GaN region induced by the GIL is found to be responsible for triggering the premature SEB. TCAD simulations reveal that at a critical drain voltage, this enhanced hole accumulation effect eliminates the channel barrier and induces the subsequent leakage current increase, enabling channel conduction and triggering SEB during irradiation. Under prolonged irradiation at a drain bias below the SEB voltage, the initial rise in the average drain current further indicates continuous hole accumulation. Postirradiation degradation is manifested as a negative threshold voltage shift of 0.21 V and a source–drain leakage increase by two orders of magnitude, associated with irradiation-induced damage in the p-GaN gate. These results indicate that the detailed gate epistructure is sensitive to SEEs, which should be delicately designed in the p-GaN HEMT for space applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4665-4672"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"P-Channel GaN FETs on Low-Doped Layers Enabled by Thermal Mg-Diffusion Process: Demonstration and Characterization","authors":"Manuel Fregolent;Biplab Sarkar;Shun Lu;Jia Wang;Hirotaka Watanabe;Kwon Woong;Carlo De Santi;Gaudenzio Meneghesso;Enrico Zanoni;Yoshio Honda;Hiroshi Amano;Matteo Meneghini","doi":"10.1109/TED.2026.3707083","DOIUrl":"https://doi.org/10.1109/TED.2026.3707083","url":null,"abstract":"This work reports on the development of GaN-based p-channel FETs on low-doped (~<inline-formula> <tex-math>${{10}}^{{17}}text {c}text {m}^{-{3}}text {)}$ </tex-math></inline-formula> p-GaN layers by exploiting enhanced ohmic contacts obtained with a post-growth thermal Mg-diffusion process. Two architectures were tested, namely 1) MESFETs and 2) MOSFETs. The presence of improved ohmic contacts on very low-doped layers reflects in highly ideal DC characteristics, showing an I<inline-formula> <tex-math>${}_{mathrm {ON}}$ </tex-math></inline-formula>/I<inline-formula> <tex-math>${}_{mathrm {OFF}} gt 10^{{6}}$ </tex-math></inline-formula>, excellent ohmic behavior, and ideal transfer characteristics. Temperature dependence of <inline-formula> <tex-math>$I_{text {D}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V_{text {G}}$ </tex-math></inline-formula> characteristics showed highly stable <inline-formula> <tex-math>$V_{text {TH}}$ </tex-math></inline-formula>, while the <inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula> is affected by the activation of the Mg dopants. Finally, a model for channel mobility was developed, resulting in an effective hole mobility of ~0.6 cm<inline-formula> <tex-math>${}^{{2}} cdot $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}^{-{1}} cdot $ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>. The results prove that the Mg-diffusion-enhanced ohmic contacts are extremely effective in enabling future p-channel GaN devices for fully GaN CMOS devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5167-5172"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11616627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact Model for Accurate Decoupling of Interface and Buffer Traps in HEMTs","authors":"Fanyuan Zhang;Xu Hou;Aoran Fan;Juan Xue;Fengyi Li;Weigang Ma;Xing Zhang","doi":"10.1109/TED.2026.3707131","DOIUrl":"https://doi.org/10.1109/TED.2026.3707131","url":null,"abstract":"This work proposes a physics-based compact modeling framework for the frequency dispersion of gate capacitance in AlGaN/gallium nitride (GaN) high-electron-mobility transistors (HEMTs), enabling capacitance–voltage (C–V) decoupling and an accurate analysis of interface and buffer traps. An improved buffer trap charge model is developed by partitioning the buffer layer into a near-interface region, described by a triangular potential well, and a far region, treated via the integration of Poisson’s equation and Gauss’s law. Incorporating this static charge model with Shockley-Read-Hall (SRH) statistics and the Lehovec admittance formalism, a unified capacitance dispersion framework is established by decomposing the intrinsic gate capacitance into barrier, 2DEG, and trap components, with distinct time constants derived for buffer and interface traps. Validated against TCAD simulations and experimental measurements across a wide range of frequencies and gate biases, the model achieves excellent agreement (4.59% versus TCAD and 1.66% versus measurements). This model provides a clear physical picture for trap characterization while remaining structurally compatible with circuit-level implementation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4717-4723"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Threshold Voltage E-Mode MIS-HEMTs on 6-in GaN-on-Si: Fully Recessed Gate With N2/O2 Plasma Treatment","authors":"Qingyuan Zuo;Xin Xia;Huolin Huang;Yun Lei;Jianxun Dai;Wei Li;Yanliang Qiu;Xinyang Wang;Kainan Wang;Kaiming Ma;Yung C. Liang","doi":"10.1109/TED.2026.3705020","DOIUrl":"https://doi.org/10.1109/TED.2026.3705020","url":null,"abstract":"To enhance the performance of enhancement-mode metal-insulator-semiconductor high-electron-mobility transistors with a fully etched gate barrier, this work comparatively investigates various plasma treatment schemes. The complete etching of the AlGaN barrier exposes the underlying GaN channel, making device performance highly dependent on interface quality, and thus necessitating a low-damage plasma treatment. Conventional N- or F- based plasmas induce additional interface damage, whereas the proposed N₂/O₂ mixed plasma treatment effectively mitigates plasma-induced defects, leading to surface states suppression and dielectric/semiconductor interface quality enhancement. After annealing, the surface roughness approaches that of the as-grown epitaxial wafer. Comprehensive characterizations of untreated, N₂/O₂, and O₂ treated devices reveal that the N₂/O₂ plasma treatment yields superior performance metrics, including reduced <sc>on</small>-resistance, enhanced gate controllability, and elevated breakdown voltage (BV), alongside minimized threshold voltage shift and suppressed dynamic <sc>on</small>-resistance degradation, thus significantly improving device reliability. Particularly, the <sc>off</small>-state drain–source BV was enhanced from 1003 to 1428 V, confirming the N₂/O₂ mixed plasma treatment as a highly promising strategy for performance optimization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4700-4707"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Radiation Detection Performance of Gamma Rays From Melt- and Solution-Grown Inorganic Perovskite CsPbBr3 Semiconductor Detectors","authors":"Bao Xiao;Yuquan Wang;Haoming Qin;Wenjie Chen;Xuchang He;Jun Du;Nannan Shen;Qihao Sun;Yihui He","doi":"10.1109/TED.2026.3695836","DOIUrl":"https://doi.org/10.1109/TED.2026.3695836","url":null,"abstract":"Perovskite CsPbBr₃ has emerged as a promising room-temperature semiconductor radiation detector, synthesizable via both melt- and solution-growth methods. Herein, we systematically compare the <inline-formula> <tex-math>$gamma $ </tex-math></inline-formula>-ray detection performance of CsPbBr₃ crystals grown by inverse temperature crystallization (ITC) and vertical Bridgman (VB) method. ITC-grown crystals exhibit relatively low optical transmittance of ~65%, a short photoluminescence (PL) lifetime of ~6.07 ns, moderate resistivity of <inline-formula> <tex-math>$6.06times 10^{{9}}~Omega {cdot }text {cm}$ </tex-math></inline-formula>, and a limited <sc>on–off</small> ratio of ~350. In contrast, VB-grown crystals show markedly improved optoelectronic properties, including higher transmittance (75%~80%), a much longer PL lifetime (~36.75 ns), higher resistivity (<inline-formula> <tex-math>$1.08times 10^{{10}}~Omega {cdot }text {cm}$ </tex-math></inline-formula>), and a significantly enhanced <sc>on–off</small> ratio (~5300). These improvements indicate higher crystal quality and reduced defect density in VB-grown CsPbBr₃ crystals, leading to more efficient charge transport. Notably, the average hole mobility and mobility-lifetime product increase from 5.36 cm<inline-formula> <tex-math>${}^{{2}}{cdot }text {V}^{-{1}}{cdot }text {s}^{-{1}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$4.45times 10^{-{4}}~text {cm}^{{2}}{cdot }text {V}^{-{1}}$ </tex-math></inline-formula> to 24.87 cm<inline-formula> <tex-math>${}^{{2}}{cdot }text {V}^{-{1}}{cdot }text {s}^{-{1}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$3.58times 10^{-{3}}~text {cm}^{2}{cdot }text {V}^{-{1}}$ </tex-math></inline-formula>, respectively. Accordingly, asymmetric Au/CsPbBr₃/EGaIn detectors fabricated from VB-grown crystals deliver excellent average energy resolutions (ERs) of ~9.8% and ~5.5% for ²⁴¹Am and ⁵⁷Co <inline-formula> <tex-math>$gamma $ </tex-math></inline-formula>-ray sources, respectively, along with superior detector uniformity, whereas ITC-based detectors exhibit only moderate ERs of ~29.6% and ~22.6%. These results suggest that melt-grown CsPbBr₃ crystals are more favorable for high-performance <inline-formula> <tex-math>$gamma $ </tex-math></inline-formula>-ray detectors applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4986-4992"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Channel-Implantation-Induced Doping Morphology on SiC UMOSFETs","authors":"Chenyu Wang;Yu Zhou;Yibo Zhang;Fengyu Du;Jingkai Guo;Haohang Yang;Boyi Bai;Binbin Ding;Zhiwen Zhang;Hao Yuan;Xiaoyan Tang;Chao Han;Yuming Zhang;Qingwen Song","doi":"10.1109/TED.2026.3703376","DOIUrl":"https://doi.org/10.1109/TED.2026.3703376","url":null,"abstract":"The impact of channel-implantation-induced deep gradient-doped (DGD) gate-oxide shielding on 4H-silicon carbide (SiC) UMOSFETs is systematically investigated, with particular emphasis on the resulting doping distribution and morphology. Channel implantation forms a deep P-type shielding region with a pronounced low-doped tail and an inverted-trapezoidal doping profile through a simplified process. TCAD simulations reveal that this intrinsic doping profile enables effective shielding of the gate oxide electric field while simultaneously modulating the vertical bulk electric field in the blocking state, thereby enhancing the voltage-sustaining capability of the P-type region and alleviating electric-field crowding at the p-n junction edge. As a result, compared with conventionally implanted dual-trench UMOSFETs (DT-UMOSFETs), SiC UMOSFETs employing the DGD shielding structure achieve a 24.5% increase in breakdown voltage and a 4% reduction in specific <sc>on</small>-resistance, yielding a 61.4% improvement in Baliga’s figure of merit (BFOM). Owing to the intrinsically lower specific <sc>on</small>-resistance, the associated parasitic capacitance penalty remains limited when compared at the same resistance class. To validate the simulation trends, DGD-UMOSFET devices were fabricated and experimentally characterized. Benchmark comparisons further indicate that UMOSFETs employing channel-implantation-formed gate-oxide shielding structures can achieve competitive BFOM values within the reported performance landscape of advanced SiC power MOSFET technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4679-4685"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multidimensional Theory of Charge Partitioning in Semiconductor Devices","authors":"Kejun Xia","doi":"10.1109/TED.2026.3689084","DOIUrl":"https://doi.org/10.1109/TED.2026.3689084","url":null,"abstract":"We present a multidimensional theory (2-D or 3-D) for charge partitioning in semiconductor devices with an arbitrary number of terminals, extending the well-known 1-D Ward–Dutton (WD) theory and its derivatives. The charge partitioning factors are governed by differential equations subject to appropriate boundary conditions. When the conductivity depends explicitly only on voltage, we show that the partitioning factors can be interpreted in terms of either voltage distribution or current splitting in a companion device with homogeneous conductivity, which is simpler than the original device. As illustrative applications, closed-form solutions are derived for 2-D circular MOSFETs, 3-D cylindrical through-silicon vias (TSVs), and 3-D spherical BJTs. The analysis is further extended to account for field-dependent mobility and position-dependent conductivity.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4724-4731"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerated Modeling of Parasitic Effect and Electromigration-Aware Reliability Evaluation for Interconnects in RRAM-Based Crossbar Array","authors":"Wenbo Wang;Siwei Tan;Yizhang Liu;Hao Xie;Lunyao Wang;Yinshui Xia;Wenchao Chen","doi":"10.1109/TED.2026.3703390","DOIUrl":"https://doi.org/10.1109/TED.2026.3703390","url":null,"abstract":"The parasitic effects and reliability challenges in resistive random access memory (RRAM) crossbar arrays are critical factors constraining the computational accuracy of in-memory computing (IMC) systems. In this work, the characteristics of electromigration-induced void formation are investigated through multiphysics simulations that couple electrical, thermal, and stress effects, and the reliability is assessed by tracking the temporal evolution of interconnect resistance. To enhance the efficiency of parasitic parameter extraction, a ResNet-based neural network is developed for predicting <italic>RLC</i> equivalent circuit parameters. In addition, the Partial Element Equivalent Circuit (PEEC) method is utilized instead of full-wave simulations, significantly accelerating the generation of datasets Finally, the reliability evolution characteristics of nanoscale interconnects are incorporated into a neural computing circuit composed of an RRAM crossbar array. Both the circuit’s output behavior for single-image inference and the temporal evolution of recognition accuracy on the MNIST test dataset are analyzed. This study provides an effective solution for parasitic parameter extraction and reliability evaluation in high-precision IMC systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5092-5098"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication and Emission Performance of Nanoscandia-Diffusion Cathode via Mechanical Fusion Coating Method","authors":"Zhiqian Yuan;Yan Li;Shixian Ding;Feng Ren;Xingqi Wang;Xiaoxia Wang;Xueliang He;Zenglin Zhou","doi":"10.1109/TED.2026.3700594","DOIUrl":"https://doi.org/10.1109/TED.2026.3700594","url":null,"abstract":"Vacuum microwave devices require cathode materials with high emission current density (<inline-formula> <tex-math>$ge$ </tex-math></inline-formula>50 A/cm²) and long operational lifetime. To address issues of poor emission uniformity and limited reproducibility in Sc₂O₃-W mixed-matrix cathodes, this study introduces a mechanical fusion coating process. Using classified tungsten powder (average size: <inline-formula> <tex-math>$3.8~mu $ </tex-math></inline-formula>m; span <inline-formula> <tex-math>$le 1.2$ </tex-math></inline-formula>), a uniform W@Sc₂O₃ structure nano-Sc₂O₃ coating (100–290 nm) was applied. This method eliminated Sc₂O₃ agglomeration and yielded a sintered matrix with closed porosity <inline-formula> <tex-math>$le 0.5$ </tex-math></inline-formula>%, a pore size of 0.6–<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>m, and carbon content <inline-formula> <tex-math>$le 400$ </tex-math></inline-formula> ppm. At <inline-formula> <tex-math>$1100~^{circ }text {C}_{text {b}}$ </tex-math></inline-formula>, the cathode achieved pulsed emission current densities of 149.86 A/cm² (1% duty cycle) and 81.36 A/cm² (5% duty cycle), representing a 108.1% improvement over planetary milled cathodes. The W@Sc₂O₃ increases specific surface area, supplying more active sites, while Sc₂O₃ migration to sintering necks enhances matrix stability. The uniform Sc₂O₃ distribution ensures consistent sintering shrinkage, enabling batch-suitable cathodes with high structural stability and machinability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5173-5178"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Maximum Process Temperature on Negative Bias Temperature Instability in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors","authors":"Chia-Chuan Wu;William Cheng-Yu Ma;Ting-Chang Chang;Hong-Yi Tu;Ya-Ting Chien;Han-Yu Chang;Bo-Shen Huang;Su-Wen Yang","doi":"10.1109/TED.2026.3708821","DOIUrl":"https://doi.org/10.1109/TED.2026.3708821","url":null,"abstract":"This study investigates the effect of the maximum process temperature on bias-temperature-instability-like degradation in p-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). Devices fabricated at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C, <inline-formula> <tex-math>$370~^{circ }$ </tex-math></inline-formula>C, and <inline-formula> <tex-math>$350~^{circ }$ </tex-math></inline-formula>C show comparable initial threshold voltage and subthreshold swing owing to the identical process flow and postfabrication hydrogen annealing. Under negative gate bias temperature stress, lower process-temperature devices exhibit a larger threshold voltage shifts, stronger subthreshold swing degradation, and lower extracted the effective activation energy. These results indicate that maximum process temperature has a limited impact on the initially observable threshold voltage and subthreshold swing, but critically affects long-term reliability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5293-5296"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}