IEEE Transactions on Electron Devices最新文献

{"title":"Cu–Cu Bonded Microbump Interconnects With a 10-μm Pitch for 3-D-Stacked Chiplets","authors":"Zilin Wang;Ziqing Wang;Zheyao Wang","doi":"10.1109/TED.2024.3469914","DOIUrl":"https://doi.org/10.1109/TED.2024.3469914","url":null,"abstract":"This article reports the fabrication and test results of fine-pitch microbump interconnects for stacked chiplets fabricated using a new Cu–Cu bonding method that is developed from Cu–Sn transient-liquid-phase (TLP) bonding. A redox treatment method is devised to change conventional Cu–Sn bumps to porous Cu–Sn bumps that can initiate TLP bonding by forming porous Cu–Sn intermetallic compounds (IMCs). The porous Cu–Sn bonding is changed to dense Cu–Cu bonding by removing the Sn composition using redox reactions and compressing the porous bumps using bonding pressures. The method inherits the merits of low resistivity and high reliability from Cu bonding and low temperature, low pressure, and free of chemical-mechanical planarization (CMP) from TLP bonding. The formation mechanism and the bonding model of the porous bumps are proposed, and the process details are given. The bonding of \u0000<inline-formula> <tex-math>$1000times 800$ </tex-math></inline-formula>\u0000 microbump array with a \u0000<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>\u0000 m pitch has been demonstrated for chiplet interconnects. The results show that the bonded microbumps have high yield, low resistance, and high reliability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6963-6969"},"PeriodicalIF":2.9,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Area and Energy-Efficient Quantum Tunneling-Based Thermal Sensor on 45nm RFSOI Technology","authors":"Shubham Patil;Abhishek Kadam;Jay Sonawane;Shreyas Deshmukh;R. Gaurav;Ajay Kumar Singh;Sandip Lashkare;Veeresh Deshpande;Laxmeesha Somappa;Udayan Ganguly","doi":"10.1109/TED.2024.3469177","DOIUrl":"https://doi.org/10.1109/TED.2024.3469177","url":null,"abstract":"The compact and energy-efficient integrated temperature sensors are crucial for temperature monitoring and control. In this work, we propose a novel area and energy-efficient band-to-band tunneling (BTBT)-based oscillator for temperature sensing applications. It utilizes oscillation frequency as a metric for temperature sensing. The linearity in BTBT current with temperature can enable sensing with a simple readout mechanism. The initially designed circuit is simulated and analyzed in TCAD using mixed-mode simulation, followed by the fabrication of the proposed circuit using GF 45nm RFSOI technology. Measurements show the BTBT oscillator’s quasi-linear response as a function of temperature. Our proposed work enables the area (\u0000<inline-formula> <tex-math>$0.32~mu text { m}^{{2}}$ </tex-math></inline-formula>\u0000) and energy-efficient temperature sensor (2.5 fJ/cycle) for the energy and area-constraint edge applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7208-7212"},"PeriodicalIF":2.9,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"N-Type Low-Temperature Polycrystalline Silicon and Amorphous Oxide Thin-Film Transistor-Based Robust Dual-Output Gate Driver","authors":"Chih-Lung Lin;Chung-Tien Chiu;Li-Wei Shih;Yi-Chien Chen;Chia-Ling Tsai;De-Lin Shih;Po-Cheng Lai","doi":"10.1109/TED.2024.3466838","DOIUrl":"https://doi.org/10.1109/TED.2024.3466838","url":null,"abstract":"This work presents a dual-output gate driver that is based on low-temperature polycrystalline silicon and amorphous oxide (LTPO) thin-film transistors (TFTs) and supports bidirectional transmission. This gate driver generates positive and negative pulses for both n-type and p-type switching TFTs in display pixels, effectively reducing the bezel area. Simulation results indicate that the output waveforms remain undistorted even when the threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000) of low-temperature polycrystalline silicon (LTPS) TFTs varies by ±0.46 V and the \u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000 of the amorphous indium gallium zinc oxide (a-IGZO) TFTs shifts by +0.56 V. This gate driver achieves short rising/falling times of approximately 1.25/\u0000<inline-formula> <tex-math>$1.42~mu $ </tex-math></inline-formula>\u0000s for a positive pulse and 1.55/\u0000<inline-formula> <tex-math>$2.73~mu $ </tex-math></inline-formula>\u0000s for a negative pulse through the output circuit composed of LTPS TFTs during forward transmissions. When operated at 1 Hz, the output waveforms are correctly generated and stabilized at +6.6 V and −6.6 by the stabilization circuit, which includes a-IGZO TFTs. Therefore, the proposed gate driver is promising for use in low-frame-rate smartwatch displays.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6769-6773"},"PeriodicalIF":2.9,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stimulated Secondary Emission of Single-Photon Avalanche Diodes","authors":"Kurtis Raymond;Fabrice Retière;Harry Lewis;Andrea Capra;Duncan McCarthy;Austin de St Croix;Giacomo Gallina;Joe McLaughlin;Juliette Martin;Nicolas Massacret;Paolo Agnes;Ryan Underwood;Seraphim Koulosousas;Peter Margetak","doi":"10.1109/TED.2024.3469918","DOIUrl":"https://doi.org/10.1109/TED.2024.3469918","url":null,"abstract":"Large-area next-generation physics experiments rely on using silicon photomultiplier (SiPM) devices to detect single photons, which trigger charge avalanches. The noise mechanism of external crosstalk occurs when secondary photons produced during a charge avalanche escape from an SiPM and trigger other devices within a detector system. This work presents measured spectra of the secondary photons emitted from the Hamamatsu VUV4 and Fondazione Bruno Kessler (FBK) VUV-HD3 SiPMs stimulated by laser light, near operational voltages. This work describes the microscope for the injection and emission of light (MIEL) setup, which is an experimental apparatus constructed for this purpose. Measurements have been performed at a range of overvoltage values and temperatures from 86 to 293 K. The number of photons produced per avalanche at the source is calculated from the measured spectra and determined to be \u0000<inline-formula> <tex-math>${49}pm {10}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${61}pm {11}$ </tex-math></inline-formula>\u0000 photons produced per avalanche for the VUV4 and VUV-HD3, respectively, at 4-V overvoltage. No significant temperature dependence is observed within the measurement uncertainties. The overall number of photons emitted per avalanche from each SiPM device is also reported.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6871-6879"},"PeriodicalIF":2.9,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Aluminum Capping-Induced Enhancement of Electrical Performance and Stability in Zinc Tin Oxide Thin-Film Transistors via a Low-Resistance Electron Pathway","authors":"Jinwoo Lee;So-Young Bak;Se-Hyeong Lee;Hyeongrok Jang;Moonsuk Yi","doi":"10.1109/TED.2024.3469162","DOIUrl":"https://doi.org/10.1109/TED.2024.3469162","url":null,"abstract":"We present a ZnSnO (ZTO) thin-film transistor (TFT) with enhanced mobility, achieved through the incorporation of a metal-capping layer. The fabrication of the ZTO active layer involves the deposition of a ZnO incubation layer, followed by super cycles of depositing ZnO and SnO2 layers through atomic layer deposition (ALD). An additional 60-nm-thick Al layer between the source and drain serves as a metal-capping layer and forms a conductive region. Rich in free electrons and located in the back channel away from the gate insulator, the conductive region leads to a primary ON-current path, thereby improving electrical characteristics and stability. Thus, the Al-capped ZTO TFT with a capping length of \u0000<inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>\u0000m exhibits decent performance with a saturation mobility of 16.89 cm2/V\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000s, a threshold voltage of 0.81 V, a subthreshold swing (SS) of 0.59 V/dec, and an ON/OFF current ratio over 107. Moreover, it exhibits a minimal threshold voltage shift of 0.9 V in the positive bias test and −0.14 V in the negative bias stress test. On ALD-based ZTO TFTs, these results demonstrate the applicability of the Al-capping method, which successfully overcomes the tradeoff between mobility improvement and bias stability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6788-6794"},"PeriodicalIF":2.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Channel Mobility With Higher-k Doped-HfO₂ for CMOS Logic","authors":"Song-Hyeon Kuk;Kyul Ko;Bong Ho Kim;Hyeong-Rak Lim;Joon Pyo Kim;Jae-Hoon Han;Sang-Hyeon Kim","doi":"10.1109/TED.2024.3466843","DOIUrl":"https://doi.org/10.1109/TED.2024.3466843","url":null,"abstract":"The integration of higher dielectric constant (higher-k) gate oxides, such as doped-HfO2, in field-effect-transistors (FETs) has gained attention for further reducing the equivalent oxide thickness (EOT) in the advanced CMOS technology. However, the gate oxide in the MOSFET should be carefully selected considering the enhancement of the inversion carrier surface density (\u0000<inline-formula> <tex-math>${N}_{text {s}, text {inv}}$ </tex-math></inline-formula>\u0000) and channel mobility (\u0000<inline-formula> <tex-math>$mu _{text {ch}}$ </tex-math></inline-formula>\u0000), which has been a less concern in doped-HfO2. We study \u0000<inline-formula> <tex-math>$mu _{text {ch}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${N}_{text {s}, text {inv}}$ </tex-math></inline-formula>\u0000 in higher-k n-/p-channel FET (n/pFET) through gated-Hall measurement. Importantly, \u0000<inline-formula> <tex-math>$mu _{text {ch}}$ </tex-math></inline-formula>\u0000 is not degraded by higher-k doped-HfO2, unlike conventional integrations of high-k gate oxides. This finding shows that using higher-k doped-HfO2 for the gate oxide promises a potential for achieving higher drain current without mobility degradation and without reducing the gate oxide thickness, compared to paraelectric HfO2.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6534-6538"},"PeriodicalIF":2.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the Effect of Low-Energy Electron Irradiation in the RF Responsivity of GaN Nanodiodes","authors":"Elsa Pérez-Martín;Ignacio Íñiguez-de-la-Torre;Tomás González;Javier Mateos","doi":"10.1109/TED.2024.3469915","DOIUrl":"https://doi.org/10.1109/TED.2024.3469915","url":null,"abstract":"Nanodevices are intrinsically strongly influenced by the surrounding environment due to their large surface-to-volume ratio. In this brief, we explore the impact of exposing GaN nanodiodes to a scanning electron microscope (SEM), affecting their dc behavior by reducing the current level, as well as their ac response by modifying the frequency dependence of their voltage responsivity to millimeter waves up to 43.5 GHz. The experiments were performed in a wide range of temperatures from 30 to 300 K. The irreversible changes induced by the low-energy electron irradiation of the SEM beam in the occupation of the traps located at the channel sidewalls, and the accumulation of negative charge within the native oxide filling the trenches, have been found as the responsible of the enhancement of the room temperature responsivity at high frequency and the reduction of the low-frequency dispersion at low temperature.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7192-7194"},"PeriodicalIF":2.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Turn-On Voltage and Reverse Leakage Current β -Ga2O3 MIS Schottky Barrier Diodes With an AlN Interfacial Layer","authors":"Zifan Hong;Chuanlun Zhang;Jialong Lin;Jianxun Dai;Jie Zhang;Huolin Huang;Weifeng Yang","doi":"10.1109/TED.2024.3469909","DOIUrl":"https://doi.org/10.1109/TED.2024.3469909","url":null,"abstract":"We demonstrate for the first time a vertical metal/AlN/\u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-gallium oxide (\u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3) metal-insulator–semiconductor (MIS) Schottky barrier diode (SBD) with low turn-on voltage (\u0000<inline-formula> <tex-math>${V}_{text {on}}$ </tex-math></inline-formula>\u0000) and reverse leakage current. By employing an ultrathin AlN layer enabled by atomic layer deposition (ALD), the resulting AlN/\u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 MIS SBD exhibits a remarkably low leakage current of \u0000<inline-formula> <tex-math>$0.1~mu $ </tex-math></inline-formula>\u0000A/cm2, which is three orders of magnitude smaller than that of the conventional \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 SBD. Meanwhile, the AlN/\u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 MIS SBD shows a significantly improved breakdown voltage from 208 V up to 890 V, while maintaining a relatively low \u0000<inline-formula> <tex-math>${V}_{text {on}}$ </tex-math></inline-formula>\u0000 of 0.92 V and \u0000<sc>on</small>\u0000-resistance (\u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000) of 11.8 m\u0000<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>\u0000cm2, respectively. I–V measurements conducted across a range of temperatures from 298 to 432 K indicate that thermionic field emission (TFE) and trap-assisted tunneling (TAT) are the predominant electron transport mechanisms under forward bias if inserting 2 nm AlN, while TFE becomes dominant mechanism when the AlN thickness increases up to 5 nm. X-ray photoelectron spectroscopy (XPS) characterizations reveal the type I alignment for AlN/\u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 heterojunction with a large conduction band offset (\u0000<inline-formula> <tex-math>$Delta {E}_{C}$ </tex-math></inline-formula>\u0000) of 1 eV, which could function as an electron transport barrier under reverse conditions, thereby greatly suppressing the leakage current. Our study for the first time suggests a great potential for ALD-derived AlN films to be an interfacial layer in \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 SBDs and the AlN/\u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 SBDs with state-of-art performances open up more opportunities in future power electronics.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6934-6941"},"PeriodicalIF":2.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part II: Adaptive Layer-Wise Refresh Technique","authors":"Chan-Gi Yook;Wonbo Shim","doi":"10.1109/TED.2024.3469183","DOIUrl":"https://doi.org/10.1109/TED.2024.3469183","url":null,"abstract":"Two-transistor-zero-capacitor (2T0C) DRAM cell has been proposed and extensively investigated as a memory device for processing-in-memory (PIM) applications. In this two-part article, we propose a novel vertical-transistor on the gate (VTG) 2T0C DRAM cell structure and the refresh technique for PIM applications and demonstrate their effectiveness. We described the improved retention characteristics of VTG DRAM in Part I. In Part II, we introduce the adaptive layer-wise refresh technique to minimize refresh energy consumption while maintaining the inference accuracy. Additionally, we developed a customized simulation framework to evaluate the inference accuracy and hardware performance of the 2T0C DRAM-based PIM macro. Through the simulations reflecting the device characteristics extracted in Part I, the layer-wise refresh technique can achieve the same inference accuracy of 92% and 91%, with refresh energy consumption reduced by 22.9% and 16% respectively, compared to the conventional refresh method.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6639-6646"},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A True Random Number Generator Based on High-Speed Ag/a-Si/Pt Memristor","authors":"Zhenqiang Guo;Ziliang Fang;Jiangzhen Niu;Haiyun Wang;Lei Yan;Liang Tong;Jianhui Zhao;Saibo Yin;Shiqing Sun;Feng Li;Hongfang Wang;Jianhui Chen;Xiaobing Yan","doi":"10.1109/TED.2024.3454588","DOIUrl":"https://doi.org/10.1109/TED.2024.3454588","url":null,"abstract":"The inherent variability in memristor switching behavior has been a challenge to its adoption as a next-generation general-purpose memory. However, the randomness of its switching behavior may be helpful for hardware security applications. Herein, a true random number generator (TRNG) based on a high-speed Ag/amorphous-Si/Pt threshold switching (TS) device was constructed. The device possesses a large on-off ratio of about \u0000<inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula>\u0000 and a fast switching speed of about 30 ns. The results show that the delay time of the device decreases as the pulse amplitude or the pulse frequency increases. Using the random delay time as a random source, we built a TRNG circuit and achieved the flipping of “0” and “1” with a fast bit generation rate of 48 kb/s. The random bits generated by our TRNG pass 14 randomness tests of the National Institute of Standards and Technology (NIST) without any processing. This work paves the way for diffusive memristors in hardware security applications in the era of the Internet of Things.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7126-7130"},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}