IEEE Transactions on Electron Devices最新文献

{"title":"Gate-Stack Engineering With Al2O3 Interlayer for Enhanced Memory Performance in HfZrOx FeFETs","authors":"Qiuxia Wu;Yue Peng;Litao Sun;Shuo Zhang;Shouchen Yang;Zhen Zhang;Yue Zhao;Chunfu Zhang;Xuefeng Zheng;Xiaohua Ma;Yue Hao","doi":"10.1109/TED.2026.3716995","DOIUrl":"https://doi.org/10.1109/TED.2026.3716995","url":null,"abstract":"A systematic comparison is carried out between two interfacial engineering schemes in HfO2-based ferroelectric field-effect transistors (FeFETs): inserting Al2O3 at the channel/ferroelectric interface (type-I, MFAIS) and at the gate/ferroelectric interface (type-II, MAFIS). Under symmetric and asymmetric program/erase (PGM/ERS) operations, type-II engineering significantly enlarges the memory window (MW) (>2 V) and suppresses state asymmetry, while type-I engineering promotes negative-capacitance-like behavior and enhances switching characteristics. Polarization and band analysis indicate that MAFIS FeFETs exhibit a more symmetric coercive voltage (<inline-formula> <tex-math>${V}_{text {c}}text {)}$ </tex-math></inline-formula> and a reduced internal bias field (<inline-formula> <tex-math>${E}_{text {bias}}text {)}$ </tex-math></inline-formula>, leading to improved memory state symmetry. The enlarged MW is further attributed to charge trapping in the gate-side Al2O3 layer, which mitigates trap-induced disturbances in the channel. Type-II devices also demonstrate superior retention stability up to <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula> s and improved endurance characteristics up to <inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula> cycles at room temperature (RT). These results provide guidance for interface design in FeFET logic and memory applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5547-5553"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Crystal-Face-Dependent Electron Mobility Due to Distinct Interface Trap Distributions in SiC n-Channel MOSFETs","authors":"Xilun Chi;Koji Ito;Kyota Mikami;Mitsuaki Kaneko;Tsunenobu Kimoto","doi":"10.1109/TED.2026.3709762","DOIUrl":"https://doi.org/10.1109/TED.2026.3709762","url":null,"abstract":"In this study, we investigated the electron trapping and scattering mechanisms in SiC (<inline-formula> <tex-math>$boldsymbol {mathsf {11overline {2}0}}$ </tex-math></inline-formula>) and (<inline-formula> <tex-math>$boldsymbol {mathsf {1overline {1}00}}$ </tex-math></inline-formula>) n-channel MOSFETs. Body-bias measurements revealed that the interface trap density distributions in these non-polar devices do not exhibit an energetic shift with increasing effective normal field near the interface, in contrast to the behavior observed in the (0001) devices. It was found that the fixed charge density near non-polar MOS interfaces is on the order of <inline-formula> <tex-math>$boldsymbol {mathsf {textbf {10}^{textbf {12}} textbf {cm}^{-textbf {2}}}}$ </tex-math></inline-formula> and increases with increasing p-body doping concentration, while its absolute value is smaller than that observed in (0001) devices. Numerical calculation of free electron mobility (<inline-formula> <tex-math>$boldsymbol {{mathsf {mu _{free}}}}$ </tex-math></inline-formula>) was performed using the physical model we recently developed. The calculated results successfully reproduced the experimental Hall mobilities over 200–400 K. It was revealed that Coulomb scattering due to fixed charges is the dominant mobility-limiting factor in non-polar devices. The higher <inline-formula> <tex-math>$boldsymbol {{mathsf {mu_{free}}}}$ </tex-math></inline-formula> in (<inline-formula> <tex-math>$boldsymbol {mathsf {11overline {2}0}}$ </tex-math></inline-formula>) and (<inline-formula> <tex-math>$boldsymbol {mathsf {1overline {1}00}}$ </tex-math></inline-formula>) MOSFETs is mainly attributed to the reduced impact of scattering by trapped electrons and surface roughness, as a result of the distinct distributions of interface traps in polar and non-polar devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5428-5436"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact Dynamic On-State Resistance Model for GaN-HEMTs in Soft-Switching Operation","authors":"Mathias C. J. Weiser;David Miller;Michael Bosch;Dominik Koch;Jeremy Nuzzo;Ingmar Kallfass","doi":"10.1109/TED.2026.3716193","DOIUrl":"https://doi.org/10.1109/TED.2026.3716193","url":null,"abstract":"We present a compact model that can accurately describe the trapping and detrapping dynamics inside gallium-nitride (GaN)-high electron mobility transistors (HEMTs) in soft-switching operation. The model is implemented in the Verilog-A hardware description language and is based on the physical description of trapping processes and utilizes a log-normal distribution of exponential decay functions to model the nonideal detrapping dynamics. Closed-form mathematical descriptions for the trapping and detrapping behavior for a wide range of temperatures and input voltages are derived. The model parameters are extracted for a commercial 650 V GaN-HEMT, and a model validation is carried out in continuous soft-switched operation. The model is able to predict the <sc>on</small>-state resistance in operation with an average error of 4.1 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> and less.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5493-5501"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sub-THz Characterization and Transient TCAD Modeling of SiGe HBTs: Collector Profile Optimization for Power Amplifiers","authors":"Arnab Saha;Raphaël Strenaer;Thomas Zimmer;Philippe Cathelin;Alexis Gauthier;Nicolas Guitard;Nathalie Deltimple;Sébastien Fregonese","doi":"10.1109/TED.2026.3716197","DOIUrl":"https://doi.org/10.1109/TED.2026.3716197","url":null,"abstract":"This article presents a comprehensive study of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) characterized up to 500 GHz, addressing the modeling challenges and design tradeoffs required for sub-THz power amplifier (PA) applications. We report broadband S-parameter measurements from 1 to 500 GHz, large-signal (LS) 3-GHz harmonic-balance measurements, alongside DC Gummel and output characteristics, for STMicroelectronics’ B55X technology node. These measurements are used to calibrate a computationally efficient quasi-2D technology computer-aided design (TCAD) model, showing excellent agreement across the frequency spectrum. Addressing the convergence limitations of conventional harmonic balance (HB) solvers under high-power conditions, we propose a robust LS simulation methodology utilizing transient analysis coupled with discrete Fourier transform (DFT). This methodology is applied to investigate the impact of modulating the collector region on the PA figures of merit (FoMs). By modulating the collector doping, we demonstrate the tradeoffs between breakdown voltage, linearity, and power added efficiency (PAE), identifying optimal doping profiles for next-generation sub-THz amplification.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5309-5317"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"540 V Fully Vertical GaN Bipolar Transistor With 99.5% Electron Transition Efficiency and 190 Current Gain by Base Engineering","authors":"Guangyang Gu;Jiawei Tan;Weizong Xu;Yu Zhou;Yaozong Zhong;Dong Zhou;Feng Zhou;Fangfang Ren;Qian Sun;Dunjun Chen;Rong Zhang;Youdou Zheng;Hai Lu","doi":"10.1109/TED.2026.3716677","DOIUrl":"https://doi.org/10.1109/TED.2026.3716677","url":null,"abstract":"A record-high current gain exceeding 190 is achieved in the fully vertical GaN bipolar transistor through base engineering in doping and composition. By incorporating 0.02 indium (In) composition into the p-GaN base layer, the acceptor activation ratio and minority carrier lifetime are significantly enhanced. Combined with gradient composition design for conduction band smoothing, an exceptional electron transition efficiency <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula> of 99.5% across the base and output current over 10 kA/cm2 under DC conditions are realized. The improved conductivity also ensures uniform electric field distribution, enabling a breakdown voltage of 540 V with leakage current down to <inline-formula> <tex-math>$10^{-{11}}$ </tex-math></inline-formula> A and simultaneously addressing the trade-off between current gain and breakdown voltage. Additionally, the device demonstrates fast dynamic switching within 711 ns, highlighting the potential of GaN bipolar transistors in fast and efficient power conversion applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5877-5880"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental Characterization of Dispersion and Phase Velocity in a Miniaturized Double-V Meander-Line Slow-Wave Structure","authors":"Giuseppe Paterna;Salvatore Stivala;Patrizia Livreri;F. Di Maggio;G. Li Calsi;R. Martorana;A. Mendolia Calella;Alessandro Busacca","doi":"10.1109/TED.2026.3717012","DOIUrl":"https://doi.org/10.1109/TED.2026.3717012","url":null,"abstract":"A very-low-voltage double V-shaped meander-line slow-wave structure (ML-SWS) for miniaturized traveling-wave tubes (TWTs) is presented and experimentally characterized. The proposed topology enables strong beam–wave interaction at cathode voltages below 2 kV while maintaining compact dimensions and full compatibility with planar microfabrication processes. The structure is designed to operate over the 17–21-GHz frequency range and to provide a nearly constant phase velocity suitable for low-voltage electron beams. A prototype composed of 40 unit cells was fabricated on an alumina substrate and characterized through cold-test measurements. The dispersion diagram and phase velocity were extracted from the measured phase of the <inline-formula> <tex-math>${S}_{{21}}$ </tex-math></inline-formula> parameter and compared with eigenmode and time-domain simulations, showing good agreement with discrepancies below 10%. Particle-in-cell simulations were subsequently carried out to evaluate the hot-test performance. At a cathode voltage of 1.425 kV and a beam current of 100 mA, the structure achieves a maximum gain of 34.1 dB and a peak beam–wave electronic efficiency of 18% at 18 GHz. With a slow-wave structure (SWS) volume of only 0.203 cm3, the proposed double V-shaped meander-line (ML)-SWS demonstrates high power density and represents a promising solution for compact, low-voltage TWTs intended for aerospace and space applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5766-5776"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Photoelectric Synergistic Modulation in Y2O3/IGZO Transistors Enabling In-Sensor Boolean Logic and Pattern Recognition","authors":"Haoran Wang;Jiajun Sun;Hainan Zhang;Shuo Cheng;Shanshan Jiang;Huanhuan Wei;Gang He","doi":"10.1109/TED.2026.3709778","DOIUrl":"https://doi.org/10.1109/TED.2026.3709778","url":null,"abstract":"This work presents a low-power optoelectronic synaptic transistor featuring an indium-gallium-zinc-oxide (IGZO) channel and a sol-gel-derived Y2O3 gate dielectric annealed at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C. The devices exhibit excellent electrical characteristics with a maximum deviation of no more than 220 mV, including a high <sc>on</small>/<sc>off</small> current ratio of <inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>, a steep subthreshold swing of 120 mV/dec, a field-effect mobility of 38.0 cm2/(V<inline-formula> <tex-math>${,}cdot $ </tex-math></inline-formula> s), a threshold voltage of 550 mV, and a low gate leakage current density down to <inline-formula> <tex-math>$10^{-{8}}$ </tex-math></inline-formula> A/cm2, and a low reading voltage (<inline-formula> <tex-math>$le $ </tex-math></inline-formula>1 V). The introduction of the high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> Y2O3 dielectric, coupled with the tailored modulation of oxygen vacancies at the IGZO interface, enables remarkable optoelectronic synergistic effects for energy-efficient synaptic emulation. Key synaptic plasticity behaviors are systematically realized by optically controlling the dynamic capture and release of carriers at the dielectric/channel interface. Furthermore, the device demonstrates multifunctional computing capabilities by mapping spatiotemporal optical/electrical pulses to synaptic weight updates, successfully implementing Boolean logic operations (<sc>and</small>/<sc>or</small>) within a single unit. Finally, a pattern recognition system built on experimentally derived nonlinear conductance updates achieves an accuracy of 96.26%, showcasing the device’s excellent fault tolerance and significant potential for future optoelectronic neuromorphic computing systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5783-5788"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using Rectifier Diodes as Photoconductive High-Voltage Switches for Pulse Generation: TCAD Modeling and Experimental Study","authors":"Lionel Michard;Philippe Leveque;Vincent Couderc;Delia Arnaud-Cormos","doi":"10.1109/TED.2026.3710683","DOIUrl":"https://doi.org/10.1109/TED.2026.3710683","url":null,"abstract":"An off-the-shelf rectifier diode (RD) is utilized as a high-voltage nanosecond closing switch by triggering transient photoconductivity. Compared to high-resistivity bulk silicon, structures made of PIN junction stacks allow withstanding significantly higher voltage biases with drastically lower dark current. In this work, a silicon-based RD is analyzed through secondary ion mass spectrometry (SIMS) and simulated using technology computer-aided design software (Charon TCAD). The assembled model was experimentally validated through basic electrical measurements, including current–voltage (<inline-formula> <tex-math>$I$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V$ </tex-math></inline-formula>) and capacitance–voltage (<inline-formula> <tex-math>$C$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V$ </tex-math></inline-formula>) characteristics. High-voltage photoconductive switching was achieved using a picosecond, millijoule Nd:YAG laser source. Voltage pulses with an amplitude up to 7.5 kV on <inline-formula> <tex-math>$50~Omega $ </tex-math></inline-formula> and a rise time of 0.2 ns were obtained with a 20-ns pulse-forming line (PFL) and compared with TCAD simulations as a function of the incident optical energy. Based on the simulation results, a discussion is provided regarding the influence of avalanche and recombination processes on the switching behavior. In addition, a modification of the doping profile of the RD under study is proposed to increase commutation efficiency in terms of optical energy. This study directly compares TCAD simulations of high-voltage transient photoconductivity in silicon diodes to experimental measurements.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5736-5744"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Chalcogen Chemistry on Transient Switching Dynamics in GeAsSe and GeAsTe Ovonic Threshold Switches","authors":"Nishant Saxena;Chengcheng Wang;Zeyu Hu;Guosheng Wang;Muhammad Naqi;Linxi Zhang;Weidong Zhang;Zheng Chai;Daniele Garbin;Robin Degraeve;Sergiu Clima;Taras Ravsher;Attilio Belmonte","doi":"10.1109/TED.2026.3716191","DOIUrl":"https://doi.org/10.1109/TED.2026.3716191","url":null,"abstract":"Ovonic threshold switch (OTS) devices are used as selectors for emerging nonvolatile memory and neuromorphic computing applications, where their performance and reliability are strongly governed by defect states and carrier localization dynamics. In this work, we present a comparative investigation of GeAsSe and GeAsTe OTS devices to elucidate the impact of chalcogen chemistry on trap energy barriers, defect density, localization kinetics, and overall switching behavior. By combining characterizations with DC, ultrafast pulse, and double-pulse techniques across nanoseconds-to-seconds timescales, we show that material composition affects the localized states, which in turn set the characteristic energy barriers for both field-assisted and thermal-assisted delocalization, and control the leakage current, threshold voltage (V<inline-formula> <tex-math>${}_{text {th}}text {)}$ </tex-math></inline-formula>, and recovery dynamics. GeAsSe devices exhibit lower leakage, improved on/off selectivity, and lower recovery-induced Vth shift due to larger delocalization energy, while GeAsTe devices show lower switching field (F<inline-formula> <tex-math>${}_{text {th}}text {)}$ </tex-math></inline-formula>, and higher <sc>on</small>-state current, leading to more field-driven and thermal-assisted delocalized defects. These insights establish a direct link between defect energetics and device performance, offering material-level guidelines for OTS optimization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5540-5546"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Analysis of Nanosheet FET With Asymmetric Dual-κ Inner Spacer in DC and RF Perspective","authors":"Sangmin Lee;Hyunwoo Kim","doi":"10.1109/TED.2026.3711635","DOIUrl":"https://doi.org/10.1109/TED.2026.3711635","url":null,"abstract":"In this work, we propose a nanosheet field effect transistor (NSFET) with an asymmetric dual-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> inner spacer structure (<inline-formula> <tex-math>${mathrm{NSFET}}_{text {ADIS}}$ </tex-math></inline-formula>) to improve DC/RF performance. To rigorously evaluate its benefits, we benchmark NSFETADIS against two References: NSFET with a conventional fully nitride inner spacer (<inline-formula> <tex-math>${mathrm{NSFET}}_{text {Conv}}$ </tex-math></inline-formula>) and NSFET with a symmetric dual-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> inner spacer (<inline-formula> <tex-math>${mathrm{NSFET}}_{text {SDIS}}$ </tex-math></inline-formula>), utilizing 3-D technology computer-aided design (TCAD) simulations. Consequently, the high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> inner spacer strengthens the gate fringe field, lowering the source-channel barrier and increasing transconductance. Moreover, by isolating the low-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> inner spacer from the channel extension and the inner gate, we alleviate its impact on the barrier lowering while simultaneously mitigating the increase in total gate capacitance (<inline-formula> <tex-math>${C}_{text {gg}}$ </tex-math></inline-formula>) associated with the high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> dielectric. Furthermore, we extract intrinsic delay, <sc>off</small> current (<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula>), cutoff frequency (<inline-formula> <tex-math>${F}_{text {t}}$ </tex-math></inline-formula>), and maximum oscillation frequency (<inline-formula> <tex-math>${F}_{max }$ </tex-math></inline-formula>) with respect to the high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> inner spacer thickness (<inline-formula> <tex-math>${T}_{text {IS, {h}}kappa }$ </tex-math></inline-formula>) and its material. In addition, the optimized NSFETSDIS and NSFETADIS were evaluated in terms of high-frequency switching operation, and their RF performance was further assessed by comparing the gain-bandwidth product (GBW) and voltage gain (<inline-formula> <tex-math>${A}_{text {v}}$ </tex-math></inline-formula>). As a result, compared with NSFETConv and NSFETADIS achieves an 11.18% reduction in intrinsic delay and a 19.21% increase in switching frequency under the same <inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula> and active power conditions. Regarding RF performance, <inline-formula> <tex-math>${F}_{text {t}},{F}_{max }$ </tex-math></inline-formula>, GBW, and <inline-formula> <tex-math>${A}_{text {v}}$ </tex-math></inline-formula> are enhanced by 10.8%, 14.99%, 14.35%, and 10.32%, respectively.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5373-5380"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}