IEEE Transactions on Electron Devices最新文献_第2页

Field-Emission Light Sources Based on Porous Silicon Planar Electron Emitter 基于多孔硅平面电子发射器的场发射光源

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-28 DOI: 10.1109/TED.2025.3562507

He Li;Li Sailei;He Qi;Sun Wenqi;Luo Wei;Shen Guiying

引用次数: 0

Addressing the Connectivity Bottleneck With BEOL FeFETs for 3-D CMOS + X Ising Machines 用BEOL效应管解决3-D CMOS + X成像机的连接瓶颈

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-28 DOI: 10.1109/TED.2025.3562510

Tanvir H. Pantha;Abhishek Khanna;Huacheng Ye;Shaila Niazi;Miriyala P. Kamal;Biswadeep Chakraborty;Shumiya Alam;Ethan Weinstock;Nithin Babu;Saibal Mukhopadhyay;Yun Chiu;Suman Datta;Kerem Y. Camsari;Sourav Dutta

{"title":"Addressing the Connectivity Bottleneck With BEOL FeFETs for 3-D CMOS + X Ising Machines","authors":"Tanvir H. Pantha;Abhishek Khanna;Huacheng Ye;Shaila Niazi;Miriyala P. Kamal;Biswadeep Chakraborty;Shumiya Alam;Ethan Weinstock;Nithin Babu;Saibal Mukhopadhyay;Yun Chiu;Suman Datta;Kerem Y. Camsari;Sourav Dutta","doi":"10.1109/TED.2025.3562510","DOIUrl":"https://doi.org/10.1109/TED.2025.3562510","url":null,"abstract":"Recent advancements in Ising machines present an exciting new paradigm for addressing computationally intensive problems with superior energy efficiency and speed compared to conventional digital computers. Despite these promising developments, many real-world problems demand high connectivity, a requirement that exceeds the capabilities of current CMOS-based Ising machine hardware. To overcome this connectivity bottleneck, we propose a novel approach leveraging programmable multibit back-end-of-line (BEOL) ferroelectric field-effect transistor (FeFETs) capable of monolithic 3-D stacking. We experimentally demonstrate a 10-node, 24-coupling Ising machine utilizing dual-gated BEOL FeFETs. This platform enables real-time reconfigurability and supports diverse computational workloads, including combinatorial optimization problems and energy-based learning. Our platform demonstrates robust error-resilient computation with minimal accuracy degradation, even under high endurance conditions of up to 10 billion read and write cycles. This resilience is critical for both read-intensive forward problems and write-intensive inverse or learning problems. To evaluate the performance and area gains, we benchmark the proposed FeFET-based architecture against traditional CMOS implementations. The results reveal significant advantages for FeFET technology, including an <inline-formula> <tex-math>$8.2times $ </tex-math></inline-formula> increase in coupling density, an <inline-formula> <tex-math>$11times $ </tex-math></inline-formula> improvement in energy efficiency, and a <inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula> reduction in latency.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3335-3342"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

One-Ferroelectric-Tunnel-FET-Based Reconfigurable Logic Gates 基于单铁电隧道场效应晶体管的可重构逻辑门

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-28 DOI: 10.1109/TED.2025.3561710

Jaemin Yeom;Minjeong Ryu;Jae Seung Woo;Jin Wook Lee;Seonggeun Kim;Seungwon Go;Sangwan Kim;Woo Young Choi

引用次数: 0

Physics-Based Compact Modeling for the Drain Current Variability in Single-Layer Graphene FETs 基于物理的单层石墨烯场效应管漏极电流变异性紧凑模型

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-28 DOI: 10.1109/TED.2025.3560616

Nikolaos Mavredakis;Anibal Pacheco-Sanchez;Ramon Garcia Cortadella;Anton-Guimerà-Brunet;Jose A. Garrido;David Jiménez

{"title":"Physics-Based Compact Modeling for the Drain Current Variability in Single-Layer Graphene FETs","authors":"Nikolaos Mavredakis;Anibal Pacheco-Sanchez;Ramon Garcia Cortadella;Anton-Guimerà-Brunet;Jose A. Garrido;David Jiménez","doi":"10.1109/TED.2025.3560616","DOIUrl":"https://doi.org/10.1109/TED.2025.3560616","url":null,"abstract":"For the growth of emerging graphene field-effect transistor (GFET) technologies, a thorough characterization of on-wafer variability is required. Here, we report for the first time a physics-based compact model, which precisely describes the drain current (<inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula>) fluctuations of monolayer GFETs. Physical mechanisms known to generate 1/f noise in transistors, such as carrier number and Coulomb scattering mobility fluctuations, are also revealed to cause <inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula> variance. Such effects are considered in the model by being activated locally in the channel and the integration of their contributions from source to drain results in total variance. The proposed model is experimentally validated from a statistical population of three different-sized solution-gated (SG) GFETs from strong p- to strong n-type bias conditions. A series resistance <inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula> variance model is also derived mainly contributing at high carrier densities.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3314-3321"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Monolithically Integrated Hydrogen-Terminated Diamond FET Logic Circuits 单片集成氢端金刚石场效应晶体管逻辑电路

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-28 DOI: 10.1109/TED.2025.3563146

Yuesong Liang;Wei Wang;Genqiang Chen;Fei Wang;Yuxiang Du;Minghui Zhang;Yanfeng Wang;Hong-Xing Wang

{"title":"Monolithically Integrated Hydrogen-Terminated Diamond FET Logic Circuits","authors":"Yuesong Liang;Wei Wang;Genqiang Chen;Fei Wang;Yuxiang Du;Minghui Zhang;Yanfeng Wang;Hong-Xing Wang","doi":"10.1109/TED.2025.3563146","DOIUrl":"https://doi.org/10.1109/TED.2025.3563146","url":null,"abstract":"Logic circuits are the first step toward integrated circuits. Here, we fabricated the monolithically E/R logic, direct coupled E/E logic, and E/D inverter logic circuit with respective loads of resistor, enhancement field-effect transistor (FET), and depletion FET using hydrogenated diamond and observed the performance of these logic circuits. The gain and voltage swing of E/R logic circuits are strongly influenced by the value of the load resistance, which are commonly employed in separate components. E/E logic circuit exhibits small voltage swing, low gain, and low noise margin. E/D logic circuits present significant advantages in terms of voltage swing, gain, noise margins, and power consumption over E/R and E/E logic circuits. The E/D mode circuit shows a logic voltage swing of −9.44 V, a voltage gain of 15.5 V/V, low-/high-noise margins of 0.82/7.07 V, and static power consumption of <inline-formula> <tex-math>$10^{-{3}}$ </tex-math></inline-formula> W and proper functions up to at least <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C at a supply voltage of −10 V. These results show great potential for diamond smart power integrated circuit application.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2834-2840"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Studies on Traveling Wave Tubes With the Bunching Mechanism of Resistive Wall and the Circuit-Field Synchronous Interaction 具有阻壁聚束机制的行波管及电场同步相互作用的研究

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-28 DOI: 10.1109/TED.2025.3560268

Yue Ouyang;Hairong Yin;Jinchi Cai;Dongdong Jia;Pengcheng Yin;Wuyang Fan;Lingna Yue;Jin Xu;Yong Xu;Yanyu Wei;Jun He;Hailong Wang

引用次数: 0

On the Capacitance of Nanosheet Transistors 纳米片晶体管的电容研究

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-24 DOI: 10.1109/TED.2025.3559482

L. Donetti;C. Medina-Bailon;J. L. Padilla;C. Sampedro;F. Gamiz

引用次数: 0

Reconfigurable Ge Transistors Enabling Adaptive Differential Amplifiers 可重构的Ge晶体管支持自适应差分放大器

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-24 DOI: 10.1109/TED.2025.3559912

Andreas Fuchsberger;Alexandra Dobler;Lukas Wind;Andreas Kramer;Julian Kulenkampff;Maximilian Reuter;Daniele Nazzari;Giulio Galderisi;Enrique Prado Navarrete;Johannes Aberl;Moritz Brehm;Thomas Mikolajick;Jens Trommer;Klaus Hofmann;Masiar Sistani;Walter M. Weber

{"title":"Reconfigurable Ge Transistors Enabling Adaptive Differential Amplifiers","authors":"Andreas Fuchsberger;Alexandra Dobler;Lukas Wind;Andreas Kramer;Julian Kulenkampff;Maximilian Reuter;Daniele Nazzari;Giulio Galderisi;Enrique Prado Navarrete;Johannes Aberl;Moritz Brehm;Thomas Mikolajick;Jens Trommer;Klaus Hofmann;Masiar Sistani;Walter M. Weber","doi":"10.1109/TED.2025.3559912","DOIUrl":"https://doi.org/10.1109/TED.2025.3559912","url":null,"abstract":"Exploiting the capabilities of multi-gated transistors is a promising strategy for adaptive and compensative analog circuits. Typically, reconfigurable transistors, which can be switched between n- and p-type operation at runtime, are used as universal transistors in fine grain programmable digital circuits. However, in the analog domain, by operating the transistors deliberately in intermediate states, they enable adjustments to application-specific requirements and allow for compensation of undesired deviations. Here, we propose a Ge-on-SOI transistor circuit primitive that enables an adaptable circuit design featuring n- and p-type common source (CS) and drain circuits, with electrostatically tuneable output-to-input ratio. Most notably, combined experimental and simulation studies promote verification and scalability assessment. Finally, the first experimental evidence of the electrostatic compensation of transistor/circuitpath-related device-to-device inequalities is shown in a differential amplifier featuring adaptable gain.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2868-2873"},"PeriodicalIF":2.9,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975300","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fabrication and Dark Current Analysis of InAsSb-Based nBn Structures for High-Performance Mid-Infrared Applications 用于中红外高性能应用的inassb基nBn结构的制备和暗电流分析

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-24 DOI: 10.1109/TED.2025.3560265

Bingfeng Liu;Lianqing Zhu;Lidan Lu;Weiqiang Chen;Ruixin Gong;Yang Chen;Mingli Dong

{"title":"Fabrication and Dark Current Analysis of InAsSb-Based nBn Structures for High-Performance Mid-Infrared Applications","authors":"Bingfeng Liu;Lianqing Zhu;Lidan Lu;Weiqiang Chen;Ruixin Gong;Yang Chen;Mingli Dong","doi":"10.1109/TED.2025.3560265","DOIUrl":"https://doi.org/10.1109/TED.2025.3560265","url":null,"abstract":"This study presents a comprehensive characterization and dark current analysis of InAsSb-based nBn structures for high operating temperature (HOT) mid-wavelength infrared (MWIR) applications. InAsSb layers with varying Sb compositions were grown by molecular beam epitaxy (MBE) to achieve lattice match and minimize dislocation density. High-resolution X-ray diffraction (HRXRD), atomic force microscopy (AFM), and reciprocal space mapping (RSM) were employed to assess crystal quality, strain relaxation, and surface morphology, demonstrating significant improvements with optimized growth conditions. The fabricated nBn photodetectors, featuring a lattice-matched AlAsSb barrier, exhibited a low dark current density of <inline-formula> <tex-math>$4.5times 10^{-{5}}$ </tex-math></inline-formula> A/cm2 at 130 K and <inline-formula> <tex-math>$2.6times 10^{-{4}}$ </tex-math></inline-formula> A/cm2 at 190 K. Blackbody-calibrated photocurrent spectroscopy confirmed that the InAsSb MWIR photodetectors exhibited excellent performance at 160 K, achieving peak quantum efficiency (QE) of 58%, a responsivity of 1.69 A/W, and a detectivity of <inline-formula> <tex-math>$2.13times 10^{{11}}$ </tex-math></inline-formula> cm Hz1/2/W at <inline-formula> <tex-math>$3.58~mu $ </tex-math></inline-formula>m, demonstrating their potential for high-temperature infrared detection applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3029-3034"},"PeriodicalIF":2.9,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced Writability of 4P4N CFET SRAM Cell With Transmission Gates 带传输门的4P4N fet SRAM单元的可写性增强

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-24 DOI: 10.1109/TED.2025.3560269

Seung-Woo Jung;In Ki Kim;Sung-Min Hong

引用次数: 0