IEEE Transactions on Electron Devices最新文献

{"title":"Highly Robust All-Oxide Transistors Toward Vertical Logic and Memory","authors":"Zehao Lin;Zhuocheng Zhang;Chang Niu;Hongyi Dou;Ke Xu;Mir Md Fahimul Islam;Jian-Yu Lin;Changhyuck Sung;Minji Hong;Daewon Ha;Haiyan Wang;Muhammad Ashraful Alam;Peide. D. Ye","doi":"10.1109/TED.2024.3495632","DOIUrl":"https://doi.org/10.1109/TED.2024.3495632","url":null,"abstract":"In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over \u0000<inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>\u0000 C but also gained a boosted on-/off-ratio over \u0000<inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>\u0000 with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability (\u0000<inline-formula> <tex-math>$boldsymbol {Delta } {V}_{text {TH}}text {)}$ </tex-math></inline-formula>\u0000 of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for \u0000<inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula>\u0000 s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length (\u0000<inline-formula> <tex-math>${T}_{text {IO,{g}}}text {)}$ </tex-math></inline-formula>\u0000 of 10 nm, achieving on-/off-ratio over \u0000<inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula>\u0000 and maximum current (\u0000<inline-formula> <tex-math>${I}_{max }text {)}$ </tex-math></inline-formula>\u0000 over \u0000<inline-formula> <tex-math>$160~boldsymbol {mu } $ </tex-math></inline-formula>\u0000 A/\u0000<inline-formula> <tex-math>$boldsymbol {mu } $ </tex-math></inline-formula>\u0000 m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to \u0000<inline-formula> <tex-math>$10^{{12}}$ </tex-math></inline-formula>\u0000 cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7984-7991"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multiphysics Simulation of Chiplet Integration Process-Induced Stress Effects on AC and DC Quantum Transport of FinFET From System Technology Co-Optimization Perspective","authors":"Liang Tian;Yizhang Liu;Wenchao Chen","doi":"10.1109/TED.2024.3488676","DOIUrl":"https://doi.org/10.1109/TED.2024.3488676","url":null,"abstract":"Hybrid bonding plays an important role in advanced 2.5-D/3-D chiplet integration due to its distinctive advantages, such as higher interconnect density, lower power consumption, and better signal integrity. However, the dc/ac performance of the logic device in chiplet can be affected by the strain induced by the annealing and cooling steps of hybrid bonding. In this article, a coupled multiphysics simulation is performed to investigate the impact of the hybrid bonding process on the performance of p-type FinFET by introducing stress from the hybrid bonding process into quantum transport simulation for FinFET based on nonequilibrium Green’s function (NEGF) formalism, in which the impact of hybrid bonding process-induced stress on the band structure of the device is captured by employing six-band \u0000<inline-formula> <tex-math>${k} cdot {p}$ </tex-math></inline-formula>\u0000 Hamiltonian and deformation potential theory. The simulation results indicate that the on-state current and the hole density in the channel can be enhanced due to the variation of the density of states (DOSs) caused by hybrid bonding process-induced stress, the effect of process-induced stress on Y parameters and gate capacitance in the frequency domain is also explored. Devices near the center of copper pillars are more affected than those far away from the copper pillars. Decreasing the radius of copper pillars and annealing temperature or increasing the distance between copper pillars can decrease the hybrid bonding process-induced stress in FinFET, hence decreasing the change in device performance, including \u0000<sc>on</small>\u0000-state current, Y parameters, and gate capacitance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7294-7301"},"PeriodicalIF":2.9,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvement of Memory Window of Silicon Channel Hf₀.₅Zr₀.₅O₂ FeFET by Inserting Al₂O₃/HfO₂/Al₂O₃ Top Interlayer","authors":"Runhao Han;Tao Hu;Jia Yang;Mingkai Bai;Yajing Ding;Xianzhou Shao;Saifei Dai;Xiaoqing Sun;Junshuai Chai;Hao Xu;Kai Han;Xiaolei Wang;Wenwu Wang;Tianchun Ye","doi":"10.1109/TED.2024.3489595","DOIUrl":"https://doi.org/10.1109/TED.2024.3489595","url":null,"abstract":"In this work, we propose a gate structure to enhance the memory window (MW) of Si-channel Hf0.5Zr0.5O2 FeFETs. We achieve an MW of 10.04 V by inserting an Al2O3/HfO2/Al2O3 (AHA) top dielectric interlayer between the ferroelectric Hf0.5Zr0.5O2 layer and the metal gate, where the gate-stack thickness is 14.8 nm. The physical origin is that the Al2O3/HfO2, HfO2/Al2O3, and Al2O3/Hf0.5Zr0.5O2 interfaces can trap charges from the metal gate, contributing to the MW enhancement. This AHA top dielectric multilayer effectively suppresses charge loss compared with a single Al2O3 top dielectric interlayer. Moreover, the de-trapping of charges injected from the metal gate is the primary factor for the degradation of the MW in this structure. Our work provides a guide for improving the MW of FeFET.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7489-7494"},"PeriodicalIF":2.9,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dark Current Performance Enhancement in Type-II Superlattice Photodetectors via pBn Barrier Engineering","authors":"Pooja Kawde;Anuja Singh;Bhaskaran Muralidharan","doi":"10.1109/TED.2024.3488683","DOIUrl":"https://doi.org/10.1109/TED.2024.3488683","url":null,"abstract":"Type-II superlattices (T2SLs) are currently technologically favored absorbers for infrared (IR) photodetectors due to their tunable band gap, lower Auger recombination rates, and higher effective masses in comparison to traditional bulk ternary alloys such as HgCdTe. The pBn barrier configuration is usually preferred to improve the dark current characteristics of the InAs/GaSb T2SL IR photodetectors. To investigate conclusively the impact of a barrier on the dark current, we present a comprehensive study featuring a pBn and a p-i-n device configuration at 77 K. In the pBn configuration, the doping levels in the barrier and absorber layer suppress the band-to-band tunneling (BTBT) and the trap-assisted tunneling (TAT) current dominates. In the p-i-n detector, the TAT current prevails with a small contribution of BTBT current near \u0000<inline-formula> <tex-math>${V}=-1~text {V}$ </tex-math></inline-formula>\u0000, as a function of absorber doping. It is shown that the pBn detector exhibits 104 times less TAT current when compared with the p-i-n detector at \u0000<inline-formula> <tex-math>${V}=-{0.1}~text {V}$ </tex-math></inline-formula>\u0000. As the dark current varies with the number of monolayers of InAs and GaSb in a given period, we then focus on the dark current minimization of three pBn detectors with an absorber layer consisting of a symmetric superlattice (SL), InAs-rich SL, and GaSb-rich SL each with an energy band gap of 0.23 eV. We conclusively ascertain and demonstrate the barrier and absorber configurations along with the bias conditions that minimize the dark currents thereby setting a stage to systematically engineer barriers with the aim of minimizing dark currents via a component-by-component analysis.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7628-7636"},"PeriodicalIF":2.9,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142790225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Electrical Uniformity and Performance via Low-Cost Hybrid Wet Transfer Method for van der Waals Source/Drain Contact Formation in MoS₂ Field-Effect Transistors","authors":"Yu Heng Deng;Rui Su;Weichao Jiang;Hao Sun;Qing He Wang;Lu Liu;Jingping Xu;Peter T. Lai","doi":"10.1109/TED.2024.3487821","DOIUrl":"https://doi.org/10.1109/TED.2024.3487821","url":null,"abstract":"A hybrid wet transfer method for the fabrication of MoS2 field-effect transistor (FET) array is demonstrated by using polymethyl methacrylate (PMMA) support and hydrofluoric (HF) assistance, which significantly reduces the fabrication complexity and cost. The MoS2FET array is fabricated with amorphous HfO2 as a gate dielectric, undoped CVD monolayer MoS2 as a conduction channel, and Ag as source/drain (S/D) electrodes. Transmission electron microscopy, Raman spectroscopy, and photoluminescence spectrum confirm the integrity of the monolayer MoS2 film and the well-fit, damage-free interface between MoS2 and Ag or HfO2, demonstrating the feasibility of this transfer method. The FET exhibits an impressive on-off current ratio of up to \u0000<inline-formula> <tex-math>$3.1 times 10^{{8}}$ </tex-math></inline-formula>\u0000 at a drain voltage (\u0000<inline-formula> <tex-math>${V}_{text {DS}}$ </tex-math></inline-formula>\u0000) of 1 V and a substantial on-current up to \u0000<inline-formula> <tex-math>$271 ; mu $ </tex-math></inline-formula>\u0000A\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m\u0000<inline-formula> <tex-math>$^{-{1}}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>${V}_{text {DS}} = 3$ </tex-math></inline-formula>\u0000 V and gate voltage = 5 V. The electrical measurements of 200 transistors show a low threshold voltage of 0.72 V with a standard deviation of 0.17 V and a high field-effect mobility of 69.9 cm\u0000<inline-formula> <tex-math>$^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ </tex-math></inline-formula>\u0000 with a standard deviation of 9.8 cm\u0000<inline-formula> <tex-math>$^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ </tex-math></inline-formula>\u0000. Furthermore, the devices exhibit a low contact resistance of 1.49 k\u0000<inline-formula> <tex-math>$Omega cdot mu $ </tex-math></inline-formula>\u0000m with a standard deviation of 0.33 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, indicating good electrical uniformity and exceptional performance for the Ag S/D electrodes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7943-7947"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedded Silicon-Germanium-Based Thermoelectric Devices on 300-mm Wafer","authors":"C. Schwinge;R. Hoffmann;K. Biedermann;M. Czernohorsky;J. Kannan;M. Rudolph;F. Mende;M. Wagner-Reetz;G. Gerlach;W. Weinreich","doi":"10.1109/TED.2024.3482259","DOIUrl":"https://doi.org/10.1109/TED.2024.3482259","url":null,"abstract":"Scalability and the absence of moving components are excellent advantages for integrated thermoelectric (TE) devices in microelectronic applications. Both TE coolers (TECs) and TE generators (TEGs) could enhance computer chip efficiency and reliability. We show the fabrication of CMOS-compatible silicon-germanium (SiGe)-based TEC and TEG multistage structures for lateral temperature gradients with microelectronic manufacturing processes on 300-mm wafers. The smallest structures have a size of 1500 \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 500 nm and achieved a cooling temperature difference of around 0.13 K. The TEGs of equal dimensions reached a maximum voltage factor of 545 mV\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000mm\u0000<inline-formula> <tex-math>$^{-{2}} cdot $ </tex-math></inline-formula>\u0000K\u0000<inline-formula> <tex-math>$^{-{1}}$ </tex-math></inline-formula>\u0000 and a specific power generation factor of 2.1 nW\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000mm\u0000<inline-formula> <tex-math>$^{-{2}} cdot $ </tex-math></inline-formula>\u0000K\u0000<inline-formula> <tex-math>$^{-{2}}$ </tex-math></inline-formula>\u0000 near room temperature. Three different n-type SiGe materials were compared and examined regarding their TE properties. To address the challenge of contacting the TE element, we have captured and analyzed transmission electron microscopy (TEM) images for defect identification.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7794-7801"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10750481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias","authors":"P. Zhao;L. Witters;A. Jourdain;M. Stucchi;N. Jourdan;J. W. Maes;H. Bana;C. Zhu;R. Chukka;F. Sebaai;K. Vandersmissen;N. Heylen;D. Montero;S. Wang;K. D’Havé;F. Schleicher;J. De Vos;G. Beyer;A. Miller;E. Beyne","doi":"10.1109/TED.2024.3487080","DOIUrl":"https://doi.org/10.1109/TED.2024.3487080","url":null,"abstract":"Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si0.75Ge0.25 etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7963-7969"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"1200-V Trench-FS IGBT: Process-Based Modeling and Short-Circuit Safe Operating Area (SCSOA) Optimization With the TOPSIS Method","authors":"Yifei Chang;Jiaxuan Wang;Hao Guan;Pan Liu","doi":"10.1109/TED.2024.3489603","DOIUrl":"https://doi.org/10.1109/TED.2024.3489603","url":null,"abstract":"Power electronics are widely used in new energy vehicles, photovoltaics, and other fields. Its robustness has been concerned, and short-circuit robustness is an essential part of it, which is worth in-depth research. In this work, a 1200-V Trench-field-stop (FS) insulated-gate bipolar transistor (IGBT) was focused on for its short-circuit safe operating area (SCSOA) capability analysis. First, a model based on the actual process flow was set up, aligned with the scanning electron microscope (SEM) results, with the discrepancy between its static and dynamic electrical characteristics controlled within 5% and 12%, respectively. Subsequently, two primary failure modes and mechanisms of the device under test (DUT) under short-circuit conditions were identified, analyzed through TCAD modeling, and verified through actual short-circuit tests. Finally, the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS) method for multiple-criteria decision-making (MCDM) was applied to optimize the SCSOA, enhancing the short-circuit robustness of the device by 4% with minimal loss to other electrical performances.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7716-7726"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142790240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Broadband and Transient-Accurate AlGaN/GaN HEMT SPICE Model for X-Band RF Applications","authors":"Raghvendra Dangi;Ahtisham Pampori;Praveen Pal;Mohammad Sajid Nazir;Pragya Kushwaha;Yogesh Singh Chauhan","doi":"10.1109/TED.2024.3487959","DOIUrl":"https://doi.org/10.1109/TED.2024.3487959","url":null,"abstract":"Dispersive effects such as trapping play a vital role in determining the performance of AlGaN/gallium nitride (GaN) high-electron mobility transistors (HEMTs) for RF and power applications—necessitating accurate modeling for robust circuit designs. This work presents a rigorous SPICE model to capture the transient and large-signal impact of traps in AlGaN/GaN HEMTs. The model has been implemented in the industry-standard ASM-HEMT compact-model framework. The model accurately accounts for the variation in threshold voltage and change in 2DEG charge carrier concentration in the source- and drain-side access regions under various drain-lag and gate-lag quiescent conditions. Threshold voltage and 2DEG charge carrier concentration at the source- and drain-side access regions show a linear dependence on drain-lag and gate-lag quiescent conditions, respectively. The results obtained using the developed model are in good agreement with the measured data. This model is valid for transient current simulations at different quiescent conditions and accurately captures the large-signal behavior at the optimal load impedance. Finally, pulsed IV characteristics at different temperatures have been validated against device measurements.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7390-7397"},"PeriodicalIF":2.9,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of Drain-Induced Barrier Lowering in GaN HEMTs Using a Drain Current Injection Technique","authors":"Björn Hult;Johan Bergsten;Ragnar Ferrand-Drake Del Castillo;Vanya Darakchieva;Anna Malmros;Hans Hjelmgren;Mattias Thorsell;Niklas Rorsman","doi":"10.1109/TED.2024.3489592","DOIUrl":"https://doi.org/10.1109/TED.2024.3489592","url":null,"abstract":"Assessing short channel effects (SCEs) is crucial in the high-frequency optimization of downscaled field-effect transistors (FETs) such as GaN high electron mobility transistors (HEMTs). Drain-induced barrier lowering (DIBL) is commonly used for quantifying the ability of the gate to modulate the drain-source current at high drain voltages. DIBL is traditionally extracted from the relative shift of the threshold voltage at different drain-source voltages. In this article, we propose a new method based on a drain current injection technique (DCIT) to assess DIBL. This method facilitates a direct measure of the threshold voltage over a wide range of drain-source voltages in a single measurement. The method is demonstrated and compared to the conventional method using AlGaN/GaN and InAlGaN HEMTs with a Fe-doped buffer and a C-doped AlGaN back-barrier, respectively. Furthermore, the impact of different gate lengths and GaN channel layer thicknesses is presented. The measurements are analyzed and discussed with supporting technology computer-aided design (TCAD) simulations. The proposed method facilitates a more general and detailed measurement of the DIBL for HEMTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7383-7389"},"PeriodicalIF":2.9,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}