Experimental Analysis and Mathematical Modeling of Program Efficiency in Gate-Side Injection Type FeFETs Depending on the Gate Interlayer

Abstract

We experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal – gate interlayer (G.IL) – ferroelectrics – channel interlayer (Ch.IL) – Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges ( ${Q}_{\text {it}}'$ ) from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for nand cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive ${Q}_{\text {it}}$ injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low- $\kappa $ SiO2 G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing ${V}_{\text {th}}$ shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation nand Flash memory technologies.