IEEE Transactions on Electron Devices最新文献

{"title":"Design and Development of Polarization-Enhanced E-Mode GaN p-FET and Complementary Logic (CL) Circuits","authors":"Teng Li;Jingjing Yu;Sihang Liu;Yunhong Lao;Jiawei Cui;Hengyuan Qi;Junjie Yang;Han Yang;Xuelin Yang;Maojun Wang;Yamin Zhang;Shiwei Feng;Bo Shen;Meng Zhang;Jin Wei","doi":"10.1109/TED.2025.3556047","DOIUrl":"https://doi.org/10.1109/TED.2025.3556047","url":null,"abstract":"The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (<inline-formula> <tex-math>${t}_{x}$ </tex-math></inline-formula>) is found to be a critical parameter that influences the device metrics. With a decrease in <inline-formula> <tex-math>${t}_{x}$ </tex-math></inline-formula> (i.e., larger recess depth), a more negative threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>) is achieved; however, the trade-off is an increase in <inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>. The E-mode GaN p-FET with <inline-formula> <tex-math>${t}_{x} =32$ </tex-math></inline-formula> nm exhibits a <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> of −1.1 V, a high current density of 17.7 mA/mm, a high <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$6.9times 10^{{7}}$ </tex-math></inline-formula>, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> of 1.3 V and an <inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$6~mathrm {Omega cdot }$ </tex-math></inline-formula>mm. Finally, a GaN CL inverter was fabricated and demonstrated under <inline-formula> <tex-math>${V}_{text {DD}} =6$ </tex-math></inline-formula> V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2259-2264"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Millisecond Pulsed Light Annealing for Improving Performance of Top-Gate Self-Aligned a-IGZO TFT","authors":"Heetae Kim;Seohak Park;Johak Jeong;Jun-Hwe Cha;Hoseok Lee;Chihun Sung;Jeho Na;Keun Heo;Sung Haeng Cho;Sung-Yool Choi;Byung Jin Cho","doi":"10.1109/TED.2025.3556116","DOIUrl":"https://doi.org/10.1109/TED.2025.3556116","url":null,"abstract":"The application of millisecond intense pulsed light (IPL) annealing to improve the electrical properties of top-gate self-aligned (TG-SA) amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) was investigated. The IPL annealing with a pulse energy of 40 J/cm2 and a pulsewidth of 20 ms resulted in 53.7% increase in <inline-formula> <tex-math>$mu _{text {FE}}$ </tex-math></inline-formula> and a 128.4% improvement in <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>, compared to the unannealed devices. These improvements are attributed to the selective improvement of the specific contact resistivity (<inline-formula> <tex-math>$rho _{text {c}}$ </tex-math></inline-formula>) by the IPL annealing. In addition, positive bias stress (PBS) reliability and temperature-dependent I–V measurements show the improved stability in the IPL-annealed devices and the lower activation energy (<inline-formula> <tex-math>${E}_{text {A}}$ </tex-math></inline-formula>) for charge transport, indicating that the channel region would also have a lower defect density and barrier height for carrier transport.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2399-2405"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast and Accurate Prediction of Electrical Characteristics of Next-Generation Node 3-D NAND Flash Memory Using Transfer Learning","authors":"Hyundong Jang;Soomin Kim;Kyeongrae Cho;Kihoon Nam;Donghyun Kim;Hyeok Yun;Seungjoon Eom;Rock-Hyun Baek","doi":"10.1109/TED.2025.3556104","DOIUrl":"https://doi.org/10.1109/TED.2025.3556104","url":null,"abstract":"Electrical characteristics of scaled 3-D <sc>nand</small> cells for next-generation node development were predicted using transfer learning with limited data. The <sc>nand</small> cell structure parameters were considered as the inputs, and outputs included key electrical characteristics, such as cell <inline-formula> <tex-math>${V}_{t}$ </tex-math></inline-formula>, the difference in <inline-formula> <tex-math>${V}_{t}$ </tex-math></inline-formula> between the initial and programming states (<inline-formula> <tex-math>$Delta {V}_{t}$ </tex-math></inline-formula>), subthreshold swing (SS), and <sc>on</small>-current (<inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>). A multilayer perceptron (MLP) model comprising four hidden layers and focusing on large <sc>nand</small> cells (25 nm gate length) with 2000 data points served as a pre-trained model. The transfer model leveraged pre-trained knowledge to predict the electrical characteristics of smaller cells (19 nm gate length) with 500 data points without weight and bias training. Evaluation of test data exhibited remarkable accuracy with both the mean and standard deviation below 3%, proving the model’s effectiveness despite limited data. In addition, a comprehensive evaluation was conducted by comparing the performance of the model with variations in the dataset size and the presence of transfer learning, highlighting the effectiveness and advantages of transfer learning. Transfer learning could provide detailed structure information of the next node for engineers and expedite device development, resulting in significant time and cost savings.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2354-2359"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of a Low-Loss Transmission Structure for W-Band TWT","authors":"Zhiyu Chen;Jingrui Duan;Yuan Zheng;Hao Li;Yubin Gong","doi":"10.1109/TED.2025.3556048","DOIUrl":"https://doi.org/10.1109/TED.2025.3556048","url":null,"abstract":"A low-loss transmission structure for W-band traveling wave tube (TWT) is proposed in this article. It converts the rectangular waveguide fundamental TE10 mode into the corrugate waveguide HE11 mode with a quasi-Gaussian energy distribution, thereby reducing ohmic loss on the waveguide walls. The sections maintaining and generating the HE11 mode are theoretically analyzed. The simulation results show that the <inline-formula> <tex-math>${S} _{{11}}$ </tex-math></inline-formula> of the converter is less than −20 dB in the frequency range of 80–100 GHz, and the mode conversion purity reaches 99.66%. Compared with a conventional rectangular waveguide with a 4.5 dB/m transmission loss, the insertion loss of novel structure has successfully been reduced by 3.1 dB/m to as low as 1.4 dB/m Furthermore, the same length W-band low-loss transmission structure and rectangular waveguide have been fabricated and cold-tested, the results reveal a reduction in insertion loss of 2.5 dB per meter, verifying the simulation predictions. A burned spot experiment was conducted to verify the energy distribution of the HE11 mode. The experimental results confirm the feasibility of the proposed low-loss transmission structure for low-loss transmission in W-band TWT input-output structures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2611-2617"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extremely High ESD Failure Voltage of RESURF LDMOS Devices for ESD Resilient Driver Applications","authors":"Aakanksha Mishra;M. Monishmurali;B. Sampath Kumar;Shaik Ahamed Suzaad;Shubham Kumar;Kiran Pote Sanjay;Amit Kumar Singh;Avinash Singh;Ankur Gupta;Mayank Shrivastava","doi":"10.1109/TED.2025.3556114","DOIUrl":"https://doi.org/10.1109/TED.2025.3556114","url":null,"abstract":"This work reports an extremely high ESD failure voltage in the transmission line pulse (TLP) characteristics of the laterally diffused metal-oxide-semiconductor (LDMOS) devices, while investigating a correlation between the critical voltage and filament formation. A high failure voltage enables an additional immunity to ESD damage by providing extra protection against the overvoltage stress in high-voltage (HV) I/O applications. The ESD behavior of LDMOS devices in the presence of reduced surface field (RESURF)-implant in the drift region is investigated in detail. Furthermore, an approach to drift region design and electric field engineering that affects this high failure voltage in RESURF LDMOS devices is discussed, using measurement and 3-D TCAD simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2187-2194"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Large Scale Neural Network Acceleration With 3-D FeNOR-Based Computing-in-Memory Design","authors":"Yang Feng;Dong Zhang;Chen Sun;Zijie Zheng;Yue Chen;Qiwen Kong;Gan Liu;Xiaolin Wang;Yuye Kang;Kaizhen Han;Zuopu Zhou;Leming Jiao;Jixuan Wu;Jiezhi Chen;Xiao Gong","doi":"10.1109/TED.2025.3554164","DOIUrl":"https://doi.org/10.1109/TED.2025.3554164","url":null,"abstract":"In this work, we introduce and experimentally demonstrate a 3-D stacked ferroelectric <sc>nor</small> (FeNOR) memory, featuring a back-end-of-line (BEOL) zinc oxide (ZnO) channel, and a metal-ferroelectric–metal-insulator5 semiconductor (MFMIS) unit cell. The main contributions of this work are as follows: 1) enhanced memory window (MW) and high <sc>on</small>/<sc>off</small> ratio: The MFMIS architecture in 3-D FeNOR enables a tunable and large MW (~4 V), as well as an <sc>on</small>/<sc>off</small> ratio (<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula>) of six orders of magnitude; 2) low operation voltage and high endurance: The integration of ferroelectric materials allows for low operation voltages (~4 V) and excellent endurance (<inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula> cycles); 3) efficient neural network implementation: Leveraging the 3-D FeNOR structure, we further develop VGG-16 and ResNet-50 convolutional neural networks that achieve high prediction accuracy, decent area efficiency, and low power consumption. The emergence of 3-D FeNOR technology positions ferroelectric devices as a highly promising candidate for computing-in-memory (CIM) applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2319-2326"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Data-Driven Device Design Framework for Semiconductor Manufacturing With Dual-Hierarchy DNN Prediction Scheme and PSO","authors":"Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yue Cheng;Xuanzhi Jin;Yunlong Li;Dawei Gao;Yitao Ma;Kai Xu","doi":"10.1109/TED.2025.3556049","DOIUrl":"https://doi.org/10.1109/TED.2025.3556049","url":null,"abstract":"Optimizing devices in integrated circuits (ICs) remains challenging due to the complexity of modern manufacturing. Traditional methods like technology computer-aided design (TCAD) require extensive human intervention. Meanwhile, machine learning (ML)-based approaches provide automation but frequently struggle with real-world manufacturing variations across the full fabrication workflow. This work proposes a loop optimization framework composed of three key components: an inverse model for device parameter prediction, a forward model as a TCAD surrogate, and a weighted particle swarm optimization (PSO) algorithm. Trained on real manufacturing data that includes manufacturing variations, the surrogate model better reflects actual fabrication conditions. Compared to TCAD simulations, the trained forward model achieves a computational speedup of nearly 40000 times. Furthermore, by leveraging the inverse model to constrain optimization and a fully adjustable weighting mechanism, the framework enables precise control over optimization intensity and solution reliability, ensuring adjustable tradeoffs. It also supports customizable weight adjustments for different electrical characteristic metrics, allowing users to prioritize specific characteristics as required. Overall, this work provides an efficient and flexible tool for balancing tradeoffs and optimizing semiconductor device design.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2512-2521"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Optimization of Silicon Avalanche Photodiodes With Desired Breakdown Voltage Using Bayesian Optimization","authors":"Sara Ghazvini;Gerd Schuppener;Wenjuan Fan;Srinath Ramaswamy;William G. Vandenberghe","doi":"10.1109/TED.2025.3552537","DOIUrl":"https://doi.org/10.1109/TED.2025.3552537","url":null,"abstract":"In this study, we introduce an innovative optimization methodology for the design and optimization of avalanche photodiodes (APDs) using analytical calculations, Bayesian optimization (BO), and technology computer-aided design (TCAD) simulations. The parameters under optimization include the thickness and doping concentration of the <italic>p</i> and <italic>i</i> regions. Our approach aims to tailor APDs to specific breakdown voltage (BV) requirements while achieving superior performance characteristics, such as gain, responsivity, and bandwidth. Through BO, we efficiently explore the design space to identify optimal configurations. The optimized APDs exhibit enhanced performance compared to previous studies, with superior responsivity, gain, and cutoff frequency while having the desired BV. The optimization process successfully designs APDs with BVs ranging from 30 to 50 V, achieving gains of 100, responsivities of 0.29 A/W, and impressive cutoff frequencies exceeding 0.9 GHz for a photon wavelength of 650 nm and an intensity of 0.1 W/cm2 with the BV error less than 0.5 V relative to the target value. This approach demonstrates the effectiveness of BO in optimizing APDs for specific applications, addressing the challenges of balancing multiple performance metrics and meeting targeted BV requirements.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2424-2430"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A High-Resolution and Large-Bandwidth Resonant Accelerometer With Thermal Boost Sensitivity","authors":"Chengxin Li;Chen Wang;Hemin Zhang;Chun Zhao;Aojie Quan;Sina Sadeghpour;Mustafa Mert Torunbalci;Michael Kraft","doi":"10.1109/TED.2025.3554161","DOIUrl":"https://doi.org/10.1109/TED.2025.3554161","url":null,"abstract":"Capacitive actuation and piezoresistive detection (CAPD) mechanisms have been explored to enhance the bandwidth of resonant accelerometers, leveraging their high transduction gain to amplify weak signals. Despite these advantages, the stiffness of beams for the piezoresistive gauges poses a challenge to achieving high sensitivity and resolution. To address this limitation, this article presents a high-resolution resonant accelerometer with enhanced scale factor using a thermal boost approach to increase sensitivity. The accelerometer features a CAPD resonator consisting of a dual-clamped beam with two symmetrically arranged piezoresistive gauges. By applying a dc thermal voltage across these piezoresistive gauges, a thermal perturbation stiffness arises due to the resistance difference between the two gauges. This stiffness alters the coupling between the in-phase and out-of-phase modes of the resonator, enabling enhancements to the scale factor of the resonant accelerometer. Experimental results show that this approach significantly improves the scale factor from 975 to 2483 Hz/g and decreases the noise spectral density from 2.4 to <inline-formula> <tex-math>$0.9~mu $ </tex-math></inline-formula>g/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz, while maintaining a high bandwidth of 1000 Hz. This advancement highlights the effectiveness of thermal perturbation in boosting the scale factor and achieving a higher bandwidth-to-noise floor ratio of 1111 for resonant accelerometers.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2552-2560"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of 1-MeV Equivalent Neutron Irradiation on the Electrical Characteristic of NiOx/β-Ga2O3 p-n Diode","authors":"Yahui Feng;Hongxia Guo;Wuying Ma;Xiaoping Ouyang;Jinxin Zhang;Fengqi Zhang;Dinghe Liu;Xiaohua Ma;Yue Hao","doi":"10.1109/TED.2025.3554746","DOIUrl":"https://doi.org/10.1109/TED.2025.3554746","url":null,"abstract":"In this article, the impact of 1-MeV equivalent neutron irradiation on the electronic properties of NiOx/beta-phase gallium oxide (<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2<inline-formula> <tex-math>${mathrm {O}}_{{3}}text {)}$ </tex-math></inline-formula> p-n diode has been investigated. After neutron irradiation with a fluence of <inline-formula> <tex-math>$1times 10^{{14}}$ </tex-math></inline-formula> n/cm2, the forward current density (<inline-formula> <tex-math>${J}_{F}text {)}$ </tex-math></inline-formula> decreased by 23%, the leakage current density (<inline-formula> <tex-math>${J}text {)}$ </tex-math></inline-formula> was reduced by 45.6%, and the breakdown voltage (<inline-formula> <tex-math>${V}_{text {br}}text {)}$ </tex-math></inline-formula> increased by approximately 216 V, as measured by current − voltage (I–<inline-formula> <tex-math>${V}text {)}$ </tex-math></inline-formula> analysis. The capacitance− voltage (C–<inline-formula> <tex-math>${V}text {)}$ </tex-math></inline-formula> measurement shows that the carrier concentration in the lightly doped n-type <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 drift layer decreased from <inline-formula> <tex-math>$1.96times 10^{{16}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$1.74times 10^{{16}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{3}}$ </tex-math></inline-formula> after neutron irradiation. The effect of neutron irradiation on the trap states was studied using frequency-dependent conductivity techniques. It is revealed that the density of trap states at NiOx/<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 increases significantly from 1.12 to <inline-formula> <tex-math>$1.49times 10^{{12}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}cdot $ </tex-math></inline-formula>eV<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula> to 3.76-<inline-formula> <tex-math>$5.80times 10^{{12}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}cdot $ </tex-math></inline-formula>eV<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>, accompanied by a slight decrease in trap activation energy from 0.091 to 0.187 eV to <inline-formula> <tex-math>$0.086-0.185$ </tex-math></inline-formula> eV after neutron irradiation. Additionally, deep-level transient spectroscopy (DLTS) measurements indicate that the trap at an energy level of <inline-formula> <tex-math>${E}_{C}$ </tex-math></inline-formula>–<inline-formula> <tex-math>${E}_{T} =0.75$ </tex-math></inline-formula> eV, induced by neutron irradiation, is likely the primary cause of the degradation in NiOx/<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 p-n diode properties. These findings can offer significant theoretical insights for the design of future anti-radiation hardening.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2240-2245"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}