IEEE Transactions on Electron Devices最新文献_第3页

Compact Model of Filament-Free Bulk RRAM 无长丝大容量随机存储器的紧凑模型

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-27 DOI: 10.1109/TED.2026.3714752

Yucheng Zhou;Yue Zhou;Ashwani Kumar;Fengyi Sun;Yu-Hwa Lo;Ertugrul Cubukcu;Duygu Kuzum

{"title":"Compact Model of Filament-Free Bulk RRAM","authors":"Yucheng Zhou;Yue Zhou;Ashwani Kumar;Fengyi Sun;Yu-Hwa Lo;Ertugrul Cubukcu;Duygu Kuzum","doi":"10.1109/TED.2026.3714752","DOIUrl":"https://doi.org/10.1109/TED.2026.3714752","url":null,"abstract":"Filament-free bulk switching resistive random-access memory (b-RRAM) holds great promise for future in-memory computing applications. b-RRAM addresses shortcomings of filamentary RRAM devices including high voltage forming step, variations, low <sc>on</small>-state resistance and high energy consumption. In order to explore new design concepts, like CMOS-RRAM integration for compute in memory and reconfigurable neuromorphic systems, it is essential to develop robust compact models for b-RRAM, compatible with circuit simulators to evaluate performance at the system level. In this article, we present a physics-based compact model for b-RRAM based on oxygen vacancy (V<inline-formula> <tex-math>${}_{text {O}}$ </tex-math></inline-formula>) migration. The model describes the electric-field-driven migration of VOs and the resulting movement of the interface between VO-rich and VO-deficient oxide regions. The model is validated by experimental data from trilayer (Al2O3/TiO2/TiO<inline-formula> <tex-math>${}_{text {x}}$ </tex-math></inline-formula>) b-RRAM devices with Al top electrode. It successfully reproduces the DC switching behavior, area scaling of the device resistance, temperature-dependent <inline-formula> <tex-math>$I$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V$ </tex-math></inline-formula> characteristics, and pulse switching dynamics. By incorporating an interface position-dependent activation energy <inline-formula> <tex-math>${E}_{text {a}}$ </tex-math></inline-formula>(x), the model captures the switching saturation behavior observed across various pulse conditions. The excellent agreement between the model and experimental results demonstrates that the proposed model enables accurate device modeling and hence, suitable for large-scale circuit simulations with b-RRAM array. Array-level simulations further confirm reliable convergence and efficient runtime from a single cell up to 100 000-cell crossbar arrays, demonstrating the model’s suitability for large-scale circuit and system-level simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5395-5402"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 950 °C-Thermal-Budget-Compatible Al2O3-Embedded Hf0.5Zr0.5O2 Poly-Si Channel- Last FeFET for 3-D NAND Applications 一种950°c -热预算兼容的al2o3 -嵌入式Hf0.5Zr0.5O2多晶硅通道-用于3-D NAND应用的最后场效应晶体管

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-09-07 DOI: 10.1109/TED.2026.3717557

Wenbo Fan;Xiaoyu Ke;Yajing Ding;Xianzhou Shao;Saifei Dai;Tao Hu;Runhao Han;Min Liao;Xinpei Jia;Fengbin Tian;Tingting Li;Bo Tang;Junshuai Chai;Hao Xu;Qing Luo;Xiaolei Wang;Wenwu Wang;Tianchun Ye

引用次数: 0

Light Optical Power Enhancement of High-Power Deep-Ultraviolet LEDs Through Optimized Fluoropolymer Packaging 通过优化含氟聚合物封装提高高功率深紫外led的光功率

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-22 DOI: 10.1109/TED.2026.3710689

Zhengang Liang;Yufan Wei;Zhiwei Gao;Chengfei Li;Yang Peng;Renli Liang;Jiangnan Dai

{"title":"Light Optical Power Enhancement of High-Power Deep-Ultraviolet LEDs Through Optimized Fluoropolymer Packaging","authors":"Zhengang Liang;Yufan Wei;Zhiwei Gao;Chengfei Li;Yang Peng;Renli Liang;Jiangnan Dai","doi":"10.1109/TED.2026.3710689","DOIUrl":"https://doi.org/10.1109/TED.2026.3710689","url":null,"abstract":"Deep-ultraviolet light-emitting diodes (DUV LEDs) have significant potential for applications in disinfection and water treatment. However, their widespread commercialization is limited by challenges in light extraction efficiency (LEE) and wall-plug efficiency (WPE). This study focuses on optimizing fluoropolymer packaging to enhance the optoelectronic performance of high-power DUV LEDs. By implementing an experimentally optimized, dam-free fluoropolymer sidewall-encapsulated structure in combination with a simulation-optimized lens, the internal reflection and absorption losses of DUV LED chips are effectively reduced, which significantly boosts light output power (LOP). The optimized fluoropolymer packaging enables the DUV LED with a light output power of 69.35 mW at 200 mA, representing a 68.15% improvement over the reference DUV LED, and the related WPE is increased by 60.60%. Furthermore, the emission angle is reduced drastically from 130° to 22°, resulting in a tenfold increase in on-axis (<inline-formula> <tex-math>$sim 0^{circ }text {)}$ </tex-math></inline-formula> radiant intensity. This work demonstrates that substantial improvements in DUV LED light output and far-field directionality can be realized through packaging optimization, offering a practical approach for the fabrication of high-irradiance DUV LED module.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5598-5603"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multilevel Analog Switching in HfO2/TiOx Flexible Memristor for Precision Neuromorphic Computing 用于精密神经形态计算的HfO2/TiOx柔性忆阻器的多电平模拟开关

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-31 DOI: 10.1109/TED.2026.3716988

Parthasarathi Pal;Shilpa Singh;Sanjay Kumar;Themis Prodromakis;Yeong-Her Wang

{"title":"Multilevel Analog Switching in HfO2/TiOx Flexible Memristor for Precision Neuromorphic Computing","authors":"Parthasarathi Pal;Shilpa Singh;Sanjay Kumar;Themis Prodromakis;Yeong-Her Wang","doi":"10.1109/TED.2026.3716988","DOIUrl":"https://doi.org/10.1109/TED.2026.3716988","url":null,"abstract":"Ongoing progress in scientific research continues to extend technological frontiers, with flexible and wearable electronic systems becoming increasingly central to the next-generation device development. A major bottleneck lies in managing the high thermal budget during the complementary-metal–oxide–semiconductor (CMOS)-compatible fabrication and device performance. Here, we report a CMOS process-compatible stacked flexible memristor-based HfO2, realized on flexible polyimide (PI) substrates and specifically designed to tolerate elevated thermal processing for neuromorphic hardware integration. The fabricated device achieves a high ION/IOFF ratio above <inline-formula> <tex-math>${1}.{6}times {10} ^{{3}}$ </tex-math></inline-formula> under a 100-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A compliance current and displays excellent uniformity across device arrays. Mechanical durability tests confirmed stable functionality beyond <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula> cycles at a curvature radius of 5 mm. In addition, endurance exceeding <inline-formula> <tex-math>$10^{{6}}$ </tex-math></inline-formula> WRITE operations demonstrates strong potential for online learning in neural architecture, while the data retention surpassing <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula> s at <inline-formula> <tex-math>$120~^{circ }$ </tex-math></inline-formula>C ensures reliable long-term data storage and inference. The effectiveness of the devices is further verified through multilayer perceptron (MLP) neural network (NN) simulations employing experimentally derived parameters, yielding a nonlinearity (NL) factor of 0.27 and an enhanced classification accuracy of 97.17% from baseline for input patterns.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5554-5562"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Monolithic 3-D Stackable DRAM With Oxide-Channel- Access Transistors: Density Scaling Through Dual-Deck Stacking and Multilevel Cell 带有氧化通道存取晶体管的单片3d可堆叠DRAM：通过双层堆叠和多层单元实现密度缩放

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-08-12 DOI: 10.1109/TED.2026.3719267

Po-Kai Hsu;Sungwon Cho;Janak Sharda;Kiseok Lee;Hyeonwoo Park;Suman Datta;Shimeng Yu

{"title":"Monolithic 3-D Stackable DRAM With Oxide-Channel- Access Transistors: Density Scaling Through Dual-Deck Stacking and Multilevel Cell","authors":"Po-Kai Hsu;Sungwon Cho;Janak Sharda;Kiseok Lee;Hyeonwoo Park;Suman Datta;Shimeng Yu","doi":"10.1109/TED.2026.3719267","DOIUrl":"https://doi.org/10.1109/TED.2026.3719267","url":null,"abstract":"A monolithic 3-D dynamic random access memory (DRAM) with an oxide channel access transistor has emerged as a promising path to extend memory density beyond the limits of conventional 2-D and early 3-D DRAM technologies. However, scaling is fundamentally constrained by high aspect ratio contacts (HARCs) and sense margin degradation with elevated parasitics as stack height increases. This work explores two directions to overcome these challenges. First, we propose a dual-deck stacking process, in which two monolithic oxide semiconductor transistor-accessed 3-D DRAM arrays are sequentially fabricated and vertically integrated. This approach effectively doubles the number of stacked layers. Furthermore, dimension finetuning on wordline (WL) thickness and bitline (BL) spacing mitigates the sense margin loss. Second, we introduce a multilevel cell (MLC) 3-D DRAM design that employs a CMOS-under-array (CUA) configuration to boost the memory density, which is challenging to introduce in conventional 2-D DRAM due to the tight column pitch. A successive approximation sensing scheme and a Monte Carlo analysis demonstrate reliable two-bit-per-cell operation with clear voltage separations. At the bank level, the combined dual-deck and MLC scheme achieves up to <inline-formula> <tex-math>$3.19times $ </tex-math></inline-formula> density improvement over single-deck, single-level 3-D DRAM, despite moderate latency and energy tradeoffs. These results highlight the scalable pathway of 3-D DRAM for ultrahigh-density memory in large AI models and future computing systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5563-5569"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation on the Cumulative Degradation in p-GaN Gate HEMTs Under Synergistic Electrical Stress and Heavy Ion Irradiation 协同电应力和重离子辐照下p-GaN栅极hemt的累积降解研究

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-24 DOI: 10.1109/TED.2026.3714370

Danmei Lin;Xuefeng Zheng;Shaozhong Yue;Longbing Yi;Xiaohu Wang;Hao Zhang;Kai Liu;Mao Jia;Yingzhe Wang;Ling Lv;Yanrong Cao;Weidong Zhang;Peipei Hu;Jie Liu;Xiaohua Ma;Yue Hao

{"title":"Investigation on the Cumulative Degradation in p-GaN Gate HEMTs Under Synergistic Electrical Stress and Heavy Ion Irradiation","authors":"Danmei Lin;Xuefeng Zheng;Shaozhong Yue;Longbing Yi;Xiaohu Wang;Hao Zhang;Kai Liu;Mao Jia;Yingzhe Wang;Ling Lv;Yanrong Cao;Weidong Zhang;Peipei Hu;Jie Liu;Xiaohua Ma;Yue Hao","doi":"10.1109/TED.2026.3714370","DOIUrl":"https://doi.org/10.1109/TED.2026.3714370","url":null,"abstract":"In this work, the synergistic effects of electrical stress and heavy-ion irradiation on the cumulative degradation of p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) are systematically investigated. The devices were irradiated with Ta ions (LET = 76.3 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg) under the drain bias slightly lower than the single-event burnout (SEB) threshold voltage (<inline-formula> <tex-math>${V}_{text {SEB}}text {)}$ </tex-math></inline-formula>. The saturated drain current (<inline-formula> <tex-math>${I}_{text {Dsat}}text {)}$ </tex-math></inline-formula> exhibits a pronounced cumulative degradation with increasing heavy-ion fluence under <sc>off</small>-state electrical stress. Electrical characterization results show that neither electrical stress nor irradiation alone induces significant degradation, whereas their synergistic effect leads to severe performance degradation. Furthermore, analyses based on low-frequency noise (LFN) and capacitance deep-level transient spectroscopy (<inline-formula> <tex-math>$C$ </tex-math></inline-formula>-DLTS) reveal a substantial increase in trap density in the p-GaN layer after irradiation. The increased traps within the p-GaN layer degrade carrier transport in the channel, mainly through enhanced Coulomb scattering and mobility reduction, accompanied by a partial reduction in the effective 2DEG density.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5342-5346"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel High-Performance PLDC EIO: Design, Simulation, and Cold Test 一种新型高性能PLDC EIO：设计、仿真和冷态测试

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-21 DOI: 10.1109/TED.2026.3712719

S. Muhammad Shahab;Jin Xu;Ying H. Liu;T. Zhang;L. Gu;Xinjian Niu

{"title":"A Novel High-Performance PLDC EIO: Design, Simulation, and Cold Test","authors":"S. Muhammad Shahab;Jin Xu;Ying H. Liu;T. Zhang;L. Gu;Xinjian Niu","doi":"10.1109/TED.2026.3712719","DOIUrl":"https://doi.org/10.1109/TED.2026.3712719","url":null,"abstract":"This article presents a high-efficiency, phase-locked dual-cavity (PLDC) extended interaction oscillator (EIO) operating in the W band. Both cavities are designed in the higher order TM31-<inline-formula> <tex-math>$2pi $ </tex-math></inline-formula> mode, enabling multibeam injection and effective suppression of competing modes. The bunching cavity (BC) premodulates three cylindrical electron beams, while the output cavity (OC) generates power under phase-locked conditions. Particle-in-cell (PIC) simulations predict an average output power of 5.31 kW at 93.5 GHz with an electronic efficiency of 19.95%, representing a twofold improvement over a conventional single-stage EIO. The OC was fabricated and cold-tested, and the measured S11 characteristics agree well with simulations. Operating in the nonrelativistic regime with an 11.1-kV supply and compact form factor, the PLDC EIO bridges the gap between low-power semiconductor devices and large, high-voltage relativistic systems. This combination of high power, high efficiency, and compactness makes it well-suited for mobile radar, UAV payloads, and field-deployable millimeter-wave (MMW) systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5751-5758"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mechanistic Optimization of Spacer-Type Split-Gate Flash Balancing Yield and Performance 间隔型分栅闪光平衡成品率及性能的机理优化

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-29 DOI: 10.1109/TED.2026.3712335

Wanyi Ling;Dianyu Qi;Yongyu Wu;Guangji Li;Miao Zhou;Qingshuang Xu;Xuan Li;Dawei Gao;Kun Ren

{"title":"Mechanistic Optimization of Spacer-Type Split-Gate Flash Balancing Yield and Performance","authors":"Wanyi Ling;Dianyu Qi;Yongyu Wu;Guangji Li;Miao Zhou;Qingshuang Xu;Xuan Li;Dawei Gao;Kun Ren","doi":"10.1109/TED.2026.3712335","DOIUrl":"https://doi.org/10.1109/TED.2026.3712335","url":null,"abstract":"Driven by the stringent reliability requirements of automotive and Internet-of-Things (IoT) applications, this work proposes a spacer-defined split-gate Flash architecture for 55-nm embedded platforms, where a self-aligned spacer process defines the floating-gate (FG) to improve manufacturability while enabling strong gate coupling. Optimization of this structure reveals a critical trilemma among manufacturability, memory window (MW), and subthreshold swing (SS), further complicated by strong nonlinear coupling among select-gate (SG) space, TEOS height, and FG thickness. To resolve these interdependencies, a four-stage synergistic optimization framework is established by integrating TCAD-driven mechanistic decoupling with strict manufacturing constraints. These constraints include a <inline-formula> <tex-math>$ge 76$ </tex-math></inline-formula>-nm common-source-to-active-area spacing for residue-free etching. Mechanistic analysis identifies a 90-nm SG TEOS as the onset of a field-enhancement regime. This regime maximizes the tunneling field without inducing electrostatic instability. An optimized 325-nm SG space stabilizes channel barrier modulation and avoids severe erase-state degradation while preserving high MW and strong <inline-formula> <tex-math>${I} _{mathbf {text {ds}text {at}}}$ </tex-math></inline-formula>. The identified “Golden Recipe” delivers a 15% increase in <inline-formula> <tex-math>${I} _{mathbf {text {ds}text {at}}}$ </tex-math></inline-formula>, a 7.44-V MW, and a 68% improvement in SS. Silicon validation confirms a 7.21-V MW and 100% functional array yield, providing a rigorous physical basis for defining the process window of advanced spacer-type eFlash in high-volume manufacturing.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5520-5527"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Floating-Gate IGZO Thin-Film Transistor Employing Split-Gate to Enable Tunable Subthreshold Swing for AMOLED Pixel Circuits 采用分栅实现AMOLED像素电路可调亚阈值摆幅的浮栅IGZO薄膜晶体管

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-08-17 DOI: 10.1109/TED.2026.3720488

Sunyeol Bae;Hyung-Jun Noh;Yumin Yun;Chae-Hwan Park;Junhyeong Park;Soo-Yeon Lee

{"title":"Floating-Gate IGZO Thin-Film Transistor Employing Split-Gate to Enable Tunable Subthreshold Swing for AMOLED Pixel Circuits","authors":"Sunyeol Bae;Hyung-Jun Noh;Yumin Yun;Chae-Hwan Park;Junhyeong Park;Soo-Yeon Lee","doi":"10.1109/TED.2026.3720488","DOIUrl":"https://doi.org/10.1109/TED.2026.3720488","url":null,"abstract":"Precise subthreshold current control is required for low-gray expression in active-matrix organic light-emitting diode (AMOLED) displays. However, steep subthreshold swings (SSs) are sensitive to voltage fluctuations, limiting the resolution of low-gray expression. We propose a floating-gate indium–gallium–zinc–oxide (IGZO) thin-film transistor (TFT) incorporating a split-gate, enabling geometrically tunable SS through layout engineering. The overlap length (L<inline-formula> <tex-math>${}_{text {ov}}text {)}$ </tex-math></inline-formula> between the driving gate (DG) and floating gate (FG) controls the gate coupling ratio (GCR), achieving a wide SS tunability ranging from 94 mV/dec to 1.08 V/dec, governed by a capacitive coupling model and TCAD simulations. Furthermore, the auxiliary bias gate (BG) enables independent threshold voltage (<inline-formula> <tex-math>${V} _{text {th}}text {)}$ </tex-math></inline-formula> tuning, offering additional operational flexibility. Circuit simulations of a 2T1C OLED pixel confirm that a high SS significantly expands the data voltage window from 1.5 to 8 V, enhancing robustness for voltage deviation and gray-scale precision.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5715-5721"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Current Nonuniform Conduction in Multifinger Bidirectional SCR: The Primary Limiting Factor of ESD Failure Current 多指双向可控硅电流不均匀传导：ESD失效电流的主要限制因素

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-28 DOI: 10.1109/TED.2026.3712707

Yitao Wang;Yang Wang;Hongjiao Yang;Tao Xiao;Yujie Chen

{"title":"Current Nonuniform Conduction in Multifinger Bidirectional SCR: The Primary Limiting Factor of ESD Failure Current","authors":"Yitao Wang;Yang Wang;Hongjiao Yang;Tao Xiao;Yujie Chen","doi":"10.1109/TED.2026.3712707","DOIUrl":"https://doi.org/10.1109/TED.2026.3712707","url":null,"abstract":"This article adds an additional diode path to the traditional silicon-controlled rectifier (SCR) structure to reduce the reverse conduction resistance, and utilizes the SCR structure to form a bidirectional SCR (Bi-SCR) through back-to-back connection, which was developed in a CMOS-DMOS (BCD) technology. Through DC measurements, transmission line pulse (TLP) testing, and system-level IEC testing, it has a breakdown voltage (BV) of ±46 V, a failure current of ±15 A, and a contact discharge level of ±14 kV, all of which can meet the bidirectional electrostatic discharge protection requirements of automotive electronic communication ports with a working voltage of ±24 V. After TLP testing, it was found that the failure current of multifinger Bi-SCR devices decreased significantly compared to multifinger SCR devices used to compose Bi-SCR. 2-D technology computer-aided design (TCAD) was used to study this phenomenon. Research has shown that the decrease in failure current can be directly correlated with changes in device <sc>on</small>-resistance and nonuniform turn-on behavior, and improvement methods at the layout level have been proposed, which restores the failure current of the device to the level of multifinger SCR devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5665-5671"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0