IEEE Transactions on Electron Devices最新文献

{"title":"Multiscale Thermal Simulation for GAAFET With First-Principles-Based Boltzmann Transport Equation","authors":"Yufei Sheng;Yonglin Xia;Jiaxuan Xu;Shuying Wang;Pengpeng Ren;Zhigang Ji;Hua Bao","doi":"10.1109/TED.2025.3592887","DOIUrl":"https://doi.org/10.1109/TED.2025.3592887","url":null,"abstract":"For next-generation advanced logic devices, gate-all-around field-effect transistors (GAAFETs) with characteristic size reaching the 10 nm scale, necessitate thorough consideration of nanoscale thermal transport to assess the impact of self-heating on device performance and reliability. However, previous studies predominantly relied on simplified or fitting models to directly adjust the effective thermal conductivities of various device components within the heat diffusion equation (HDE) or thermal resistance networks. These methods are inadequate for fully capturing nanoscale thermal transport. Here, we perform multiscale thermal simulations of GAAFETs by integrating first-principles-based nongray Boltzmann transport equation (BTE) with the HDE. By comparing the temperature distributions calculated using the gray BTE and HDE, we demonstrate the necessity of employing the nongray phonon BTE for accurate simulation of the active region. We further discover that the size-dependent thermal conductivity of metal regions should be incorporated using the electron–phonon BTE. Moreover, based on comprehensive thermal simulations of a stacked nanosheet GAAFET, we identify that the amorphous passive layer, interfacial thermal resistance between different layers, along with the thermal resistance of the STI/BDI layers and interconnections, are key factors limiting heat dissipation. Our approach fully incorporates nanoscale thermal transport while eliminating reliance on empirical parameters and facilitates multiscale simulations from materials to structures to devices, with potential applicability to circuit-level simulations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4700-4707"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantum Mechanical Analysis of Dual-Gate InGaZnO TFTs Employing a Gated-Multiprobe","authors":"Soyoung Choi;Jaewook Jeong","doi":"10.1109/TED.2025.3591390","DOIUrl":"https://doi.org/10.1109/TED.2025.3591390","url":null,"abstract":"The channel potential distribution of the dual-gate a-IGZO thin-film transistors (TFTs) was analyzed in the active layer using a gated-multiprobe method (GMP method) combining theory of quantum mechanics for the analysis of TFTs having very thin active layer. From the GMP method, the channel potential distribution follows the conventional gradual channel approximation rule from the source to the drain electrodes in case of linear region operation. In the saturation region, pinch-off with the formation of a space-charge-limited region was observed. To compare the result with the theory of quantum mechanics, ATLAS from Silvaco Inc. (ATLAS) device simulation was performed using both classical and quantum mechanical approach. The resulting parasitic resistance values of the dual-gate biasing (DGB) mode differed from the classical approach, owing to the same current spreading path of the top- and bottom-gate channel electrons, when the quantum mechanical density gradient method was applied. The accuracy of the quantum theory was confirmed using the prolonged stress results, which indicated defect creation near the middle of the channel region was the dominant mechanism for the bias stress instability, considering quantum mechanical channel electron distribution.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4983-4990"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Power and High-Speed Ag2S-Based Threshold Switching Device Enabled by Local Phase Transition-Assisted Filamentary Switching","authors":"Seongjae Heo;Sunhyeong Lee;Hyunsang Hwang","doi":"10.1109/TED.2025.3592912","DOIUrl":"https://doi.org/10.1109/TED.2025.3592912","url":null,"abstract":"As the demand for low-power electronic devices in the Internet of Things (IoT) and embedded systems continues to grow, there is an increasing need for new devices that can operate at low voltages with minimal leakage current while maintaining fast switching speeds. To address this challenge, we developed a two-terminal threshold switching (TS) device based on Ag2S, demonstrating both low leakage current and fast switching speed at low voltages. The Ag2S-based TS devices were integrated in series with MOSFETs to form a 1T-1S array, designed for steep-slope FET applications. The Ag2S-based TS device exhibited a low leakage current of 2 pA, and when integrated with the MOSFET, the combined FET demonstrated a subthreshold swing (SS) of 3 mV/dec. Remarkably, the device exhibited a fast switching speed of 1 ns at 2.0 V. In addition, as the Ag2S composition approached stoichiometry, both leakage current and threshold voltage decreased, alleviating the voltage–time dilemma typically encountered in filamentary switching devices. These enhanced properties are attributed to the local phase transition of Ag2S and superionic conductivity of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ag2S, which facilitate rapid ion transport and filament formation under an electric field. Furthermore, at a compliance current of <inline-formula> <tex-math>$30~mu $ </tex-math></inline-formula>A, the device demonstrated a turn-off speed of tens of nanoseconds. By increasing the compliance current to several hundred microamperes, the device also exhibited a short-term retention of several minutes, showing potential for application in next-generation DRAM-like volatile memory.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4916-4921"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic Threshold Voltage Drift of Silicon Carbide MOSFET With Drain Stress","authors":"Huapping Jiang;Yao Li;Xinxin Li;Mengya Qiu;Nianlei Xiao;Lei Tang;Xiaohan Zhong;Ruijin Liao","doi":"10.1109/TED.2025.3592639","DOIUrl":"https://doi.org/10.1109/TED.2025.3592639","url":null,"abstract":"Silicon carbide (SiC) MOSFETs are widely favored for their excellent performance. However, reliability concerns have hindered their rapid development, with threshold voltage drift being one of the key concerns. Although threshold voltage drift under static and dynamic gate stress has been widely investigated, limited attention has been paid to the threshold voltage drift induced by drain stress. In this work, a dedicated test platform for SiC MOSFETs was developed, enabling independent and decoupled application of gate and drain stresses. Moreover, the drain stress can be further decomposed into voltage and current components for more detailed analysis. In addition, TCAD simulations were used to investigate the mechanisms underlying the different threshold voltage drifts induced by various stress modes. It was found that drain stress has a noticeable effect on threshold voltage drift, which cannot be neglected. Moreover, there is a coupling effect between drain and gate stresses. These findings aim to provide better management and coping strategies for threshold voltage drift in power electronic device applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4802-4809"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced Dye-Sensitized Solar Cells via MoS2 Nanosheets-Modified TiO2 Photoanodes","authors":"Chih-Hsien Lai;Wen-Hao Chen;Jung-Chuan Chou;Chun-Yu Li;Po-Hui Yang;Po-Yu Kuo;Yu-Hsun Nien;Jhih-Wei Zeng","doi":"10.1109/TED.2025.3592167","DOIUrl":"https://doi.org/10.1109/TED.2025.3592167","url":null,"abstract":"Molybdenum disulfide (MoS2), is a novel 2-D material, has recently garnered significant attention. In this study, MoS2 nanosheets (NSs) were synthesized via a liquid-phase exfoliation (LPE) method, and subsequently used to modify the titanium dioxide (TiO2) photoanode of dye-sensitized solar cells (DSSCs). The incorporation of MoS2 NSs not only enhances dye adsorption due to their high specific surface area but also reduces the carrier recombination rate attributed to their excellent carrier mobility. These combined effects contribute to an improvement in the photovoltaic conversion efficiency (PCE) of DSSCs. Notably, the efficiency of DSSCs with MoS2 modification increased from 4.99% to 6.55%, representing a 31% improvement.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5045-5053"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimized SOI Stacked Si Nanosheet Gate-All-Around FET With Ni(Pt)Si Silicide-First and Load-Si Thinning Techniques","authors":"Lei Cao;Guanqiao Sang;Qingzhu Zhang;Jiaxin Yao;Xiaohui Zhu;Qingkun Li;Junjie Li;Jianfeng Gao;Tingting Li;Yihong Lu;Xiaobin He;Zhenhua Wu;Yongliang Li;Junfeng Li;Huaxiang Yin;Jun Luo","doi":"10.1109/TED.2025.3592165","DOIUrl":"https://doi.org/10.1109/TED.2025.3592165","url":null,"abstract":"In this article, to optimize the performance of silicon-on-insulator (SOI) stacked Si nanosheet (NS) gate-all-around field-effect transistor (GAAFET) with long source/drain (S/D) regions, special process techniques of Ni(Pt)Si silicide-first and Load-Si thinning are successfully integrated in the experimental devices. Because of the introduced silicide-first process, the transistor performance merits of <sc>on</small>-current (<inline-formula> <tex-math>${I}_{mathrm {ON}}$ </tex-math></inline-formula>) and transconductance (<inline-formula> <tex-math>${G}_{text {m}}$ </tex-math></inline-formula>) are also increased by 34.19% and 80.55% for the reduction of 68.66% in the S/D parasitic resistance. Meanwhile, compared to the Bulk-Si GAAFET, the gate-induced drain leakage (GIDL) current of the SOI GAAFET is also decreased by more than one order of magnitude. However, the subthreshold characteristics of SOI GAAFETs exhibit a rapid degradation as the gate length (<inline-formula> <tex-math>${L}_{text {g}}$ </tex-math></inline-formula>) scaling, which is mainly due to the effect of parasitic channel in the remaining Load-Si layer. To optimize the leakage and subthreshold characteristics, the electrical impacts of Load-Si thickness (<inline-formula> <tex-math>${T}_{text {Load-Si}}$ </tex-math></inline-formula>) are thoroughly investigated by the experiment and TCAD simulation. The experimental SOI GAAFET fabricated by thinning Load-Si to 19 nm has obtained better subthreshold characteristics, improved normalized <inline-formula> <tex-math>${I}_{mathrm {ON}}$ </tex-math></inline-formula>, and caused an obvious decrease of <sc>off</small>-current (<inline-formula> <tex-math>${I}_{mathrm {OFF}}$ </tex-math></inline-formula>) at <inline-formula> <tex-math>${L}_{text {g}} = {30}$ </tex-math></inline-formula> nm. Meanwhile, the simulation results further show that the SOI GAAFET with shorter <inline-formula> <tex-math>${L}_{text {g}}$ </tex-math></inline-formula> needs to continuously decrease <inline-formula> <tex-math>${T}_{text {Load-Si}}$ </tex-math></inline-formula> to meet the requirements of a fully depleted channel and low <inline-formula> <tex-math>${I}_{mathrm {OFF}}$ </tex-math></inline-formula>.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4685-4690"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A SPICE Model of Electrolyte Synaptic Transistors","authors":"Zuheng Wu;Yang Hao;Hao Ruan;Haochen Wang;Zhihao Lin;Jianxun Zou;Zhe Feng;Wenbin Guo;Yunlai Zhu;Zuyu Xu;Yuehua Dai","doi":"10.1109/TED.2025.3591092","DOIUrl":"https://doi.org/10.1109/TED.2025.3591092","url":null,"abstract":"In recent years, electrolyte synaptic transistors have become a popular choice for neuromorphic computing hardware due to their low power consumption, high linearity, and dynamic conductance modulation capabilities. However, the lack of precise circuit models of electrolyte synaptic transistors limits the convenience of exploring electrolyte transistors-based circuits or systems. In this study, we propose a universal model for electrolyte synaptic transistors by decoupling ionic and electronic transport process. The model is highly flexible and adaptable to various electrolyte synaptic transistor devices, allowing for easy modulation of synaptic characteristics through parameter adjustments. Inspired by the adaptive capabilities of biological sensory systems, we constructed a simplified circuit based on the proposed model and validated it through LTSPICE simulations. The results demonstrate that the model accurately captures the pulse modulation capabilities of electrolyte synaptic transistors and effectively simulates the response characteristics of biological sensory neurons. The proposed electrolyte synaptic transistor model would facilitate the convenience of exploring electrolyte transistors-based circuits or systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4902-4909"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extended Photodiode Scheme for Enhancement of Demodulation Contrast in Indirect Time-of-Flight Sensors","authors":"Chan Hee Suk;Jae Hyeon Park;Hyung Soon Kim;Keon-Ho Yoo;Tae Whan Kim","doi":"10.1109/TED.2025.3592909","DOIUrl":"https://doi.org/10.1109/TED.2025.3592909","url":null,"abstract":"Recent indirect time-of-flight (iToF) sensors utilize backside structure technology (BST) to improve quantum efficiency by increasing the absorption of infrared light. However, this technology causes electrons to be generated far from the pixel center, leading to degraded demodulation contrast (DC) due to inefficient charge transfer. This study presents the first in-depth analysis of how the spatial distribution of electron generation affects DC in iToF sensors using TCAD simulations, analyzing both electron transfer ratios and optical generation profiles. We introduce the concept of transfer contrast (TrC), defined as the electron transfer ratio to the memory nodes (MNs), and examine it in conjunction with the probability of optical generation to quantify localized charge transfer inefficiencies. To address the performance degradation, we propose an extended photodiode scheme with vertical and lateral expansion. This design accelerates electrons generated even at the edges of the pixel by introducing additional electric fields across the pixel region, ensuring efficient charge transport to the MN within the pulse time. The proposed scheme enhances DC by 12% and reduces parasitic light sensitivity (PLS) by 18%, with minimal fabrication complexity. This approach is compatible with various pixel sizes and offers improved depth accuracy for infrared imaging applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5067-5072"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interaction of Total Ionizing Dose Effect and Hot Carrier Degradation in Bulk I/O-FinFETs","authors":"Jiangwei Cui;Qiwen Zheng;Yaqing Chi;Bin Liang;Xiaolong Li;Yang Guo;Qi Guo;Yudong Li","doi":"10.1109/TED.2025.3590686","DOIUrl":"https://doi.org/10.1109/TED.2025.3590686","url":null,"abstract":"In this article, the interaction of total ionizing dose (TID) effect and hot carrier injection (HCI) degradation in bulk I/O-<sc>FIN</small> field-effect transistors (FinFETs) is investigated. The results for stress post radiation (SPR) show that the HCI degradation of irradiated devices is greater than that of unirradiated, and the irradiated devices undergo rapid recovery by HCI stress for a very short time. With the increase of stress time, the influence of TID on HCI decreases and the <sc>off</small>-state leakage current after irradiation does not recover to the initial value of the device. The electrons injection into the shallow trench isolation (STI) during HCI is suggested as the reason for parameters recovery after irradiation. While the experiment results of radiation post stress (RPS) show that there is no obvious influence of HCI on TID, since there is no electrons injection into STI region during HCI before TID. The irradiation experiment under HCI bias shows that the combination of these two effects causes the change of device characteristics. The mechanism of interaction between TID and HCI is revealed.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4662-4668"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact Model for Polarization-Graded HEMTs Demonstrating Enhanced Linearity","authors":"Mohammad Sajid Nazir;Mir Mohammad Shayoub;Nivedhita Venkatesan;Patrick Fay;Yogesh Singh Chauhan","doi":"10.1109/TED.2025.3592176","DOIUrl":"https://doi.org/10.1109/TED.2025.3592176","url":null,"abstract":"This article presents an approach for modeling polarization-graded gallium nitride (GaN) high-electron-mobility transistors (HEMTs). Unlike conventional GaN HEMTs, where a 2-D electron gas (2DEG) forms at the barrier–channel interface, graded structures feature a 3-D electron distribution. TCAD simulations are used to extract carrier density and energy band diagrams, which form the basis for model development. The derivation uses refined approximations for the Fermi–Dirac integral solution, ensuring differentiability while accurately correlating carrier density with the applied gate bias through the use of potential balance. A surface-potential-based approach is subsequently used to model terminal currents and charges. Validation of the model is done through comparison with on-wafer measurements and published data, including dc transfer and output characteristics and measured S-parameters over the frequency range of 10 MHz–110 GHz. Furthermore, model accuracy in representing linearity is verified by comparing to large signal and intermodulation measurements at 10 GHz.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4795-4801"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}