IEEE Transactions on Electron Devices最新文献_第4页

Program Pulse Control for Program Efficiency and Disturbance of 3D-NAND Flash Using Novel Machine Learning-Based Pareto Optimization 利用基于机器学习的帕累托优化新方法控制程序脉冲，提高 3D-NAND 闪存的编程效率和干扰度

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3469186

Kihoon Nam;Donghyun Kim;Hyeok Yun;Chanyang Park;Hyundong Jang;Kyeongrae Cho;Seungjoon Eom;Jiyoon Kim;Seonhaeng Lee;Namhyun Lee;Gang-Jun Kim;Rock-Hyun Baek

{"title":"Program Pulse Control for Program Efficiency and Disturbance of 3D-NAND Flash Using Novel Machine Learning-Based Pareto Optimization","authors":"Kihoon Nam;Donghyun Kim;Hyeok Yun;Chanyang Park;Hyundong Jang;Kyeongrae Cho;Seungjoon Eom;Jiyoon Kim;Seonhaeng Lee;Namhyun Lee;Gang-Jun Kim;Rock-Hyun Baek","doi":"10.1109/TED.2024.3469186","DOIUrl":"https://doi.org/10.1109/TED.2024.3469186","url":null,"abstract":"We propose a novel approach that combines machine learning (ML) and Pareto optimization to simultaneously enhance the program efficiency and disturbance of 3D-NAND flash memory. The relationship between program pulse (PP) shapes and threshold voltage shifts has never been investigated owing to the presence of numerous PP shapes. The complex relationship is modeled rapidly and quantitatively by leveraging ML. A multiobjective optimization problem is designed to consider the trade-off in program efficiency and disturbance. Pareto optimization facilitates determining PP shapes that achieve optimal solutions between maximizing program efficiency and minimizing program disturbance. The Pareto front provides practical and intuitive candidates for determining optimal PP shapes. Experimental results confirm that the program efficiency and disturbance can be enhanced by 14%–22% and 5%–40%, respectively. The ML-based Pareto optimization has the potential to vary the pulse conditions for desired operations in 3D-NAND flash, which is the biggest nonvolatile memory market in the semiconductor industry.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6713-6718"},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evolution of Point Defects in Chip-Level Silicon-Based MOSFET Under Transmission Line Pulse Stress 传输线脉冲应力下芯片级硅基 MOSFET 中点状缺陷的演变

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3466840

Xinyuan Zheng;Huiying Li;Yibo Ning;Chengbing Pan;Kai Wang;Lixia Zhao

引用次数: 0

Theoretical Investigation on Down-Taper-Type Frequency-Tunable Reflective Gyro-BWO 下锥型频率可调反射式陀螺-BWO 的理论研究

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3468301

Tien-Fu Yang;Chia-Chuan Chang;Hsin-Yu Yao;Tsun-Hsu Chang

引用次数: 0

Utilizing Spiro-Type Backbone Donor to Develop Exciplex Emitter and Highly Efficient Phosphorescent OLEDs With Low Efficiency Roll-Off 利用螺型骨架供体开发具有低效率滚降特性的激发器和高效磷光 OLED

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3469176

Ming Zhang;Xiao-Cui Ma;Heng-Yuan Zhang;Gang Yang;Hui Lin;Cai-Jun Zheng;Xiaoyang Du;Silu Tao

{"title":"Utilizing Spiro-Type Backbone Donor to Develop Exciplex Emitter and Highly Efficient Phosphorescent OLEDs With Low Efficiency Roll-Off","authors":"Ming Zhang;Xiao-Cui Ma;Heng-Yuan Zhang;Gang Yang;Hui Lin;Cai-Jun Zheng;Xiaoyang Du;Silu Tao","doi":"10.1109/TED.2024.3469176","DOIUrl":"https://doi.org/10.1109/TED.2024.3469176","url":null,"abstract":"New electron-donating materials are crucial for developing efficient exciplex emitters and host matrices in simplified phosphorescent organic light-emitting diodes (PhOLEDs) with low driving voltage, high efficiency, and minimal efficiency roll-off. Herein, a spiro backbone with a highly sterically rigid structure and orthogonal configuration was attached to the commonly used 9H-carbazole (Cz) via para-linking, resulting in a new electron-donating material 9-(9,\u0000<inline-formula> <tex-math>$9'$ </tex-math></inline-formula>\u0000-spirobi[fluoren]-2-yl)- 9H-Cz (SBF-Cz). The influence of the donor strength on the photophysical, electrochemical, and electroluminescent performances was studied. SBF-Cz exhibits a high T1 level, a shallow highest occupied molecular orbital (HOMO) level, and excellent thermal properties. Utilizing these properties, a simplified blue organic light-emitting diode (OLED) using SBF-Cz:2,4,6-Tris[3-(diphenylphosphinyl)phenyl]-1,3,5-triazine (PO-T2T) as the emitter achieves an EL emission peak at 476 nm and a maximum external quantum efficiency (EQEmax) of 11.2%. Furthermore, the spiro-type exciplex as a universal host was systematically investigated in blue, green, and red PhOLEDs. Notably, the EQEmax of blue, green, and red PhOLEDs using the spiro-type exciplex as host improved by 6.8%, 23.8%, and 11.1%, respectively, compared to the conventional host mCP. Additionally, the blue, green, and red PhOLEDs exhibit lower EQE roll-off of 8.7%, 8.1%, and 1.2% at a brightness of 1000 cd\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000m-2 compared to the reference devices. This work underscores the significance of the spiro-type donor in developing new blue exciplexes and host matrices for OLEDs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6864-6870"},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Strategy to Achieve High-Performance Titanium-Doped InZnO Thin-Film Transistors Using Atomic Layer Deposition 利用原子层沉积实现高性能掺钛 InZnO 薄膜晶体管的新策略

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3466836

Tianxing Hu;Min Li;Hua Xu;Hong Tao;Jianhua Zou;Junhong Zhou;Miao Xu;Junbiao Peng;Lei Wang

引用次数: 0

Investigation of the Modulated Threshold Memristor for Tunable Artificial Neuron 用于可调人工神经元的调制阈值记忆晶体管研究

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3468289

Yongzhou Wang;Xiao Huang;Hui Xu;Rongrong Cao;Yi Sun;Peiwen Tong;Bing Song;Wei Wang;Qingjiang Li

{"title":"Investigation of the Modulated Threshold Memristor for Tunable Artificial Neuron","authors":"Yongzhou Wang;Xiao Huang;Hui Xu;Rongrong Cao;Yi Sun;Peiwen Tong;Bing Song;Wei Wang;Qingjiang Li","doi":"10.1109/TED.2024.3468289","DOIUrl":"https://doi.org/10.1109/TED.2024.3468289","url":null,"abstract":"Threshold switching (TS) memristor with a simple structure and high biomimetic offers a more promising way to implement an efficient artificial neuron than traditional methods. To accommodate the complex environments in practical applications, previous memristor-based neurons typically incorporate auxiliary circuits to ensure tunability within circuits. However, this addition not only heightens the design complexity but also reduces the efficiency. In this work, we investigate the conduction process under different thresholds in an NbOx-based memristor and further demonstrate its potential merits in human face recognition. The negative threshold voltage of the device can be linearly modulated by positive stimuli. The conduction mechanisms under different threshold states are systematically investigated by experiments and theoretical analysis, showing that the defects concentration controlled by the electrical field is attributed to the threshold modulation. The revealed mechanism is instructive for device optimization, offering an oxygen-related fabrication method. Based on such a device, we construct a tunable spiking neuron whose threshold can be modulated by only one preoperation on the neuron without other burdensome units. By modulating the threshold based on the light intensities—a lower threshold for the bright condition and a higher threshold for the dark condition—the temporal features of the neuron outputs can be maintained at a normal condition to ensure the correct recognition under different environmental luminance. The function of the proposed tunable neuron is further evaluated in a network for human face recognition. The network finally reaches a 93.25% accuracy with tunable threshold neurons, significantly surpassing the 71.87% with fixed-threshold neurons.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7177-7183"},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs 改善 3 纳米以下节点硅纳米片场效应晶体管电热特性的沟道微调工艺

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI: 10.1109/TED.2024.3469171

Sanguk Lee;Jinsu Jeong;Rock-Hyun Baek

{"title":"Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs","authors":"Sanguk Lee;Jinsu Jeong;Rock-Hyun Baek","doi":"10.1109/TED.2024.3469171","DOIUrl":"https://doi.org/10.1109/TED.2024.3469171","url":null,"abstract":"This study examined the electrical and thermal behaviors of nanosheet (NS) field-effect transistors (NSFETs) with trimmed channels using a technology computer-aided design (TCAD) simulation. NSFETs are expected to exhibit excellent electrical behaviors owing to thin gate-all-around (GAA) channels. However, NSFETs still suffer from: 1) high punchthrough current (\u0000<inline-formula> <tex-math>${I}_{text {PTS}}$ </tex-math></inline-formula>\u0000) in the punchthrough stopper (PTS) region and 2) poor heat dissipation by the thin channel thickness. Thus, to resolve these problems, this study proposed NSFETs with trimmed NS channels and a trench gate in the PTS region. This structure can be formed via the deposition of thick silicon layers during Si/SiGe stacking and consequently trimming the silicon regions (NS channels, PTS region) following the channel release. Consequently, the trench gate strengthened the gate controllability for the PTS region, exhibiting remarkable \u0000<inline-formula> <tex-math>${I}_{text {PTS}}$ </tex-math></inline-formula>\u0000 suppression. In addition, untrimmed thick channel ends improved heat transfer, whereas the trimmed channel centers provided excellent gate controllability. Therefore, the trimming process, which formed trimmed channels and a trench gate, is expected to simultaneously solve the inherent electrical and thermal issues encountered in NSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7184-7191"},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part II: Circuit-Compatible Modeling 考虑表面散射的矩形互连器件空间分辨电导率--第二部分：电路兼容建模

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-04 DOI: 10.1109/TED.2024.3467029

Xinkang Chen;Sumeet Kumar Gupta

{"title":"Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part II: Circuit-Compatible Modeling","authors":"Xinkang Chen;Sumeet Kumar Gupta","doi":"10.1109/TED.2024.3467029","DOIUrl":"https://doi.org/10.1109/TED.2024.3467029","url":null,"abstract":"In Part I of this work, we had presented a spatially resolved model for conductivity of interconnects capturing surface scattering based on the well-known Fuchs-Sondheimer (FS) approach. However, the proposed spatially resolved FS (SRFS) model involves computing complicated integrals making it ill-suited for circuit simulations. In this part, we build upon our SRFS model to develop a circuit-compatible conductivity model for rectangular interconnects accounting for 2-D surface scattering. The proposed circuit-compatible model offers spatial resolution of conductivity as well as explicit dependence on the physical parameters such as electron mean free path (\u0000<inline-formula> <tex-math>$lambda _{{0}}$ </tex-math></inline-formula>\u0000), specularity (p), and interconnect geometry. We validate our circuit-compatible model over a range of physical parameters showing a close match with the physical SRFS model proposed in Part I (with error <0.7%). We also compare our circuit-compatible model with a previous spatially resolved analytical model (appropriately modified for a fair comparison) and show that our model captures the spatial resolution of conductivity and the dependence on physical parameters more accurately. Finally, we present a semi-analytical equation for the average conductivity based on our circuit-compatible model.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6950-6957"},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Manipulating Band-to-Band Tunneling Current in Low-Voltage pMOS Devices in BCD Technology: A TCAD and Experimental Investigation 操纵 BCD 技术中低压 pMOS 器件的带间隧道电流：TCAD 和实验研究

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-04 DOI: 10.1109/TED.2024.3466842

Guglielmo Albani;Elena Rebussi;Emanuele D’Ambrosio;Annalisa Gilardini;Alessandra Manca;Pietro Miccichè;Daria Doria;Pierpaolo Monge;Elia Sora;Silvia Vangelista;Emanuele Viganò

{"title":"Manipulating Band-to-Band Tunneling Current in Low-Voltage pMOS Devices in BCD Technology: A TCAD and Experimental Investigation","authors":"Guglielmo Albani;Elena Rebussi;Emanuele D’Ambrosio;Annalisa Gilardini;Alessandra Manca;Pietro Miccichè;Daria Doria;Pierpaolo Monge;Elia Sora;Silvia Vangelista;Emanuele Viganò","doi":"10.1109/TED.2024.3466842","DOIUrl":"https://doi.org/10.1109/TED.2024.3466842","url":null,"abstract":"This study investigates the issue of reducing band-to-band leakage current in low-voltage (LV) CMOS devices realized using BCD technology. Through TCAD simulations and comprehensive experimental characterization, the influence of key process parameters on leakage current in this category of devices is examined. The presented findings suggest that band-to-band tunneling (B2B) can be significantly mitigated by carefully selecting the rapid thermal processing (RTP) annealing temperature. Subsequently, we address the side effects of the modification of the process parameter on the electrical performance of the devices, aiming to recover affected electrical figures of merit through precise adjustments to the process working point. The study shows that this goal can be reached by a proper modification of the p+ implant energy. In the end, a statistical analysis is presented, with the purpose of understanding the impact of these process changes on the distribution of defects. This research not only proposes a method to tackle the well-known issue of B2B current but also provides valuable insight into the steps required to achieve substantial enhancements in the electrical performance of components by fine-tuning BCD process parameters.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6927-6933"},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Approach to Extract the Trap States via the Dynamic Ron Method With Substrate Voltage Applied During the Recovery Time 在恢复时间内施加基底电压，通过动态罗恩法提取陷阱状态的方法

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-04 DOI: 10.1109/TED.2024.3467038

Ya-Huan Lee;Po-Hsun Chen;Yong-Ci Zhang;Chung-Wei Wu;Sheng-Yao Chou;Yu-Bo Wang;Hung-Ming Kuo;Yu-Shan Lin;Yan-Ta Chen;Yu-Jie Tsai;Ting-Chang Chang

{"title":"An Approach to Extract the Trap States via the Dynamic Ron Method With Substrate Voltage Applied During the Recovery Time","authors":"Ya-Huan Lee;Po-Hsun Chen;Yong-Ci Zhang;Chung-Wei Wu;Sheng-Yao Chou;Yu-Bo Wang;Hung-Ming Kuo;Yu-Shan Lin;Yan-Ta Chen;Yu-Jie Tsai;Ting-Chang Chang","doi":"10.1109/TED.2024.3467038","DOIUrl":"https://doi.org/10.1109/TED.2024.3467038","url":null,"abstract":"This study discusses the application of the substrate voltage during the recovery time with the dynamic on-resistance (dynamic \u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000) method to extract the deep trap states in the buffer layer after the hard-switching stress in p-GaN high electron mobility transistors (p-GaN HEMTs). This method will be more suitable for the detection of the deep trap states where the carriers are difficult to de-trap in the buffer layer. Then, a hard switching stress condition is applied to the device and the degradation is caused by the mechanism of the hot electron effect and the impact ionization. The generated electrons and holes will trap into the buffer layer in the drift region at the gate edge near the drain side and the AlGaN layer under the gate, respectively. Moreover, through the novel of the dynamic \u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000 method with the substrate voltage applied, the deep trap states in the buffer can be extracted.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6616-6619"},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0