IEEE Transactions on Electron Devices最新文献

{"title":"Investigating the Performance of Sub-10-nm WSi2N4 MOSFETs With Native Dielectric Through a Machine Learning Tight-Binding Framework","authors":"Michael Spinazze;Youngki Yoon","doi":"10.1109/TED.2025.3561757","DOIUrl":"https://doi.org/10.1109/TED.2025.3561757","url":null,"abstract":"Monolayer WSi2N4 has emerged as a promising 2-D semiconductor for high-performance ultrascaled MOSFETs. In this work, we use machine learning techniques to generate a sparse tight-binding (TB) Hamiltonian and evaluate the performance of sub-10-nm n-type and p-type WSi2N4 MOSFETs with native Si3N4 as the gate dielectric. To validate our approach, we compare the I–V characteristics generated by our machine learning TB (MLTB) model with those obtained from a TB model using the maximally localized Wannier function (MLWF) approach for a monolayer HfS2 MOSFET, demonstrating excellent agreement. Our results show that both n-type and p-type WSi2N4 MOSFETs meet the International Roadmap for Devices and Systems (IRDS) 2022 <sc>on</small>-current (<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>) target for high-performance (HP) applications at channel lengths (<inline-formula> <tex-math>${L}_{text {ch}}$ </tex-math></inline-formula>) of 5–10 nm. For high-density (HD) applications, n-type and p-type devices can be scaled down to 7 and 8 nm, respectively, while maintaining IRDS compliance. At a 10-nm channel length, n-type devices achieve a higher <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula> than p-type devices, while both exhibit comparable subthreshold swing (SS) close to the 60-mV/dec limit at room temperature. However, as <inline-formula> <tex-math>${L}_{text {ch}}$ </tex-math></inline-formula> decreases, n-type devices experience greater SS degradation than p-type devices due to enhanced source-to-drain tunneling, allowing p-type devices to outperform at shorter channel lengths. In addition, transport simulations reveal directionally isotropic carrier behaviors in WSi2N4. These findings underline the potential of WSi2N4 for next-generation ultrascaled transistors and showcase the utility of machine-learning-based approaches in modeling devices constructed with novel 2-D materials.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3287-3294"},"PeriodicalIF":2.9,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Study of Low-Frequency Noise Origins in Scaled Atomic-Layer-Deposited IGZO TFTs","authors":"Sumi Lee;Chang Niu;Chun-An Shih;Jian-Yu Lin;Zhuocheng Zhang;Yizhi Zhang;Linjia Long;Haiyan Wang;Muhammad A. Alam;Peide D. Ye","doi":"10.1109/TED.2025.3562509","DOIUrl":"https://doi.org/10.1109/TED.2025.3562509","url":null,"abstract":"In this work, we investigate the 1/f noise, i.e., low-frequency noise (LFN), characteristics of scaled atomic-layer-deposited indium-gallium–zinc oxide (IGZO) thin-film transistors (TFTs) focusing on key factors such as: 1) varying indium (In) concentrations; 2) post-thermal annealing; and 3) channel length (<inline-formula> <tex-math>${L}_{text {ch}}text {)}$ </tex-math></inline-formula> scaling. Increasing the In ratio from 2:1:1 to 7:1:1 enhances field-effect mobility (<inline-formula> <tex-math>$mu _{text {FE}}text {)}$ </tex-math></inline-formula> from 11.2 to 36.6 cm2/V and reduces LFN by up to 85%, demonstrating the role of In content in improving both electrical performance and noise characteristics. Post-annealing further mitigates LFN, achieving reductions of up to 68%, depending on the IGZO compositions. As <inline-formula> <tex-math>${L}_{text {ch}}$ </tex-math></inline-formula> scales down, the dominant LFN mechanism shows a tendency to shift from mobility fluctuations (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula><inline-formula> <tex-math>$mu $ </tex-math></inline-formula>) in long-channel devices (<inline-formula> <tex-math>${L}_{text {ch}} = 1~mu $ </tex-math></inline-formula>m) to carrier number fluctuations (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>n) in short-channel devices (<inline-formula> <tex-math>${L}_{text {ch}} =50$ </tex-math></inline-formula> nm), as indicated by the distinct dependence of normalized drain-current power spectral density (<inline-formula> <tex-math>${S}_{text {ID}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {D}}^{{2}}text {)}$ </tex-math></inline-formula> on gate overdrive voltage. This behavior, supported by LFN measurements at elevated temperatures (<inline-formula> <tex-math>$sim 125~^{circ }$ </tex-math></inline-formula>C) and bias temperature instability (BTI) analyses, highlights the increasing influence of near-interface traps in scaled devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2993-2999"},"PeriodicalIF":2.9,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Fabrication of a Novel 1200 V 4H-SiC Trench MOSFET With Periodically Grounded Trench Bottom Shielding","authors":"Jun Yuan;Wei Chen;Fei Guo;Kuan Wang;Zhijie Cheng;Yangyang Wu;Shaodong Xu;Rong Zhang;Guoqing Xin;Zhiqiang Wang","doi":"10.1109/TED.2025.3559888","DOIUrl":"https://doi.org/10.1109/TED.2025.3559888","url":null,"abstract":"In this article, a silicon carbide (SiC) trench MOSFET with periodically grounded p-type shielding region (P+SLD) at the trench bottom (PGP-TMOS) is designed and experimentally demonstrated. There exist deep-implanted P+ (DP) regions on both sides of the trench and the P+SLD is grounded by connecting to the DP region periodically. Therefore, the PGP-TMOS owns two different schematic cross section views. The P+SLD and DP region together improve the robustness of the gate oxide. A current spreading layer (CSL) by epitaxy is introduced to improve the device performance. Numerical 2D-simulation results show that compared with the trench MOSFET with floating P+SLD (FP-TMOS), the peak electric field in the gate oxide (<inline-formula> <tex-math>${E}_{text {ox,peak}}text {)}$ </tex-math></inline-formula> is decreased by 50.77% while the breakdown voltage (BV) and specific <sc>on</small>-resistance (<inline-formula> <tex-math>${R}_{text {on,sp}}text {)}$ </tex-math></inline-formula> keep almost the same. In addition, the PGP-TMOS demonstrates superior switching characteristics. The PGP-TMOS has been manufactured on different wafers. When single epitaxial wafers are used, BV of the samples is only 1300 V and the conduction characteristic is poor due to the junction field-effect transistor (JFET) effect and ion implantation scattering. BV and <inline-formula> <tex-math>${R}_{text {on,sp}}$ </tex-math></inline-formula> are improved to 1570 V and 5.96 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2, respectively, when the PGP-TMOS is manufactured on wafers with a CSL layer introduced by epitaxy. BV and <inline-formula> <tex-math>${R}_{text {on,sp}}$ </tex-math></inline-formula> are improved by 20.77% and 91.85%, respectively, compared with the former ones. Moreover, the influence of the key parameters on the PGP-TMOS is discussed, which provides guidance for subsequent optimization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3063-3067"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stack Optimization of TiOx-Based Resistive Switching Devices Through Interface Engineering","authors":"Yu Shi;Manoj Sachdev;Guo-Xing Miao","doi":"10.1109/TED.2025.3561703","DOIUrl":"https://doi.org/10.1109/TED.2025.3561703","url":null,"abstract":"Metal-oxide-based resistive switching random access memory (RRAM) is a promising candidate for next-generation embedded memory due to its simple structure, fast switching speed, and compatibility with CMOS fabrication processes. To enhance its compute density and reduce power consumption, integrating RRAM devices into advanced technology nodes is crucial, necessitating the scaling down of device area and operational voltage. This study explores the influence of bottom TiN electrodes with varying growth conditions, revealing a strong correlation between forming voltage and nitrogen concentration in TiN. In addition, the relationship between forming voltage and high-resistance state (HRS) resistance is examined, showing that lower forming voltages result in higher HRS resistance. Nitrogen plasma treatment of both bottom and top electrode interfaces effectively reduces forming voltage without compromising HRS resistance. These findings provide guidelines for optimizing TiOx-based RRAM devices for compute-in-memory (CIM) applications and can be generalized to similar metal-oxide-based RRAM devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2964-2969"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spectrum Continuously Tunable White LED Based on Bilayer Thickness-Graded Quantum Dots","authors":"Hua Xiao;Qiannan Jiang;Haiyun Chen;Qiaoyang Zhang;Mingxin Liu;Wensong Wang","doi":"10.1109/TED.2025.3561249","DOIUrl":"https://doi.org/10.1109/TED.2025.3561249","url":null,"abstract":"Regulating the emission spectrum of white light-emitting diode (WLED) is crucial for enhancing lighting quality and advancing smart lighting technology. This study proposes a device to achieve continuous tunability of the multicolor emission spectrum by designing a bilayer cadmium selenide (CdSe)-based quantum-dot (QD) light-conversion structure and the corresponding illuminating control system. Spectral modulation is achieved by a three-pronged approach: 1) the fabrication of the thickness-graded QD film; 2) preassembly monochromatic spectra characterization and spectral optimization; and 3) postassembly mechanical control of a push rod connected to the blue LED chip. Compared to others, the proposed approach provides precise control over continuous spectra modulation in both simulation and experimental settings using just two parameters: driving voltage and blue LED chip position. This device offers a wide range of options for correlated color temperature (CCT) ranging from approximately 2000–60 000 K and illuminance from approximately 0–200 lx. Furthermore, the detailed study of light modulation offers viable approaches for realizing tunable WLEDs in smart lighting and Internet of Things (IoT) systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3035-3042"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Field-Emission Light Sources Based on Porous Silicon Planar Electron Emitter","authors":"He Li;Li Sailei;He Qi;Sun Wenqi;Luo Wei;Shen Guiying","doi":"10.1109/TED.2025.3562507","DOIUrl":"https://doi.org/10.1109/TED.2025.3562507","url":null,"abstract":"This article proposes a novel field-emission light source (FELS) with a simplified structure that can be operated under low-pressure conditions. The flat-format FELS, driven by a porous silicon (PS)-based planar electron emitter, exhibits bright luminescence at a low field emission current density of approximately <inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>A/cm2 even at the ambient pressure as high as <inline-formula> <tex-math>$10^{{2}}$ </tex-math></inline-formula> Pa. This suggests the favorable energy conversion efficiency for this FELS device. Moreover, this novel FELS achieves reduced thermal effects and power consumption due to its lower driving voltage and conduction current compared with the conventional device. The repeatability within 8% and the stability below 3% of the PS planar emitter further supports its potential for FELS applications. As a promising on-chip electron source, the PS-based cold cathode opens avenues for future high-performance, low cost, silicon-compatible FELS with large area and operation at ambient pressure.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3219-3224"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144190570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Addressing the Connectivity Bottleneck With BEOL FeFETs for 3-D CMOS + X Ising Machines","authors":"Tanvir H. Pantha;Abhishek Khanna;Huacheng Ye;Shaila Niazi;Miriyala P. Kamal;Biswadeep Chakraborty;Shumiya Alam;Ethan Weinstock;Nithin Babu;Saibal Mukhopadhyay;Yun Chiu;Suman Datta;Kerem Y. Camsari;Sourav Dutta","doi":"10.1109/TED.2025.3562510","DOIUrl":"https://doi.org/10.1109/TED.2025.3562510","url":null,"abstract":"Recent advancements in Ising machines present an exciting new paradigm for addressing computationally intensive problems with superior energy efficiency and speed compared to conventional digital computers. Despite these promising developments, many real-world problems demand high connectivity, a requirement that exceeds the capabilities of current CMOS-based Ising machine hardware. To overcome this connectivity bottleneck, we propose a novel approach leveraging programmable multibit back-end-of-line (BEOL) ferroelectric field-effect transistor (FeFETs) capable of monolithic 3-D stacking. We experimentally demonstrate a 10-node, 24-coupling Ising machine utilizing dual-gated BEOL FeFETs. This platform enables real-time reconfigurability and supports diverse computational workloads, including combinatorial optimization problems and energy-based learning. Our platform demonstrates robust error-resilient computation with minimal accuracy degradation, even under high endurance conditions of up to 10 billion read and write cycles. This resilience is critical for both read-intensive forward problems and write-intensive inverse or learning problems. To evaluate the performance and area gains, we benchmark the proposed FeFET-based architecture against traditional CMOS implementations. The results reveal significant advantages for FeFET technology, including an <inline-formula> <tex-math>$8.2times $ </tex-math></inline-formula> increase in coupling density, an <inline-formula> <tex-math>$11times $ </tex-math></inline-formula> improvement in energy efficiency, and a <inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula> reduction in latency.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3335-3342"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"One-Ferroelectric-Tunnel-FET-Based Reconfigurable Logic Gates","authors":"Jaemin Yeom;Minjeong Ryu;Jae Seung Woo;Jin Wook Lee;Seonggeun Kim;Seungwon Go;Sangwan Kim;Woo Young Choi","doi":"10.1109/TED.2025.3561710","DOIUrl":"https://doi.org/10.1109/TED.2025.3561710","url":null,"abstract":"A novel reconfigurable logic gate (RLG) utilizing one ferroelectric tunnel field-effect transistor (FeTFET) is proposed for the first time. By leveraging the symmetric ambipolar current of the TFET and the minor loop behavior of the ferroelectric, <sc>nand/or/xnor/imp/rimp</small> operations are performed within a single FeTFET, enabling logic-in-memory (LiM) with high area efficiency. It is demonstrated that two inputs can be programmed in two steps, and the type of logic operation can be changed by simply altering the read voltage. The proposed FeTFET-based RLGs consume >99% lower operation energy than FeFET-based ones.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3302-3306"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physics-Based Compact Modeling for the Drain Current Variability in Single-Layer Graphene FETs","authors":"Nikolaos Mavredakis;Anibal Pacheco-Sanchez;Ramon Garcia Cortadella;Anton-Guimerà-Brunet;Jose A. Garrido;David Jiménez","doi":"10.1109/TED.2025.3560616","DOIUrl":"https://doi.org/10.1109/TED.2025.3560616","url":null,"abstract":"For the growth of emerging graphene field-effect transistor (GFET) technologies, a thorough characterization of on-wafer variability is required. Here, we report for the first time a physics-based compact model, which precisely describes the drain current (<inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula>) fluctuations of monolayer GFETs. Physical mechanisms known to generate 1/f noise in transistors, such as carrier number and Coulomb scattering mobility fluctuations, are also revealed to cause <inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula> variance. Such effects are considered in the model by being activated locally in the channel and the integration of their contributions from source to drain results in total variance. The proposed model is experimentally validated from a statistical population of three different-sized solution-gated (SG) GFETs from strong p- to strong n-type bias conditions. A series resistance <inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula> variance model is also derived mainly contributing at high carrier densities.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3314-3321"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monolithically Integrated Hydrogen-Terminated Diamond FET Logic Circuits","authors":"Yuesong Liang;Wei Wang;Genqiang Chen;Fei Wang;Yuxiang Du;Minghui Zhang;Yanfeng Wang;Hong-Xing Wang","doi":"10.1109/TED.2025.3563146","DOIUrl":"https://doi.org/10.1109/TED.2025.3563146","url":null,"abstract":"Logic circuits are the first step toward integrated circuits. Here, we fabricated the monolithically E/R logic, direct coupled E/E logic, and E/D inverter logic circuit with respective loads of resistor, enhancement field-effect transistor (FET), and depletion FET using hydrogenated diamond and observed the performance of these logic circuits. The gain and voltage swing of E/R logic circuits are strongly influenced by the value of the load resistance, which are commonly employed in separate components. E/E logic circuit exhibits small voltage swing, low gain, and low noise margin. E/D logic circuits present significant advantages in terms of voltage swing, gain, noise margins, and power consumption over E/R and E/E logic circuits. The E/D mode circuit shows a logic voltage swing of −9.44 V, a voltage gain of 15.5 V/V, low-/high-noise margins of 0.82/7.07 V, and static power consumption of <inline-formula> <tex-math>$10^{-{3}}$ </tex-math></inline-formula> W and proper functions up to at least <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C at a supply voltage of −10 V. These results show great potential for diamond smart power integrated circuit application.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2834-2840"},"PeriodicalIF":2.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}