IEEE Transactions on Electron Devices最新文献

{"title":"Comprehensive Investigation of Bias Stress-Induced Instabilities in Highly Scaled ZnO FeFETs: Impact of Channel Thickness, Channel Length, and Switching Cycles","authors":"Chen Sun;Qiwen Kong;Gan Liu;Dong Zhang;Leming Jiao;Xiaolin Wang;Jishen Zhang;Haiwen Xu;Yang Feng;Rui Shao;Yue Chen;Xiao Gong","doi":"10.1109/TED.2025.3555263","DOIUrl":"https://doi.org/10.1109/TED.2025.3555263","url":null,"abstract":"We present a comprehensive study of instabilities induced by positive and negative bias stress (PBS/NBS) in zinc oxide (ZnO) ferroelectric field-effect transistors (FeFETs), focusing on the dependence of threshold voltage (<inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula>) and memory window (MW) dynamics on channel thickness (<inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula>), channel length (<inline-formula> <tex-math>${L} _{text {CH}}$ </tex-math></inline-formula>), and switching cycles. Based on Zr-doped HfO2 (HZO) and by optimizing <inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula> and scaling <inline-formula> <tex-math>${L} _{text {CH}}$ </tex-math></inline-formula> down to 45 nm, high-performance ZnO FeFETs with an HZO-Al2O3–HZO ferroelectric (Fe) stack and an atomic layer deposition (ALD)-deposited channel are realized, achieving a large MW of 3.0 V, robust retention, and high endurance exceeding 108 cycles. Bias stress investigations reveal several key findings. First, devices with thinner <inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula> exhibit higher <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> susceptibility under PBS and NBS, which attributed to stronger electron trapping effects and the generation of more disorder state (DS) O2- defects, respectively. Thanks to the strengthened effect of NBS-enhanced erasing, thinner <inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula> results in better MW tolerance during NBS, thus partially offsetting the MW degradation due to polarization pinning. Second, this NBS-enhanced erasing effect is particularly pronounced in short-channel devices (<inline-formula> <tex-math>${L} _{text {CH}} = 45$ </tex-math></inline-formula> nm), even leading to an increase in MW. In contrast, during PBS, <inline-formula> <tex-math>${L} _{text {CH}}$ </tex-math></inline-formula> has little impact on <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> and MW instabilities. Finally, it is observed that the degraded MW in heavily cycled devices can be slightly recovered after NBS.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2334-2340"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Amorphous Indium Oxide Channel FEFETs With Write Voltage of 0.9 V and Endurance >1012 for Refresh-Free Embedded Memory","authors":"Sharadindu Gopal Kirtania;Hyeonwoo Park;Omkar Phadke;Eknath Sarkar;Dyutimoy Chakraborty;Faaiq G. Waqar;Jaewon Shin;Asif Khan;Shimeng Yu;Suman Datta","doi":"10.1109/TED.2025.3554471","DOIUrl":"https://doi.org/10.1109/TED.2025.3554471","url":null,"abstract":"This work presents, for the first time, a back-end-of-the-line (BEOL)-compatible W-doped indium oxide (IWO) ferroelectric field-effect transistor (FEFET) with a record-low operating voltage below 0.9 V and a write speed of 20 ns while achieving a transient read current window (CW) ratio (<inline-formula> <tex-math>${I}_{text {LVT}}/{I}_{text {HVT}}$ </tex-math></inline-formula>) greater than <inline-formula> <tex-math>${10}^{{4}}$ </tex-math></inline-formula>. The device also exhibits exceptional reliability characteristics such as: 1) measured bipolar write endurance up to <inline-formula> <tex-math>${10}^{{12}}$ </tex-math></inline-formula> cycles; 2) a fast read speed of 50 ns; 3) read endurance surpassing <inline-formula> <tex-math>${10}^{{12}}$ </tex-math></inline-formula> cycles; and 4) retention exceeding <inline-formula> <tex-math>${10}^{{4}}$ </tex-math></inline-formula> s at <inline-formula> <tex-math>$85~^{circ } $ </tex-math></inline-formula>C. Furthermore, a physics-based numerical model has been developed to investigate the nanoscale characteristics of BEOL FEFET devices, leveraging nucleation-limited switching in HfO2 ferroelectrics and dc characterization to extract material and channel parameters for accurate device simulation. The simulation uncovers the stochastic switching behavior of BEOL amorphous oxide semiconductor (AOS) FEFETs and demonstrates an intrinsic switching time as low as 1 ps, highlighting the potential of BEOL AOS FEFETs for ultrafast memory applications. These results establish AOS FEFETs as a compelling candidate for high-density embedded memory applications for last-level cache (LLC) (L4) in advanced CMOS technology nodes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2691-2699"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10957818","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modified Thermal Model Considering Peltier Effect and Thomson Effect for 4H-SiC GTO Thyristors","authors":"Zihan Zhang;Lei Yuan;Yang Liu;Bo Peng;Weiqun Hou;Peng Dong;Jichao Hu;Fawen Li;Xiaoyan Tang;Renxu Jia;Yuming Zhang","doi":"10.1109/TED.2025.3555258","DOIUrl":"https://doi.org/10.1109/TED.2025.3555258","url":null,"abstract":"Silicon carbide (SiC) gate turn-off thyristors (GTOs), distinguished by their high current density, high blocking voltage, high switching frequency, and excellent thermal resistance, are highly suitable as pulse switches in pulsed power systems. However, their reliability remains a critical issue requiring urgent attention. Existing research on the thermal failure mechanisms of SiC GTOs is limited, partly due to the neglect of p-n junction voltage effects on thermal distribution. In this work, the Seebeck coefficient (S) in the thermodynamic model is modified, which considers for the first time the previously neglected Peltier and Thomson heats induced by the Seebeck effect in 4H-SiC GTOs. Simulation analysis reveals that the modified model captures localized heat concentration beneath the GTO anode with enhanced accuracy. The modified model predicts approximately <inline-formula> <tex-math>$1times 10^{{9}}$ </tex-math></inline-formula> W/cm2 more heat generation within the 6-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m region beneath the anode. This result highlights the model’s ability to capture the Seebeck effect, which was omitted in the default TCAD model, providing a more accurate representation of the thermal behavior in 4H-SiC GTOs and other bipolar power devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2506-2511"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Significant Enhancement of Light Extraction in AlGaN-Based Deep-UV LED Through Ag-Nanodot/Ti/Al Reflective p-Contacts With an Ultra-Thin Ti Barrier","authors":"Fangren Cheng;Sai Pan;Hao Wang;Yan Guo;Haoshan Jin;Fangfang Ren;Yugang Zhou;Hai Lu;Rong Zhang;Youdou Zheng","doi":"10.1109/TED.2025.3556098","DOIUrl":"https://doi.org/10.1109/TED.2025.3556098","url":null,"abstract":"AlGaN-based deep ultra-violet (DUV) LEDs, which emit in the 200–280 nm range, hold great promise for applications in water and air purification, sterilization, and medical diagnostics while light extraction efficiency (LEE) is a primary bottleneck for improving the overall efficiency of deep-ultraviolet light-emitting diodes (DUV LEDs). In this study, guided by finite-difference time-domain (FDTD) simulations, we designed and fabricated Ag-nanodot/Ti/Al reflective p-contacts with an ultra-thin Ti barrier for DUV LEDs. The results demonstrated a 36% increase in wall plug efficiency (WPE) while maintaining good ohmic contact when Ti thickness decreased from 100 to 5 nm. Scanning electron microscope (SEM) analysis revealed the robust stability of the contact structure. The WPE (@51.7 A/cm2, 40 mA) and LEE of the DUV LEDs with Ag-nanodot/Ti/Al p-contacts of 5-nm-thick Ti reached 4.42% and 9.575%, respectively. The results highlight the importance of p-contact reflectivity in achieving high-efficiency DUV LEDs and demonstrate a feasible route for improving the light output power (LOP) of DUV LEDs. This involves optimizing the reflector through metal-composite engineering, guided by FDTD simulations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2438-2443"},"PeriodicalIF":2.9,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-Long Disturb-Free Read Operation With Low Resistance Drift in Phase Change Memory","authors":"Ruoqin Wang;Jia Zheng;Ruobing Wang;Chenchen Xie;Li Xie;Xi Li;Zhitang Song;Xilin Zhou","doi":"10.1109/TED.2025.3555276","DOIUrl":"https://doi.org/10.1109/TED.2025.3555276","url":null,"abstract":"Compute-in-memory requires long endurance in reading of memory device orders of magnitude higher than writing. Variations in resistance of memory cells caused by read disturbance is a critical challenge for neural networks applications of emerging memory technology. Current generated by read voltage causes localized heating in the phase change memory (PCM) cell, which results in structural displacement of active phase change volume and thus appreciable variation in cell resistance. In this work, the effects of reading on both high and low resistance states (HRS and LRS) of PCM after various writing cycles are investigated. A disturb-free read scheme is demonstrated up to 1012 read cycles (~28 h) on the memory cells that experienced 108 write cycles both at <inline-formula> <tex-math>$27~^{circ }$ </tex-math></inline-formula> C and <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula> C. The reduced resistance drift by increasing the read voltage up to 0.5 V is observed which further improves the speed and accuracy of reading. This work shows that carbon-doped Ge2Sb2Te5-based PCM is a promising candidate for compute-in-memory application that requires enormous reading with high-precision.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2633-2639"},"PeriodicalIF":2.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Three-Dimensional Modeling of BEOL TDDB: Variability Specs for Sub-20 nm Half-Pitch Interconnects","authors":"Yu Fang;I. Ciofi;Ph. J. Roussel;A. Lesniewska;V. M. Blanco Carballo;R. Degraeve;I. De Wolf;K. Croes","doi":"10.1109/TED.2025.3554474","DOIUrl":"https://doi.org/10.1109/TED.2025.3554474","url":null,"abstract":"A pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2165-2172"},"PeriodicalIF":2.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultrahigh Frequency and Multichannel Output Skyrmion-Based Nano-Oscillator","authors":"Saumya Gupta;Abhishek Sharma;Debasis Das;Ashwin A. Tulapurkar;Bhaskaran Muralidharan","doi":"10.1109/TED.2025.3554473","DOIUrl":"https://doi.org/10.1109/TED.2025.3554473","url":null,"abstract":"Spintronic-based skyrmion nano-oscillators can generate tunable microwave signals that find a wide range of applications in the field of telecommunication to modern neuromorphic computing systems. Skyrmions within a single ferromagnet (FM) material encounter an undesired Magnus force, which imposes limitations on the oscillator’s frequency, typically reaching only a few gigahertz. However, for applications requiring higher data transmission speeds, oscillator frequencies must be elevated to tens of GHz. Conversely, a bilayer device featuring two FM layers coupled in a synthetic anti-ferromagnetic (SAF) configuration can effectively neutralize the Magnus force. Utilizing the bilayer device concept, we propose a multichannel oscillator design, and using micromagnetic simulations, we demonstrate that our proposed device could achieve an ultrahigh frequency of 41 GHz. The ultrahigh operational frequency represents a <inline-formula> <tex-math>$sim 342times $ </tex-math></inline-formula> improvement compared to the monolayer single skyrmion oscillator. We demonstrate the effectiveness of our proposed multichannel oscillator design by introducing multichannel nanotracks along with multiple skyrmions for enhanced frequency operation. The ultrahigh operational frequency and multichannel output are attributed to three key factors: 1) higher spin-flip length of the spacer (such as Ru) material, separating two FM layers; 2) tangential velocity, proportionality on input spin current along with weak dependence on the radius of rotation of the skyrmion-pair; and 3) skyrmion interlocking in the channel enabled by the multichannel high anisotropy rings and skyrmion-skyrmion repulsion.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2618-2624"},"PeriodicalIF":2.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3-D Vertical Resistive Switching Random Access Memory (3D-VRRAM) With Multilevel Programming for High-Density, Energy-Efficient In-Memory Computing","authors":"D. Bridarolli;C. Zucchelli;P. Mannocci;S. Ricci;M. Farronato;G. Pedretti;Z. Sun;D. Ielmini","doi":"10.1109/TED.2025.3554472","DOIUrl":"https://doi.org/10.1109/TED.2025.3554472","url":null,"abstract":"Resistive random access memory (RRAM) devices offer a broad range of attractive properties for in-memory computing (IMC) applications, such as nonvolatile storage, low read current, and high scalability. IMC allows to overcome the memory bottleneck of data-intensive workloads, such as deep learning on the edge. In this context, 3-D vertical RRAM (3D-VRRAM) is a promising option to achieve high memory cell capacity with low fabrication cost. In this work, we present an HfOx-based 3D-VRRAM crossbar array (CBA) capable of IMC with precise multilevel programming. We show an extensive experimental demonstration of both matrix-vector multiplication (MVM) and inverse/pseudoinverse matrix calculation via IMC on 3D-VRRAM. To further support the parallel IMC application in real-life scenarios, the work also reports a demonstration of relatively large-size problems adopting 2D-RRAM and SRAM-based memory arrays. These results support 3D-VRRAM for high-density, energy-efficient IMC for edge computing applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2677-2684"},"PeriodicalIF":2.9,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10949642","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microwave Power Performance of Buffer-Free AlGaN/GaN MISHEMT With MOCVD Grown Ex Situ SiN","authors":"Amit Bansal;Rijo Baby;Aniruddhan Gowrisankar;Vanjari Sai Charan;R. Muralidharan;Hareesh Chandrasekar;Aditya Sadhanala;Srinivasan Raghavan;Digbijoy N. Nath","doi":"10.1109/TED.2025.3554160","DOIUrl":"https://doi.org/10.1109/TED.2025.3554160","url":null,"abstract":"This work investigates the effect of ex situ MOCVD-grown SiNx gate dielectric and PECVD SiNx passivation layer on the microwave power performance of buffer-free AlGaN/GaN MISHEMT. We fabricated devices on a series of four samples diced from a 4 inch epi: first two samples had no gate dielectric while the latter two had upto 3 nm of ex situ SiNx as the gate dielectric. In each of the categories, one sample had baseline 100 nm SiNx passivation deposited under high frequency plasma conditions, while the other sample had 100 nm bilayer SiNx passivation. Devices had gate length of <inline-formula> <tex-math>$0.22~mu $ </tex-math></inline-formula>m and width of <inline-formula> <tex-math>$2times 50~mu $ </tex-math></inline-formula>m. Samples with no gate dielectric exhibited low 2DEG density <inline-formula> <tex-math>$sim 7times 10^{{12}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}$ </tex-math></inline-formula> possibly due to significant charge depletion by the gate Fermi pinning owing to a thin barrier (10 nm, Al0.3Ga0.7N). Moreover, these HEMTs exhibited high current collapse (CC) <inline-formula> <tex-math>$ge 38$ </tex-math></inline-formula>% irrespective of the passivation scheme when subjected to <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>s pulse. The MISHEMTs on the other hand, exhibited high 2DEG density <inline-formula> <tex-math>$sim 10^{{13}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}$ </tex-math></inline-formula> which also manifested as increased threshold voltage. Gate lag reduced to a mere 4%–6% in MISHEMTs, while under gate-drain double pulsing, the collapse was found to be 27% and 11% for different passivation schemes. Drain current transient (DCT) studies revealed suppression of surface states upon ex situ SiN deposition, and hinted at localized defects. Finally, under 28 V Class B operation at 6 and 10 GHz, output power of 8.1 W/mm power added efficiency (PAE 68%) and 5.2 W/mm (PAE 47%) respectively were measured under pulsed loadpull conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2226-2232"},"PeriodicalIF":2.9,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advancing Toward 4F² 1T1R RRAM With Local NAND-gate and Isolation Scheme","authors":"Shengyu Bao;Zongwei Wang;Yuhang Yang;Qishen Wang;Linbo Shan;Lin Bao;Yimao Cai;Ru Huang","doi":"10.1109/TED.2025.3554165","DOIUrl":"https://doi.org/10.1109/TED.2025.3554165","url":null,"abstract":"In this work, we introduce an innovative <sc>nand</small>-gate array structure that optimizes cell density through local series connection. By implementing a p-well isolation in combination with the substrate bias effect, we effectively mitigate the operating voltage constraints on series-connected cells. This design ensures symmetric read operations and maintains uniform read margins among cells in the <sc>nand</small>-gate array, achieving a record cell size of <inline-formula> <tex-math>$0.045~mu $ </tex-math></inline-formula> m2 at the 40-nm technology node. This design demonstrates robust reliability with an endurance of 100k cycles and a ten-year retention at 150 ° C. Moreover, the implementation of deep trench isolation (DTI) technology enables further density enhancements, with a projected cell area of <inline-formula> <tex-math>$0.0255~mu $ </tex-math></inline-formula> m2 at the 28-nm technology node. This approach offers significant advancements in resistive random access memory (RRAM) density, making it highly suitable for high-density memory and computing applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2327-2333"},"PeriodicalIF":2.9,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}