IEEE Transactions on Electron Devices最新文献_第4页

A Comparative Analysis of Statistical Modeling and Machine Learning Techniques for Predicting the Lifetime of Light Emitting Diodes From Accelerated Life Testing

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3535849

Reem Alsharabi;Leen Almalki;Fidaa Abed;M. A. Majid;Omar A. Kittaneh

引用次数: 0

Robustness Analysis of 1200-V IGBT Under Extremely High-Gate Voltage Stress

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3545403

Peng Liao;Hang Xu;Jianbin Guo;Xinru Chen;Changhao Wang;Qingqing Sun;David Wei Zhang

{"title":"Robustness Analysis of 1200-V IGBT Under Extremely High-Gate Voltage Stress","authors":"Peng Liao;Hang Xu;Jianbin Guo;Xinru Chen;Changhao Wang;Qingqing Sun;David Wei Zhang","doi":"10.1109/TED.2025.3545403","DOIUrl":"https://doi.org/10.1109/TED.2025.3545403","url":null,"abstract":"In this study, the robustness of insulated gate bipolar transistors (IGBTs) under extreme high-gate voltage stress (both positive and negative) is comprehensively investigated. The results indicate that all IGBTs maintain essential electrical characteristics, demonstrating considerable robustness to extreme gate voltage stress. However, varying degrees of degradation are observed depending on the polarity of the applied stress. Specifically, under high-positive gate voltage stress, the threshold voltage remains nearly stable, whereas under high-negative gate voltage stress, a significant increase in the threshold voltage is noted. Based on these findings, the degradation mechanism is proposed and experimentally validated. For negative gate voltage stress, degradation primarily results from electron injection from the gate, with elevated temperatures accelerating this process. In contrast, under positive gate voltage stress, the hole injection efficiency is much lower than that of electrons, and part of the gate voltage is absorbed by the depletion region. Additionally, G–V measurement, C–V measurement, and simulation are conducted to support the proposed mechanism. This work contributes to a deeper understanding of IGBT degradation mechanisms under high-gate voltage stress, offering insights relevant for their application in high-stress operational environments.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1893-1899"},"PeriodicalIF":2.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effects of Residual Stress on the Ferroelectric Properties of Al0.8Sc0.2N Films Sandwiched Between Pt or W Electrodes

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3545391

Xiaoxi Li;Yuan Fang;Bochang Li;Jiuren Zhou;Zhifan Wu;Cizhe Fang;Xiangyu Zeng;Siying Zheng;Yue Hao;Yan Liu;Genquan Han

{"title":"Effects of Residual Stress on the Ferroelectric Properties of Al0.8Sc0.2N Films Sandwiched Between Pt or W Electrodes","authors":"Xiaoxi Li;Yuan Fang;Bochang Li;Jiuren Zhou;Zhifan Wu;Cizhe Fang;Xiangyu Zeng;Siying Zheng;Yue Hao;Yan Liu;Genquan Han","doi":"10.1109/TED.2025.3545391","DOIUrl":"https://doi.org/10.1109/TED.2025.3545391","url":null,"abstract":"In this work, the impacts of the residual stress on the structural and ferroelectric properties of Al0.8Sc0.2N films clamped with different metal electrodes (Pt and W) were investigated. The Pt/Al<inline-formula> <tex-math>$_{mathbf {0.8}}$ </tex-math></inline-formula>Sc0.2N/Pt capacitors exhibited enhanced ferroelectric performance, with coercive fields (<inline-formula> <tex-math>${E} _{text {c}}$ </tex-math></inline-formula>) reduced by 0.2 MV/cm, leakage currents reduced by one order of magnitude and stable polarization switching across frequencies. These improvements are attributed to better crystallographic orientation and larger grain sizes driven by tensile stress. In contrast, W/Al0.8Sc0.2N/W capacitors showed larger leakage currents, higher <inline-formula> <tex-math>${E} _{text {c}}$ </tex-math></inline-formula>, and a greater susceptibility to breakdown. Moreover, the W samples showed diminished retention characteristics, with a 50% loss in nonswitched polarization at <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula> s compared to the Pt counterparts. These issues were related to the compressive stress between W and Al0.8Sc0.2N, resulting in more defects that impeded polarization switching. The findings suggest that the engineering of stress through electrode selection is essential for optimizing the performance of AlScN-based ferroelectric devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1774-1779"},"PeriodicalIF":2.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Finding a Promising CMOS Inverter Architecture With Silicon Nanosheet for Future Technology Node

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3540040

Anjali Goel;Akhilesh Rawat;Brajesh Rawat

{"title":"Finding a Promising CMOS Inverter Architecture With Silicon Nanosheet for Future Technology Node","authors":"Anjali Goel;Akhilesh Rawat;Brajesh Rawat","doi":"10.1109/TED.2025.3540040","DOIUrl":"https://doi.org/10.1109/TED.2025.3540040","url":null,"abstract":"In this work, we systematically explore the static and dynamic performance of silicon nanosheet (NSH)-based complementary metal-oxide–semiconductor (CMOS) inverters, including complementary field-effect transistor (CFET), forksheet (FSH), and standard stacked NSH (s-NSH) configurations, for the 5 nm and beyond technology node. The performance analysis of CMOS inverters is conducted using 3-D process simulations in fully calibrated technology computer-aided design (TCAD) simulation, which is based on the self-consistent solution of the Boltzmann transport equation and Poisson’s equation with quantum and mobility correction terms. Our findings reveal that the CFET inverter achieves remarkable advancements by offering around a 3.7% boost in operating frequency and around −3.7% reduction in power dissipation while decreasing the area footprint by approximately −60.8% compared with the s-NSH inverter for the 1-nm technology node. Although the FSH inverter slightly lags behind CFET in performance metrics, it still outperforms the s-NSH inverter by delivering an around 3% increment in the frequency at an equivalent power level and an area reduction of around −6.9%. Furthermore, CFET demonstrates superior resilience to process parameter variations, including doping fluctuation, oxide thickness, interface trap charges, and channel thickness. This robustness, combined with their compact design and excellent gate electrostatic control, enables CFET inverters to consistently outperform both FSH and s-NSH inverters across all evaluated technology nodes and design parameters. These advantages firmly establish the CFET inverter as the preferred choice for future ultrascale technology nodes and low-power logic applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1574-1581"},"PeriodicalIF":2.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Plasma-Free Nitridation for MOSCAPs and GeOI GAAFETs Utilizing Cyclic Passivation of Ozone/Hydrazine With Low Leakage Current, Low Interface Traps, and High Thermal Stability

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3545401

Xin-Ren Yu;Jia Yuan Hung;Ta-Chun Cho;William Cheng-Yu Ma;Yao-Jen Lee;Yeong-Her Wang

{"title":"Plasma-Free Nitridation for MOSCAPs and GeOI GAAFETs Utilizing Cyclic Passivation of Ozone/Hydrazine With Low Leakage Current, Low Interface Traps, and High Thermal Stability","authors":"Xin-Ren Yu;Jia Yuan Hung;Ta-Chun Cho;William Cheng-Yu Ma;Yao-Jen Lee;Yeong-Her Wang","doi":"10.1109/TED.2025.3545401","DOIUrl":"https://doi.org/10.1109/TED.2025.3545401","url":null,"abstract":"Hydrazine (N2H4) plasma-free nitridation reacts on the interface layer oxidated by ozone, forming a high-quality GeON interfacial layer (IL) through alternating passivation. On metal-oxide-semiconductor capacitor (MOSCAP) with Al2O3/GeON gate stacked, the nitridation of N2H4 can effectively improve the interface quality and bring good electrical properties, such as low gate leakage current (<inline-formula> <tex-math>$3.27times 10^{-{5}}$ </tex-math></inline-formula> A/cm2 at <inline-formula> <tex-math>${V} _{text {G}} = 1$ </tex-math></inline-formula> V) and reduced interface defect density at midgap (<inline-formula> <tex-math>$8.59times 10^{{11}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>$^{-{2}} cdot text { eV}^{-{1}}$ </tex-math></inline-formula>). In addition, this work has fabricated layer-transferred GeOI gate-all-around FET (GAAFET) to verify the IV characteristics of N2H4. Compared with devices passivated with NH3, those with N2H4 have better on-/off-ratio, threshold voltage distribution, and thermal stability. The GeOI GAAFET CMOS inverter exhibits more symmetrical characteristics, indicating that the passivation with N2H4 is suitable for devices with GAA structure.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1597-1603"},"PeriodicalIF":2.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrostatic Discharge and Failure Model of Carbon Nanotube Field-Effect Transistors

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3545011

Yachi Duan;Can Yang;Dong Zhang;Yuepeng Gao;Yichao Sun;Jia Si;Peng Lu;Xiaojing Li;Jianhui Bu;Bo Li

{"title":"Electrostatic Discharge and Failure Model of Carbon Nanotube Field-Effect Transistors","authors":"Yachi Duan;Can Yang;Dong Zhang;Yuepeng Gao;Yichao Sun;Jia Si;Peng Lu;Xiaojing Li;Jianhui Bu;Bo Li","doi":"10.1109/TED.2025.3545011","DOIUrl":"https://doi.org/10.1109/TED.2025.3545011","url":null,"abstract":"The electrostatic discharge (ESD) and failure mechanisms of carbon nanotube field-effect transistors (CNT FETs) were thoroughly investigated via transient current tests and numerical simulations. Experiments demonstrated that CNT FETs have a three-stage ESD process according to transmission-line pulse (TLP) and human-body model (HBM) measurements, vastly different from the snapback phenomenon in conventional Si CMOS transistors. As the drain bias (<inline-formula> <tex-math>${V} _{text {DS}}$ </tex-math></inline-formula>) increases from 2 to 12 V, the ESD mechanism of CNT FETs changes from thermionic emission (first stage) to band-to-band tunneling (second stage), which results in a dynamic discharge impedance. The soft breakdown of the drain-to-gate isolation dielectric contributes to the discharge current in the third stage when <inline-formula> <tex-math>${V} _{text {DS}} gt 12$ </tex-math></inline-formula> V. The breakdown current-induced heating of CNT FETs can cause critical damage to the drain-to-gate isolation dielectric and the metal contacts and eventually result in device failure. Therefore, the drain-to-gate isolation dielectric is identified as the weak spot, requiring optimization to enhance the reliability of CNT FETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1617-1623"},"PeriodicalIF":2.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Extraction of Subgap Density of States in Amorphous In–Ga–Zn–O Thin-Film Transistors by Measuring Capacitor-on-Gate Structure

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-04 DOI: 10.1109/TED.2025.3545603

Soobin An;Junhyeong Park;Jin Kyu Lee;Kyeong-Soo Kang;Ji-Hwan Park;Yuseong Jang;Soo-Yeon Lee

引用次数: 0

A High-Voltage Dual Direction Silicon-Controlled Rectifier Based on Flexible Stacking Strategy

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-03 DOI: 10.1109/TED.2025.3544975

Yang Wang;Zeyu Zhong;Xiangliang Jin;Yuan Wang

{"title":"A High-Voltage Dual Direction Silicon-Controlled Rectifier Based on Flexible Stacking Strategy","authors":"Yang Wang;Zeyu Zhong;Xiangliang Jin;Yuan Wang","doi":"10.1109/TED.2025.3544975","DOIUrl":"https://doi.org/10.1109/TED.2025.3544975","url":null,"abstract":"Electrostatic discharge (ESD) is a critical factor affecting the reliability of automotive electronic chips. However, the structural design of conventional on-chip high-voltage silicon-controlled rectifiers (SCRs) presents numerous challenges. Currently, there is a lack of a simple ESD solution to address the reliability issues in the aforementioned field. Therefore, this brief proposes a simple high-voltage dual direction SCR (DDSCR). The device can achieve a multiplicative increase in holding voltage (<inline-formula> <tex-math>${V} _{h}$ </tex-math></inline-formula>) by flexibly adjusting the ESD characteristics of the unit structure and utilizing a stacked layout of shorting resistors, while the trigger voltage (<inline-formula> <tex-math>${V} _{{t}{1}}$ </tex-math></inline-formula>) remains largely unaffected by the number of unit devices connected in series. We validated the effectiveness of the proposed structure using a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m bipolar-CMOS-DMOS (BCD) process and further analyzed its working principle through technology computer-aided design (TCAD) simulations. The test results indicated that the proposed stacking strategy demonstrated good versatility, providing a simple and reliable solution for on-chip ESD research in various high-voltage applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"2086-2089"},"PeriodicalIF":2.9,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HfO₂–ZrO₂ Superlattice HZO Ultrathin Poly-Si Channel (3.5 nm) Junctionless FeTFTs Exhibiting Superior Endurance and Robust Retention

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-03 DOI: 10.1109/TED.2025.3544188

Dong-Ru Hsieh;Zi-Yang Hong;Huai-En Luo;Wei-Ju Yeh;Jia-Chian Ni;Ciao-Fen Chen;Yen-Fu Lin;Shun-Tsung Lo;Tien-Sheng Chao

{"title":"HfO₂–ZrO₂ Superlattice HZO Ultrathin Poly-Si Channel (3.5 nm) Junctionless FeTFTs Exhibiting Superior Endurance and Robust Retention","authors":"Dong-Ru Hsieh;Zi-Yang Hong;Huai-En Luo;Wei-Ju Yeh;Jia-Chian Ni;Ciao-Fen Chen;Yen-Fu Lin;Shun-Tsung Lo;Tien-Sheng Chao","doi":"10.1109/TED.2025.3544188","DOIUrl":"https://doi.org/10.1109/TED.2025.3544188","url":null,"abstract":"In this study, HfO2–ZrO2 superlattice (SL) HfZrO2 (HZO) 3.5-nm ultrathin poly-Si channel (UTPC) junctionless (JL) ferroelectric thin-film transistors (FeTFTs) with the two types of HfO2/ZrO2 nanolamination (NL) thicknesses (0.5 and 1.0 nm) and a 1.0-nm ZrO2 seed layer were experimentally investigated and discussed their ferroelectricity and reliability for the first time. Compared with the conventional HZO UTPC JL FeTFTs, the SL HZO UTPC JL FeTFTs with a HfO2 and ZrO2 NL thickness of 1 nm achieved a relatively large pristine/residual pulsed memory window (MW) up to 1.09/1.06 V under a very low pulse height <inline-formula> <tex-math>$times $ </tex-math></inline-formula> pulse width down to <inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula> Vs and nearly zero MW degradation rate (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> MW/MW<inline-formula> <tex-math>$_{,text {pristine}}$ </tex-math></inline-formula>) down to 2.8% after the endurance test up to <inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula> cycles. Furthermore, the SL HZO UTPC JL FeTFTs with an NL thickness of 1 nm exhibited a robust 10/298/423 K retention characteristic for 25 h with a sufficiently large pulsed MW of 1.30/1.38/0.65 V, and the synaptic behavior with a maximum channel conductance over 1400 nS. According to pulsed characteristic and reliability viewpoints, the HfO2–ZrO2 SL HZO UTPC JL FeTFTs are greatly promising candidates for 3-D nand nonvolatile memories (NVMs) and neuromorphic systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1756-1762"},"PeriodicalIF":2.9,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Investigation of the Hysteresis and Reliability Mechanism of Amorphous Oxide Semiconductor Thin-Film Transistors Applied in Dynamic Random Access Memory

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-03-03 DOI: 10.1109/TED.2025.3545007

Jie Luo;Yunjiao Bao;Yanyu Yang;Yupeng Lu;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo

{"title":"The Investigation of the Hysteresis and Reliability Mechanism of Amorphous Oxide Semiconductor Thin-Film Transistors Applied in Dynamic Random Access Memory","authors":"Jie Luo;Yunjiao Bao;Yanyu Yang;Yupeng Lu;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo","doi":"10.1109/TED.2025.3545007","DOIUrl":"https://doi.org/10.1109/TED.2025.3545007","url":null,"abstract":"In recent years, there has been significant interest in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). Multiple investigations have documented the advancement of AOS TFTs, which are utilized in 2T0C dynamic random access memory (DRAM). This work investigates the hysteresis and reliability performance of InGaZnO (IGZO) TFTs and InSnO (ITO) TFTs under different annealing conditions. ITO TFTs have superior electrical performance, with an extremely little hysteresis of practically zero volts and threshold voltage shifts of less than 0.07 V with negative and positive bias stress (PBS) lasting 1000 s. The analysis of hysteresis relies on considering the traps existing at the interface between the gate dielectric and the channel, the interface between the passivation layer and the channel, and electric dipoles. Meanwhile, the good reliability of ITO TFTs is attributed to the simple composition of the ITO channel and the change in valence state of Sn during annealing. The text discusses the illumination of the influence caused by the shifting of threshold voltage in 2T0C DRAM read transistors. ITO read transistors exhibit a retention duration that is more than seven times longer. This finding indicates that the ITO channel is a potential avenue for research within the realm of 2T0C DRAM.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1763-1768"},"PeriodicalIF":2.9,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0