Optimized SOI Stacked Si Nanosheet Gate-All-Around FET With Ni(Pt)Si Silicide-First and Load-Si Thinning Techniques

Abstract

In this article, to optimize the performance of silicon-on-insulator (SOI) stacked Si nanosheet (NS) gate-all-around field-effect transistor (GAAFET) with long source/drain (S/D) regions, special process techniques of Ni(Pt)Si silicide-first and Load-Si thinning are successfully integrated in the experimental devices. Because of the introduced silicide-first process, the transistor performance merits of on-current ( ${I}_{\mathrm {ON}}$ ) and transconductance ( ${G}_{\text {m}}$ ) are also increased by 34.19% and 80.55% for the reduction of 68.66% in the S/D parasitic resistance. Meanwhile, compared to the Bulk-Si GAAFET, the gate-induced drain leakage (GIDL) current of the SOI GAAFET is also decreased by more than one order of magnitude. However, the subthreshold characteristics of SOI GAAFETs exhibit a rapid degradation as the gate length ( ${L}_{\text {g}}$ ) scaling, which is mainly due to the effect of parasitic channel in the remaining Load-Si layer. To optimize the leakage and subthreshold characteristics, the electrical impacts of Load-Si thickness ( ${T}_{\text {Load-Si}}$ ) are thoroughly investigated by the experiment and TCAD simulation. The experimental SOI GAAFET fabricated by thinning Load-Si to 19 nm has obtained better subthreshold characteristics, improved normalized ${I}_{\mathrm {ON}}$ , and caused an obvious decrease of off-current ( ${I}_{\mathrm {OFF}}$ ) at ${L}_{\text {g}} = {30}$ nm. Meanwhile, the simulation results further show that the SOI GAAFET with shorter ${L}_{\text {g}}$ needs to continuously decrease ${T}_{\text {Load-Si}}$ to meet the requirements of a fully depleted channel and low ${I}_{\mathrm {OFF}}$ .