IEEE Transactions on Electron Devices最新文献

{"title":"Transistors Based on Novel 2-D Monolayer Semiconductors Bi₂O₂Se, InSe, and MoSi₂N₄ for Enhanced Logic Density Scaling","authors":"Keshari Nandan;Ateeb Naseer;Amit Agarwal;Somnath Bhowmick;Yogesh S. Chauhan","doi":"10.1109/TED.2024.3509407","DOIUrl":"https://doi.org/10.1109/TED.2024.3509407","url":null,"abstract":"Making ultra-short gate-length transistors significantly contributes to scaling the contacted gate pitch. This, in turn, plays a vital role in achieving smaller standard logic cells for enhanced logic density scaling. As we push the boundaries of miniaturization, it is intriguing to consider that the ultimate limit of contacted gate pitch could be reached with remarkable 1 nm gate-length transistors. Here, we identify InSe, Bi2O2Se, and MoSi2N4 as potential 2-D semiconductors for 1 nm transistors with low contact resistance and outstanding interface properties. We employ a fully self-consistent ballistic quantum transport model starting from first-principle calculations. Our simulations show that the interplay between electrostatics and quantum tunneling influences the performance of these devices over the device design space. MoSi2N4 channels have the best immunity to quantum tunneling, and Bi2O2Se channel devices have the best electrostatics. We show that for a channel length of 12 nm, all the devices can deliver \u0000<inline-formula> <tex-math>${I}_{text {on}}/{I}_{text {off}} gt {10}^{{3}}$ </tex-math></inline-formula>\u0000, suitable for electronic applications, and Bi2O2Se is the best-performing channel material.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"516-521"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Optimization of Burn-In Techniques for Screening Commercial 1.2-kV SiC MOSFETs","authors":"Limeng Shi;Hengyu Yu;Michael Jin;Jiashu Qian;Monikuntala Bhattacharya;Shiva Houshmand;Atsushi Shimbori;Marvin H. White;Anant K. Agarwal","doi":"10.1109/TED.2024.3508674","DOIUrl":"https://doi.org/10.1109/TED.2024.3508674","url":null,"abstract":"The burn-in technique is a well-established screening method designed to eliminate early failures in the gate oxide of silicon carbide (SiC) MOSFETs. Despite its widespread application, optimizing the burn-in technique to improve both efficiency and feasibility remains a significant challenge. This study investigates the performance of commercial 1.2-kV SiC planar MOSFETs following the burn-in process, focusing on parameters, such as threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula>\u0000,\u0000<sc>on</small>\u0000-resistance (\u0000<inline-formula> <tex-math>${R}_{text {on}}text {)}$ </tex-math></inline-formula>\u0000, and subthreshold hysteresis (Hy). The degradation characteristics of SiC MOSFETs during the burn-in and subsequent recovery processes are thoroughly analyzed. The results indicate that aggressive burn-in conditions, such as elevated oxide electric fields or prolonged stress durations, induce defect generation at or near the SiC/SiO2 interface. These new defects and pre-existing defects promote electron trapping, leading to an increase in \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000. Therefore, this study proposes two optimization strategies to refine the burn-in technique while maintaining the intrinsic performance of SiC MOSFETs under demanding conditions. The first approach involves identifying a critical stress duration to minimize defect generation during the burn-in process. The second approach utilizes pulse-mode burn-in technology, incorporating a negative gate bias to reduce the effects of electron trapping.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"331-337"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gate-Controlled MoS₂ Photodiode With Spectral Response From 450 to 1550 nm by Phosphorus-Implantation","authors":"Chao Wang;Xin Hao;Ding Lu;Chao Tan;Guoling Luo;Xiumin Xie;Qingmin Chen;Zungui Ke;Zegao Wang","doi":"10.1109/TED.2024.3508653","DOIUrl":"https://doi.org/10.1109/TED.2024.3508653","url":null,"abstract":"Efficient p-type doping is at the top of the priority list for developing MoS2 electronics and optoelectronics devices due to MoS2 exhibiting the characteristics of an n-type semiconductor. However, implantation, a CMOS-compatible, controllable, and area-selective p-type doping process, is still unclear on MoS2. Here, it is reported that the phosphorus-implantation (P-implantation), a part of the CMOS process, can achieve p-type doping and extend cutoff wavelength from ~980 nm to a value over 1550 nm selectively by modulating implantation dose. By tuning the implantation dose, it was able to transform MoS2 from semiconductor to semimetal. Besides, we fabricate a gate-controlled MoS2 photodiode with spectral response from 450 to 1550 nm by P-implantation. The photodiode has 24 times more responsivity and 500 times the special detectivity than pristine transistor and achieves the responsivity of 6.1 A/W at 1550-nm illumination. In summary, this study opens a guideline for commercialization of MoS2 chips and enriches the application scenarios of MoS2 in NIR photodetection.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"295-300"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Mg-Doped AlGaN Electron Blocking Layer on Micro-LEDs: A Comparative Analysis of Carrier Transport Versus Chip Size and Current Density","authors":"Ying Jiang;Zhuoying Jiang;Mengyue Mo;Kai Huang;Zhaoxia Bi;Cheng Li;Jinchai Li;Junyong Kang;Rong Zhang","doi":"10.1109/TED.2024.3509822","DOIUrl":"https://doi.org/10.1109/TED.2024.3509822","url":null,"abstract":"Micro-light emitting diode (micro-LED) is an essential component for the next-generation self-emissive display. However, existing studies often focus on specific parameters, such as chip size and current density, which restricts the overall understanding of micro-LEDs. This study presents a novel and extensive numerical analysis evaluating the impact of Mg-doped AlGaN electron blocking layers (EBLs) on InGaN-based micro-LED performance, covering current densities from 0.1 to 1000 A/cm2 and mesa sizes from 3 to \u0000<inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>\u0000m for micro-LEDs to \u0000<inline-formula> <tex-math>$gt 200~mu $ </tex-math></inline-formula>\u0000m for conventional LEDs. Unlike prior studies, our work uniquely investigates the interplay between EBL doping concentrations and micro-LED performance across multiple dimensions, providing new insights into carrier injection mechanisms. By varying the EBL doping levels (\u0000<inline-formula> <tex-math>$1times 10^{{19}}$ </tex-math></inline-formula>\u0000 cm−3, \u0000<inline-formula> <tex-math>$3times 10^{{18}}$ </tex-math></inline-formula>\u0000 cm−3, and without EBL), we explored their impact on the band alignment at the last quantum barrier (LQB) and EBL interface, which is crucial for modulating carrier injections and increasing light output power density (LOPD). The results indicate that optimizing EBL properties improves electron blocking at low current densities and enhances hole injection at higher densities, effectively reducing the current leakage and enhancing the luminous efficiency of micro-LEDs across a broad range of current densities. This comprehensive analysis challenges conventional micro-LED design approaches by emphasizing the importance of EBL engineering to achieve balanced and efficient carrier injections under a variety of operating conditions, providing a pathway for future innovations in micro-LED technology.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"306-311"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Study on Short Circuit Characteristics of 4H-SiC MOSFET Coupled With Electron Irradiation","authors":"Yan Chen;Yun Bai;Antao Wang;Leshan Qiu;Jieqin Ding;Yidan Tang;Xiaoli Tian;Jilong Hao;Xuan Li;Xinyu Liu","doi":"10.1109/TED.2024.3508660","DOIUrl":"https://doi.org/10.1109/TED.2024.3508660","url":null,"abstract":"In this article, the electron irradiation coupling short circuit (SC) characteristics of 4H-silicon carbide (SiC) MOSFET are studied. The SC influence mechanism of electron irradiation coupling is proposed, and the influence of minority carrier lifetime on the SC characteristics of the device after irradiation is further studied. The 4H-SiC MOSFET and 4H-SiC wafer are irradiated by 2-MeV electrons. The changes in static parameters of 4H-SiC MOSFET are analyzed, and the SC characteristics of 4H-SiC MOSFET under electron irradiation coupling are studied by the limit SC (LSC) test method. The results show that after irradiation, the SC peak current of 4H-SiC MOSFET increases by 9.6%, the critical SC failure time (\u0000<inline-formula> <tex-math>${t}_{text {crit}}$ </tex-math></inline-formula>\u0000) decreases by 10.85%, and the critical SC failure energy (\u0000<inline-formula> <tex-math>${E}_{text {crit}}$ </tex-math></inline-formula>\u0000) decreases by 5.29%. MOSFET’s LSC failure mechanism after electron irradiation is parasitic BJT conduction. Through TCAD simulation and theoretical derivation, it is proved that the increase of the base current is the main cause of parasitic BJT conduction, and the decrease of carrier lifetime will trigger parasitic BJT conduction earlier. The minority carrier lifetime can be reduced by 97% after electron irradiation. The influence mechanism of electron irradiation on SC characteristics is verified by TCAD simulation. The total ion dose effect will increase the SC peak current, and the displacement effect will significantly reduce the minority carrier lifetime, thus reducing the SC capacity of the device. The simulation results are consistent with the experimental results.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"323-330"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comparative Analysis of Electrical and Optical Thermometry Techniques for AlGaN/GaN HEMTs","authors":"Seokjun Kim;Daniel C. Shoemaker;Anwarul Karim;Husam Walwil;Matthew T. DeJarld;Maher B. Tahhan;Jarrod Vaillancourt;Eduardo M. Chumbes;Jeffrey R. Laroche;Georges Pavlidis;Samuel Graham;Sukwon Choi","doi":"10.1109/TED.2024.3508656","DOIUrl":"https://doi.org/10.1109/TED.2024.3508656","url":null,"abstract":"Gallium nitride (GaN)-based radio frequency (RF) power amplifiers are spearheading the deployment of next-generation wireless systems owing to the large power handling capability at high frequencies and high-power-added efficiency. Unfortunately, this high power density operation leads to severe overheating, which reduces its lifetime and efficiency. Thus, correctly characterizing the temperature rise is of crucial importance to properly design GaN devices and cooling solutions. Optical-based thermometry techniques such as Raman thermometry and infrared (IR) thermography are commonly used to estimate the peak temperature rise, but they are limited by optical access, topside metallization, and depth averaging. Gate resistance thermometry (GRT) offers an alternative method to measure the temperature without needing optical access to the channel. Therefore, in this work, Raman thermometry is used in conjunction with GRT and electrothermal modeling to determine the accuracy of each method for a field-plated GaN high electron mobility transistor (HEMT) under various bias conditions. While both Raman thermometry and GRT measured a similar temperature rise under fully open (FO) channel conditions, it was found that GRT was better at estimating the peak temperature under a partially pinched-off (PPO) bias condition due to the source-connected field plate (SCFP) restricting optical access to the drain side of the gate edge.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"162-168"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of Two Noise Equivalent Circuit Models for GaAs and InP High-Electron-Mobility Transistors","authors":"Ao Zhang;Jianjun Gao","doi":"10.1109/TED.2024.3508670","DOIUrl":"https://doi.org/10.1109/TED.2024.3508670","url":null,"abstract":"This article presented a novel approach for the modeling of noise behavior for GaAs and InP high-electron-mobility transistors (HEMTs). Closed-form expressions for minimum noise figure \u0000<inline-formula> <tex-math>${F}_{min } $ </tex-math></inline-formula>\u0000, noise resistance \u0000<inline-formula> <tex-math>${R}_{n} $ </tex-math></inline-formula>\u0000, optimum source conductance \u0000<inline-formula> <tex-math>${G}_{text {opt}} $ </tex-math></inline-formula>\u0000, and optimum source susceptance \u0000<inline-formula> <tex-math>${B}_{text {opt}} $ </tex-math></inline-formula>\u0000 based on the noise equivalent circuit model are derived. The model is verified by measurements of the four noise parameters of a GaAs HEMT up to 26 GHz and an InP HEMT up to 40 GHz. The W-band low noise amplifier (LNA) is designed to validate the noise model for HEMT.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"154-161"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wide Bandwidth, High Power Radio Frequency Limiter Based on Lanthanum Cobalt Oxide on SiC","authors":"Rajashree Bhattacharya","doi":"10.1109/TED.2024.3506500","DOIUrl":"https://doi.org/10.1109/TED.2024.3506500","url":null,"abstract":"The insulator-to-metal phase transition oxides offer an opportunity to overcome the current constraints in RF limiter technology. In this article, we present shunt power limiters based on sputtered lanthanum cobalt oxide (LaCoO3, LCO) on silicon carbide substrate. The LCO limiters presented in this article achieve limiting behavior over the broadest temperature range ever reported for an insulator to metal transition (IMT) material-based RF switch, from 10 °C to 225 °C. At 2 GHz, the power limiter provides <1-dB insertion loss up to 75 °C, resilience up to 40 dBm, and leakage power of 20 dBm. S-parameter testing was conducted from 0.1 to 50 GHz, verifying the broadband viability of LCO microwave devices. We present low small signal losses at high temperature and frequency, with a maximum insertion loss of 1.15 dB at 125 °C and 50 GHz. Finally, we report on a 3-D multiphysics model that accurately predicts the LCO RF device behavior and can be used for further device optimization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"522-528"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multistates and Ultralow-Power Ferroelectric Tunnel Junction by Inserting Al₂O₃ Interlayer","authors":"Yefan Zhang;Shihao Yu;Peng Yang;Xiaopeng Luo;Hui Xu;Xi Wang;Haijun Liu;Sen Liu;Qingjiang Li","doi":"10.1109/TED.2024.3503533","DOIUrl":"https://doi.org/10.1109/TED.2024.3503533","url":null,"abstract":"In this article, we have designed an optimized ferroelectric tunnel junction (FTJ) device structure that inserts 3-nm Al2O3 between Hf0.5Zr0.5O2 (HZO) films. The Al2O3 interlayer can block the longitudinal growth of HZO grains and increase the number of ferroelectric domains. Therefore, the FTJ devices with Al2O3 interlayer demonstrate amazing multilevel states (256) and ultralow computational power consumption (76.1 pW/bit). In addition, the proposed FTJ device shows high linearity (\u0000<inline-formula> <tex-math>$alpha _{text {p}} = -1.262$ </tex-math></inline-formula>\u0000), wide modulation capability, and good reproducibility. The results indicate that the device has high potential in energy-efficient brain-like computing application.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"228-233"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Laser Micromachining of 2-D Microstrip V-Band Meander-Line Slow Wave Structures","authors":"Dmitrii A. Nozhkin;Andrei V. Starodubov;Roman A. Torgashov;Viktor V. Galushka;Ilya O. Kozhevnikov;Alexey A. Serdobintsev;Alexey D. Lebedev;Anton A. Kozyrev;Nikita M. Ryskin","doi":"10.1109/TED.2024.3507759","DOIUrl":"https://doi.org/10.1109/TED.2024.3507759","url":null,"abstract":"Vacuum electron devices operating at sub-THz frequencies require miniaturized high-frequency electromagnetic interaction structures manufactured using high-precision micromachining technologies. In this article, we present the results of microfabrication of 2-D planar microstrip periodic slow wave structures (SWSs) on dielectric substrate using magnetron sputtering and laser micromachining. A multistage optimized process that allows a substantial improvement of the fabrication accuracy is presented and discussed in detail. A batch of V-band meander-line SWS circuits is fabricated. Characterization of the fabricated structures by optical microscopy and scanning electron microscopy (SEM) demonstrates dimensional deviation less than \u0000<inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>\u0000m. Experimental investigation of cold-test electromagnetic parameters shows good transmission and reflection characteristics.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"453-458"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}