IEEE Transactions on Electron Devices最新文献

{"title":"Performance Enhancement of Solution-Processed p-Type CsPbBr3 TFT by Ultraviolet-Ozone Treatment","authors":"Wenlan Xiao;Yao Dong;Guangtan Miao;Guoxia Liu;Fukai Shan","doi":"10.1109/TED.2024.3466835","DOIUrl":"https://doi.org/10.1109/TED.2024.3466835","url":null,"abstract":"As a pure inorganic perovskite material, CsPbBr3 exhibits the advantages of high optical gain, low nonradiation loss, and ambient preparation. In this work, the p-type CsPbBr3 perovskite thin film was prepared by solution process in the air, and the thin-film transistors (TFTs) based on CsPbBr3 were integrated. The effects of ultraviolet-ozone (UVO) treatment on the electrical and optical properties for the CsPbBr3 TFTs were investigated, and the residual oxygen and carbon-related impurities in CsPbBr3 thin film can be removed after UVO treatment. It is found that the CsPbBr3 TFT treated by UVO for 3 min demonstrates the highest electrical and optical performance, including the on/off current ratio of \u0000<inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula>\u0000, hole mobility of 1.08 cm\u0000<inline-formula> <tex-math>$^{{2}} cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ </tex-math></inline-formula>\u0000, responsivity of 1.2 A/W, specific detectivity of \u0000<inline-formula> <tex-math>$4.52times 10^{{12}}$ </tex-math></inline-formula>\u0000 Jones, and external quantum efficiency (EQE) of 266%. Meanwhile, the TFTs based on CsPbBr3 with UVO treatment exhibit high environmental stability after storage in air for 30 days. The UVO treatment is effective for surface passivation of the CsPbBr3 thin film, and the performance of the TFT can be optimized correspondingly. This work provides a promising approach for the development of all inorganic, low-cost, and high-performance perovskite TFTs and photodetectors in the future.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6764-6768"},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Suppressing the Leakage of GaN HEMTs on Single-Crystalline AlN Templates by Buffer Optimization","authors":"Junbo Wang;Xiangdong Li;Zhibo Cheng;Tao Zhang;Wenyong Zhou;Long Chen;Ye Yuan;Tongxin Lu;Lezhi Wang;Zilan Li;Shuzhen You;Xinqiang Wang;Yue Hao;Jincheng Zhang","doi":"10.1109/TED.2024.3466841","DOIUrl":"https://doi.org/10.1109/TED.2024.3466841","url":null,"abstract":"Single-crystalline AlN templates are a promising substrate choice for GaN power HEMTs, which have, however, seldom been investigated. In this work, high-performance GaN HEMTs on 2-in AlN templates are successfully demonstrated and evaluated. The buffer lateral leakage was significantly suppressed by five orders of magnitude by epitaxially growing an AlN nucleation layer to deactivate the impurities of Si and O, which are introduced at the interface of buffer/AlN template during the secondary epitaxy. An exceptionally high lateral blocking voltage exceeding 10 kV was attained with a spacing of \u0000<inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>\u0000 m. HEMTs without any field plate structure showcase an outstanding breakdown voltage of over 8 kV and an on/off ratio of \u0000<inline-formula> <tex-math>$10^{{9}}$ </tex-math></inline-formula>\u0000. The dynamic \u0000<inline-formula> <tex-math>$R_{text{on}}$ </tex-math></inline-formula>\u0000 degradation is limited to be within 20%, and the threshold voltage \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 exhibits a 10% shift after off-state stress. High-performance GaN HEMTs demonstrated in this work prove that the single-crystalline AlN templates are promising for future high-reliability power HEMTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6609-6615"},"PeriodicalIF":2.9,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstration of Effective Intrinsic Electron Velocity >107 cm/s in Ultrawide Bandgap Al₀.₆₄Ga₀.₃₆N Channel HEMTs","authors":"Parthasarathy Seshadri;Jiahao Chen;Kenneth Stephenson;Md Abdullah Mamun;Ruixin Bai;Zehuan Wang;Shubhra Pasayat;Asif Khan;Chirag Gupta","doi":"10.1109/TED.2024.3464584","DOIUrl":"https://doi.org/10.1109/TED.2024.3464584","url":null,"abstract":"This article reports on the effective intrinsic electron velocity exceeding \u0000<inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>\u0000 cm/s in high-composition Al\u0000<inline-formula> <tex-math>$_{{0.64}}text {Ga}_{{0.36}}$ </tex-math></inline-formula>\u0000N channel high-electron-mobility transistors (HEMTs) at peak \u0000<inline-formula> <tex-math>${f}_{t}$ </tex-math></inline-formula>\u0000. The small-signal two-port s-parameter measurements were employed at peak \u0000<inline-formula> <tex-math>${f}_{t}$ </tex-math></inline-formula>\u0000 bias, which enabled us to compute the small-signal parameters and determine the total transit delay. A device with ~245-nm gate length yielded a total transit delay of 8.04 ps corresponding to a peak \u0000<inline-formula> <tex-math>${f}_{t}$ </tex-math></inline-formula>\u0000 of 19.8 GHz. By segregating the delay components, the intrinsic delay was estimated to be 6.22 ps. However, this intrinsic delay includes the effect of fringe capacitances that were further decoupled to yield the intrinsic transit time. The transit time under the gate was estimated to be 2.12 ps, and thus, the peak effective intrinsic electron velocity was determined to be \u0000<inline-formula> <tex-math>$1.15times 10^{{7}}$ </tex-math></inline-formula>\u0000 cm/s. These findings offer crucial insights for optimizing the design and performance of high-composition AlGaN channel HEMTs at RF power frequencies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6604-6608"},"PeriodicalIF":2.9,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs","authors":"Zhaoxiang Wei;Jiaxing Wei;Hao Fu;Lei Huang;Yu Tian;Junhou Cao;Xudong Zhu;Jiameng Sun;Hao Liu;Qian Wang;Sheng Li;Siyang Liu;Weifeng Sun","doi":"10.1109/TED.2024.3466123","DOIUrl":"https://doi.org/10.1109/TED.2024.3466123","url":null,"abstract":"The split-gate (SG) silicon carbide (SiC) MOSFETs with excellent high-frequency (HF) characteristics have been prepared, but studies on their reliability are scarce. The degradation of the electrical parameters and the corresponding mechanisms for the SG SiC MOSFET under repetitive avalanche stress are investigated and compared with those of the planar-gate (PG) SiC MOSFET. The experiments indicate that even though the static characteristics of both types of devices remain unchanged, the degradation in their capacitances varies. Charge injection into the gate oxide above the JFET region remains the dominant degradation mechanism. Degradation is found to be less serious for an SG device. With the help of 3-D TCAD simulations, the electric field distribution under the avalanche breakdown status is simulated. It is found that for the SG SiC MOSFET, the interfacial electric field is less than 1 MV/cm in the polysilicon-etched region. Combined with the smaller polysilicon-covered area in the JFET region, the increment in the capacitance is reduced after enduring the repetitive avalanche stress. Furtherly, the degradations of the gate charge and the switching characteristics are also suppressed.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6596-6603"},"PeriodicalIF":2.9,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A General Physics Model of Oxygen Vacancy Dynamics for Ferroelectricity Enhancement and Degradation in Hafnia-Based Thin Films","authors":"Shucheng Zhang;Yu Li;Yingfen Wei;Yize Sun;Xumeng Zhang;Hao Jiang;Qi Liu","doi":"10.1109/TED.2024.3465465","DOIUrl":"https://doi.org/10.1109/TED.2024.3465465","url":null,"abstract":"Oxygen vacancy (V\u0000<inline-formula> <tex-math>$_{text {O}}text {)}$ </tex-math></inline-formula>\u0000 defects have been proven to significantly influence polarization switching, particularly in hafnia-based ferroelectric (FE) thin films. In this study, we developed a physical model to delve into a fundamentally deeper understanding of various VO dynamics and their impacts on FE responses in Hf\u0000<inline-formula> <tex-math>$_{{1}-{x}}$ </tex-math></inline-formula>\u0000ZrxO2 (HZO) thin films. Specifically, the dynamic generation, drift, and diffusion of VOs during electric field cycles alter the P-E loop. Hence, the underlying mechanism of the ferroelectricity enhancement during wake-up and subsequent degradation during fatigue can be clarified. During the wake-up, the \u0000<inline-formula> <tex-math>$2{P}_{text {r}}$ </tex-math></inline-formula>\u0000 enhancement by VO generation and pinch opening by VO migration occur simultaneously. The aggregation of high-concentration VOs stops contributing to \u0000<inline-formula> <tex-math>$2{P}_{text {r}}$ </tex-math></inline-formula>\u0000 and degrades the FE properties. The competing effects lead to the transition from a ferroelectrically stable stage to fatigue.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6706-6712"},"PeriodicalIF":2.9,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Suppressed Capacitive Coupling in 2 Transistor Gain Cell With Oxide Channel and Split Gate","authors":"Omkar Phadke;Sharadindu Gopal Kirtania;Dyutimoy Chakraborty;Suman Datta;Shimeng Yu","doi":"10.1109/TED.2024.3463628","DOIUrl":"https://doi.org/10.1109/TED.2024.3463628","url":null,"abstract":"In this article, the impact of capacitive coupling in the oxide-channel-based 2 transistor gain cell (2TGC) is evaluated. The study is performed using an experimentally calibrated TCAD model of W-doped In2O3 transistor (IWO MOSFET) in the mixed mode simulation. A write “0,” read “0,” write “1,” read “1” (W0R0W1R1) operation is performed and the storage node (SN) potential is monitored. The SN is capacitively coupled to write and read wordlines (WWL and RWL), which temporarily lowers the SN potential after writing and during a read operation. For an improperly designed 2TGC, capacitive coupling leads to a disturbed read for bit “0,” and reduced sense margin for bit “1.” To mitigate this problem, \u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000 engineering, appropriate choice of \u0000<inline-formula> <tex-math>${V}_{text {HOLD}}$ </tex-math></inline-formula>\u0000, and sizing of individual transistors is helpful. To substantially suppress the capacitive coupling, a split gate (SpG) structure design for IWO MOSFET is proposed, which allows for a sizing-independent 2TGC design with an undisturbed read and a higher sense margin than the traditional design.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6749-6755"},"PeriodicalIF":2.9,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Source-Drain Series Resistance Model for N-Stack Nanosheet FETs Using Transmission Line Matrix Method","authors":"Sanjay Sharma;Shubham Sahay;Rik Dey","doi":"10.1109/TED.2024.3465452","DOIUrl":"https://doi.org/10.1109/TED.2024.3465452","url":null,"abstract":"The continuous scaling of gate length as well as source and drain (S/D) area increases the parasitic S/D series resistance \u0000<inline-formula> <tex-math>${R}_{text {sd}}$ </tex-math></inline-formula>\u0000 and decreases the channel resistance \u0000<inline-formula> <tex-math>${R}_{text {ch}}$ </tex-math></inline-formula>\u0000. As a result, the contribution of \u0000<inline-formula> <tex-math>$R_{text {sd}}$ </tex-math></inline-formula>\u0000 to the total source-to-drain series resistance \u0000<inline-formula> <tex-math>${R}_{text {tot}}$ </tex-math></inline-formula>\u0000 increases, which decreases the percentage voltage drop across the channel. As a result, the drain drive current degrades at a higher gate bias. The increase in \u0000<inline-formula> <tex-math>${R}_{text {sd}}$ </tex-math></inline-formula>\u0000 increases power dissipation, thermal noise, and delay and reduces the maximum frequency of the device. Therefore, accurate models for \u0000<inline-formula> <tex-math>${R}_{text {sd}}$ </tex-math></inline-formula>\u0000 are needed for optimizing the device geometry to improve its performance and estimate the figure of merits, accurately. The analytical model for \u0000<inline-formula> <tex-math>${R}_{text {sd}}$ </tex-math></inline-formula>\u0000 in nanosheet FET (NSFET) to capture the impact of current distribution in different vertically stacked nanosheet (NS) channels is still elusive in the literature. To this end, we have developed an analytical model for \u0000<inline-formula> <tex-math>${R}_{text {tot}}$ </tex-math></inline-formula>\u0000, which includes both \u0000<inline-formula> <tex-math>${R}_{text {sd}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${R}_{text {ch}}$ </tex-math></inline-formula>\u0000 of the N-stack NSFETs, using the transmission line matrix (TLM) method for the first time. The TLM method effectively captures the effect of current distribution in the S/D region and each of the vertically stacked NS channels in N-stack NSFET. The results obtained from the developed model for \u0000<inline-formula> <tex-math>${R}_{text {tot}}$ </tex-math></inline-formula>\u0000 show good agreement with the simulation results validating the TLM method.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6520-6526"},"PeriodicalIF":2.9,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CuO and MoS₂ Nanocomposite-Based High-Performance Wideband Photodetector","authors":"Tulika Bajpai;Ajay Kumar Dwivedi;Saumya Tripathi;Lucky Agrawal;Shweta Tripathi","doi":"10.1109/TED.2024.3462657","DOIUrl":"https://doi.org/10.1109/TED.2024.3462657","url":null,"abstract":"This article reports an aluminum (Al)/copper oxide (CuO):molybdenum disulfide (MoS2)/indium tin oxide (ITO)-coated polyethylene terephthalate (PET) structure-based broadband photodetector (PD). In the device, CuO:MoS2 nanocomposite prepared through the dispersion method acts as an active layer. The spin coating technique was employed to deposit the nanocomposite film upon ITO-coated PET, followed by the Al contacts deposition by means of a thermal evaporation unit. The fabricated PD shows a broadband response with maximum responsivity \u0000<inline-formula> <tex-math>${R}_{S}{R}_{S}$ </tex-math></inline-formula>\u0000 (A/W) of 1.23, 289.08, and 217.58 A/W at 300 nm (UV), 550 nm (visible), and 850 nm (IR) for −1 V bias at a fixed optical power of \u0000<inline-formula> <tex-math>$0.118~mu $ </tex-math></inline-formula>\u0000W. For optoelectronic applications, the CuO:MoS2 nanocomposite exhibits promising properties.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6799-6803"},"PeriodicalIF":2.9,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermionic Electron Emission Capacity of the Ba₃ScGa₂O₇.₅ Impregnated Cathode","authors":"Chenning Wang;Xiaoyu Zhou;Tianqi Jiang;Zhenrui Xu;Esmond A. Balfour;Hao Fu","doi":"10.1109/TED.2024.3465443","DOIUrl":"https://doi.org/10.1109/TED.2024.3465443","url":null,"abstract":"The high content of Ba and Sc in Ba3ScGa2O7.5 and its suitable melting point suggest that it is a candidate for thermionic emission in vacuum electron devices. To study its electron emission capacity, this compound was synthesized at \u0000<inline-formula> <tex-math>$1300~^{circ }$ </tex-math></inline-formula>\u0000C by a high-temperature solid-phase method with the stoichiometric mole ratio of BaCO3:Sc2O3:Ga2O\u0000<inline-formula> <tex-math>$_{{3}} =6$ </tex-math></inline-formula>\u0000:1:2. The test cathode impregnated with this material had a high emission capacity with the full-space charge current density of 10.2 A/cm2 at \u0000<inline-formula> <tex-math>$850~^{circ }$ </tex-math></inline-formula>\u0000C in the dc mode. The sintered mixture of the compound and tungsten powder reveals that the formation of Ba3Sc2WO9 on the cathode surface leads to reduced work function and thus enhanced emission performance. The titled compound is environmentally stable with a low weight gain percentage (4.51%) and a steady phase in the air for 288 h. Coupled with the high emission current density at low temperatures, the cathode impregnated with Ba3ScGa2O7.5 compound has superior thermionic cathode properties and promising applications in vacuum electron devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7106-7111"},"PeriodicalIF":2.9,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Skipper-in-CMOS: Nondestructive Readout With Subelectron Noise Performance for Pixel Detectors","authors":"Agustin J. Lapi;Miguel Sofo-Haro;Benjamin C. Parpillon;Adi Birman;Guillermo Fernandez-Moroni;Lorenzo Rota;Fabricio Alcalde Bessia;Aseem Gupta;Claudio R. Chavez Blanco;Fernando Chierchie;Julie Segal;Christopher J. Kenney;Angelo Dragone;Shaorui Li;Davide Braga;Amos Fenigstein;Juan Estrada;Farah Fahim","doi":"10.1109/TED.2024.3463631","DOIUrl":"https://doi.org/10.1109/TED.2024.3463631","url":null,"abstract":"The Skipper-in-CMOS image sensor integrates the nondestructive readout capability of skipper charge coupled devices (Skipper-CCDs) with the high conversion gain of a pinned photodiode (PPD) in a CMOS imaging process while taking advantage of in-pixel signal processing. This allows both single photon counting as well as high frame rate readout through highly parallel processing. The first results obtained from a \u0000<inline-formula> <tex-math>${15} times {15}~mu $ </tex-math></inline-formula>\u0000m2 pixel cell of a Skipper-in-CMOS sensor fabricated in Tower Semiconductor’s commercial 180-nm CMOS image sensor process are presented. Measurements confirm the expected reduction of the readout noise with the number of samples down to deep subelectron noise of \u0000<inline-formula> <tex-math>$0.15text {e}^ - $ </tex-math></inline-formula>\u0000, demonstrating the charge transfer operation from the PPD and the single photon counting operation when the sensor is exposed to light. This article also discusses new testing strategies employed for its operation and characterization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6843-6849"},"PeriodicalIF":2.9,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}