IEEE Transactions on Electron Devices最新文献

{"title":"3-D On-Chip Integration of GaN Power Devices on Power Delivery Network (PDN) With Direct Heat Spreading Layer Bonding for Heterogeneous 3-D (H3D) Stacked Systems","authors":"Jaeyong Jeong;Chan Jik Lee;Sung Joon Choi;Nahyun Rheem;Minseo Song;Yoon-Je Suh;Bong Ho Kim;Joon Pyo Kim;Joonsup Shim;Jiseon Lee;Myungsoo Park;Yumin Koh;Donghyun Kim;Sanghyeon Kim","doi":"10.1109/TED.2025.3556044","DOIUrl":"https://doi.org/10.1109/TED.2025.3556044","url":null,"abstract":"Heterogeneous 3-D (H3D) stacked systems offer numerous advantages for high-performance computing (HPC) and artificial intelligence/machine learning (AI/ML) applications. However, implementing H3D systems requires a re-designed power delivery network (PDN) for efficient power delivery in 3-D stacked systems and thermal management solutions. To develop an efficient PDN for the H3D system, a 3-D integrated on-chip power device is recommended. In this work, we demonstrate an H3D-integrated GaN power device on the PDN of a CMOS chip with direct heat-spreading layer bonding. The GaN power devices were designed to integrate both E-mode and D-mode with <inline-formula> <tex-math>${L}_{text {G}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$1.5~mu $ </tex-math></inline-formula> m and <inline-formula> <tex-math>${L}_{text {GD}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$15~mu $ </tex-math></inline-formula> m, and achieve a <inline-formula> <tex-math>${R}_{scriptscriptstyle{mathrm {on}}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$22.3~Omega $ </tex-math></inline-formula> mm and <inline-formula> <tex-math>${V}_{text {BD}}$ </tex-math></inline-formula> of 137 V. These results surpass the limitation of silicon-based power devices. In addition, we experimentally demonstrated that direct heat spreading layer bonding effectively relaxed the thermal effect of H3D-integrated GaN power devices using a thermoreflectance microscopy (TRM) system for the first time. By introducing a heat spreading layer, the thermal resistance (<inline-formula> <tex-math>${R}_{text {TH}}$ </tex-math></inline-formula>) of the GaN power device was reduced by 48.8% compared to GaN power devices without a heat spreading layer. These findings mark a substantial advancement in PDN technology, setting the stage for vertically integrated active PDNs that support efficient power delivery and effective thermal management in H3D stacked systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2654-2661"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Graph Representation Framework for Accelerating Atomic-Level Semiconductor Device Simulation","authors":"Tengfei Wang;Zifeng Wang;Jin He;Hao Wang;Sheng Chang","doi":"10.1109/TED.2025.3556051","DOIUrl":"https://doi.org/10.1109/TED.2025.3556051","url":null,"abstract":"This article proposes a machine-learning (ML) method to accelerate atomic-level device simulation. The main idea is to utilize graph convolutional network (GCN) to predict the potential distribution of the device, aiming to expedite the time-consuming self-consistent calculation process of the transport-Poisson equation within the nonequilibrium Green’s function (NEGF) method. Using the network-predicted electrostatic potential distribution as the initial solution can accelerate the convergence speed of the above process without compromising the accuracy of NEGF calculations. Most importantly, this network introduces a new method for device representation using graphs. It explicitly encodes the coupling effect between the device’s scattering region (SR) and electrodes while effectively capturing quantum mechanical effects at the atomic level. This method offers a more reliable and physically significant approach to device encoding, providing fresh insights on merging ML with atomic-level device simulations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2625-2632"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Si–Ge Axial Heterojunction RFET With Enhanced On-State Current and Low Subthreshold Swing","authors":"Pengjun Wan;Bo Zhang;Yuxin Ran;Siying Zheng;Yi Li;Jiuren Zhou;Jie Liang","doi":"10.1109/TED.2025.3556111","DOIUrl":"https://doi.org/10.1109/TED.2025.3556111","url":null,"abstract":"This article investigates Si and Ge dual-gate reconfigurable field-effect transistors (DG-RFETs) at the nanoscale. It is found that while the Ge DG-RFET improves the <sc>on</small>-state saturated current (<inline-formula> <tex-math>${I}_{text {ON} }$ </tex-math></inline-formula>) of the Si DG-RFET, it also generates bipolar currents at low voltages, which increase as the device size decreases. By analyzing the conduction mechanism of the DG-RFET and examining the source of the bipolar currents in Ge DG-RFETs, we propose a silicon-germanium axial heterojunction RFET (Si-Ge AH-RFET). The conduction mechanism was investigated in detail by Sentaurus TCAD, which revealed a unique double-tunneling mechanism in the P-program. Simulation results show that compared with Si DG-RFETs, <inline-formula> <tex-math>${I}_{text {ON} }$ </tex-math></inline-formula> of the proposed Si-Ge AH-RFET is improved by approximately eight times in the N-program and about 11 times in the P-program and the subthreshold swing (SS) is significantly reduced. Meanwhile, it does not exhibit the same bipolar currents at low voltages as the Ge DG-RFET and maintains the low leakage current (<inline-formula> <tex-math>${I}_{text {OFF} }$ </tex-math></inline-formula>) as the Si DG-RFET. Furthermore, compared with the Si DG-RFET, the transmission delay of the Si-Ge AH-RFET-based inverter is reduced by approximately 75%.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2640-2646"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Characterization of Polarization Switching for Ferroelectric HZO Considering Domain Propagation Effect","authors":"Po-Yi Lee;Kuo-Yu Hsiang;Gui-Huai Chen;Hau-Ting Tsai;Min Hung Lee;Pin Su","doi":"10.1109/TED.2025.3556045","DOIUrl":"https://doi.org/10.1109/TED.2025.3556045","url":null,"abstract":"This work comprehensively models and characterizes the polarization switching of ferroelectric (FE) HZO considering the domain propagation effect. We first present a SPICE framework that can solve the time-dependent Ginzburg-Landau (TDGL) equation, based on which the domain propagation effect through multidomain interaction can be examined. Furthermore, we incorporate the domain propagation effect into an NLS-based model for polycrystalline FE HZO. We have also experimentally characterized the polarization switching of FE HZO from 300 down to 80 K. Our results indicate that the domain propagation effect plays a nonnegligible role for the switching of FE HZO under the temperature of 80 K, and our model is capable of capturing the distinct polarization-switching characteristics due to domain propagation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2341-2346"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Avalanche Multiplication Factor Modeling and Extraction at High Currents in SiGe HBTs","authors":"Huaiyuan Zhang;Guofu Niu;Andries J. Scholten;Marnix B. Willemsen","doi":"10.1109/TED.2025.3558114","DOIUrl":"https://doi.org/10.1109/TED.2025.3558114","url":null,"abstract":"A new compact model and an extraction method for avalanche multiplication factor (<inline-formula> <tex-math>${M}-{1}$ </tex-math></inline-formula>) at high currents are proposed. At a fixed collector-base (CB) voltage (<inline-formula> <tex-math>${V}_{text {CB}}$ </tex-math></inline-formula>), <inline-formula> <tex-math>${M}-{1}$ </tex-math></inline-formula> first decreases with increasing emitter current (<inline-formula> <tex-math>${I}_{E}$ </tex-math></inline-formula>) and then increases at higher currents when the Kirk effect occurs. Different forced-<inline-formula> <tex-math>${I}_{E}~{M}-{1}$ </tex-math></inline-formula> extraction techniques are evaluated, including a new compact modeling-based <inline-formula> <tex-math>${M}-{1}$ </tex-math></inline-formula> extraction technique that accurately captures the Early effect, the Kirk effect, and self-heating. The model is implemented in a development version of MEXTRAM and demonstrated experimentally to model both the current and bias dependence of <inline-formula> <tex-math>${M}-{1}$ </tex-math></inline-formula> and base current (<inline-formula> <tex-math>${I}_{B}$ </tex-math></inline-formula>).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2814-2819"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of Gate Offset on Negative Capacitance Field-Effect Transistors With Self-Heating Effect","authors":"Yangjin Jung;Hyeongu Lee;Mincheol Shin","doi":"10.1109/TED.2025.3558728","DOIUrl":"https://doi.org/10.1109/TED.2025.3558728","url":null,"abstract":"We have investigated the performance of gate-all-around negative-capacitance field effect transistors (GAA-NCFETs) with self-heating effects (SHEs) by self-consistently solving nonequilibrium Green’s function (NEGF), time-dependent Ginzburg-Landau (TDGL) equation, Poisson’s equation, and heat equation. The local hot spot caused by SHE degrades the performance of the ferroelectric material, resulting in a reduction of the <sc>on</small> current (<inline-formula> <tex-math>${I}_{mathrm {scriptstyle {ON}}}$ </tex-math></inline-formula>) by approximately 30%. To mitigate this thermal degradation, a gate offset structure is proposed in this work, which leads to an improvement in the subthreshold swing (SS) and an increase in the <inline-formula> <tex-math>${I}_{mathrm {scriptstyle {ON}}}$ </tex-math></inline-formula>. The gate offset is also effective in reducing the drain-induced barrier rising, but it decreases the cut-off frequency, presenting a trade-off relationship between the figure of merit (FOM).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2789-2794"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Process Gradients and Process Parameter Correlation on Mismatch Modeling for Analog IC Design","authors":"Colin C. McAndrew","doi":"10.1109/TED.2025.3558156","DOIUrl":"https://doi.org/10.1109/TED.2025.3558156","url":null,"abstract":"The effect of across-wafer process gradients on pair mismatch is generally considered to add an additional, normally distributed, stochastic component. We analyze radial process parameter distributions, which, wafer maps show, are predominant and prove that they give rise to a semi-elliptical, not normal, distribution. Additionally, we discuss different approaches to modeling parameter correlations and the geometry dependence of mismatch and present data that show how the correlation in key mismatch parameters has changed over technology generations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2801-2806"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Circular p-GaN/p-AlGaN Rods With Metal/Thin Dielectric-Type p-Contact to Increase the Wall-Plug Efficiency for 258-nm AlGaN-Based Deep Ultraviolet Light Emitting Diodes","authors":"Wenjie Li;Zhaoqiang Liu;Chunshuang Chu;Kangkai Tian;Fuping Huang;Yonghui Zhang;Xiao Wei Sun;Zi-Hui Zhang","doi":"10.1109/TED.2025.3558159","DOIUrl":"https://doi.org/10.1109/TED.2025.3558159","url":null,"abstract":"Very strong optical absorption and the poor hole injection efficiency make AlGaN-based deep-ultraviolet light-emitting diodes (DUV LEDs) encounter low external quantum efficiency (EQE) and poor light output power (LOP). To solve these issues, we design and fabricate circular p-GaN/p-AlGaN rods with a metal/thin dielectric-type p-contact for DUV LEDs. We find that the local removal of the p-GaN layer can significantly increase the light extraction efficiency (LEE). However, direct p-type contact on the exposed p-AlGaN layer causes the increased energy band barrier height. Hence, we utilize metal/thin low-k insulator/semiconductor (MIS)-based p-type contact on the p-AlGaN layer to reduce the energy band barrier height. The results show that the MIS structure effectively facilitates intraband tunneling effect and increase the hole injection efficiency. Therefore, the forward voltage is decreased and the wall-plug efficiency (WPE) gets improved. The proposed MIS-based p-type contact also favors the reduce leakage current before the devices are turned on, which is reflected by the reduced ideality factor. By investigating the rod sizes and the gap between the neighboring rods, we also find that the enhanced WPE shall take the tradeoff between the LEE and the hole injection efficiency into account.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3017-3022"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Frequency Noise Investigation of Organic Field-Effect Transistors Based on N-Type Donor-Acceptor Conjugated Copolymer","authors":"Lijian Chen;Quanhua Chen;Hong Zhu;Walid Boukhili;Binhong Li;Xing Zhao;Chee Leong Tan;Huabin Sun;Stefan Mannsfeld;Yong Xu;Dongyoon Khim","doi":"10.1109/TED.2025.3555262","DOIUrl":"https://doi.org/10.1109/TED.2025.3555262","url":null,"abstract":"Organic field-effect transistors (OFETs) based on n-type donor-acceptor (D-A) conjugated copolymer are at the forefront of research in organic electronics. Yet, an understanding of the fundamental aspects of their charge transport, in particular the relevant traps, remains limited. In this study, we show that the low-frequency noise (LFN) of n-type OFETs based on N2200 exhibits 1/f behavior. The normalized power spectrum density of the drain current (<inline-formula> <tex-math>${I} _{text {D}}$ </tex-math></inline-formula>), namely (<inline-formula> <tex-math>${S} _{text {Id}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I} _{text {D}}^{{2}}$ </tex-math></inline-formula>), varies similarly as (<inline-formula> <tex-math>${g} _{text {m}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I} _{text {D}}$ </tex-math></inline-formula>)2 with gm being the transconductance, indicating the carrier number fluctuations. Examination on the annealing temperature and air stability of the devices with different contacts using LFN reveal sizably varied trap density, conforming the correlation between performance degradation and defect states. Thus, LFN provides quantitative insight into the charge transport behind.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2747-2750"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS","authors":"Shuhan Liu;Robert M. Radway;Xinxin Wang;Filippo Moro;Jean-Francois Nodin;Koustav Jana;Lixian Yan;Shuting Du;Luke R. Upton;Wei-Chen Chen;Jimin Kang;Jian Chen;Haitong Li;Francois Andrieu;Elisa Vianello;Priyanka Raina;Subhasish Mitra;H.-S. Philip Wong","doi":"10.1109/TED.2025.3556113","DOIUrl":"https://doi.org/10.1109/TED.2025.3556113","url":null,"abstract":"The future memory is massive, diverse, and tightly integrated with computing. This research presents tight integration, both physically and architecturally, of two on-chip memory technologies, resistive switching random access memory (RRAM) and gain cell (GC) memory. HfO2 RRAM and indium tin oxide (ITO) GC memory are monolithically integrated on 130-nm Si CMOS technology to form a joint memory that enables low-energy training and low-standby-power inference for edge devices. High-bandwidth on-chip data transfer can have a bandwidth that is <inline-formula> <tex-math>$90times $ </tex-math></inline-formula> state-of-the-art (SoTA) HBM3E and <inline-formula> <tex-math>$211times $ </tex-math></inline-formula> PCIe 7.0, enabled by high-density monolithic 3-D interconnections between memory arrays and high-speed transfer circuit within the integrated joint memory macro. Fabricated atomic layer deposition (ALD) ITO FET exhibits positive <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> of 0.67 V, excellent subthreshold slope (SS) of 65 mV/dec, high <sc>on</small>-current of <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and low <sc>off</small>-current of <inline-formula> <tex-math>$5times 10^{-{18}}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, as extracted from >5000 s retention. The joint memory macro consumes 78% less standby power and 95% less training energy for MobileBERT compared to SRAM with iso-capacity. This RRAM-GC joint memory facilitates efficient continual learning in edge devices, addressing the challenges of a resource-constrained environment while supporting adaptive artificial intelligence (AI) model updates.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2685-2690"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}