IEEE Transactions on Electron Devices最新文献_第6页

Analysis of Breakdown Characteristics of a Pseudospark-Driven Electron Beam Source 伪火花驱动电子束源的击穿特性分析

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3462684

Sahil Jain;Prerna Unadkat;Sushil Shukla;Asish Kumar Singh;Nikita M. Ryskin;Niraj Kumar

{"title":"Analysis of Breakdown Characteristics of a Pseudospark-Driven Electron Beam Source","authors":"Sahil Jain;Prerna Unadkat;Sushil Shukla;Asish Kumar Singh;Nikita M. Ryskin;Niraj Kumar","doi":"10.1109/TED.2024.3462684","DOIUrl":"https://doi.org/10.1109/TED.2024.3462684","url":null,"abstract":"In this article, an experimental investigation has been carried out to analyze the breakdown characteristics of a pseudospark (PS) discharge-driven sheet electron beam source. A single-gap PS-driven sheet beam source has been designed and developed. The developed sheet electron beam source consists of the hollow cathode (HC) and planar anode having a sheet aperture of \u0000<inline-formula> <tex-math>$7times 1$ </tex-math></inline-formula>\u0000 mm with a 3 mm interelectrode gap. The experimental investigation has been carried out at different operating voltages in the range of 10–20 kV and argon gas environment. The electron beam source has been operated in the self-breakdown mode. Experimental characterization has also been performed to study the effect of PS discharge on the back surface of HC. The prebreakdown and after-breakdown conditions of the surface of HC have been evaluated. Different characterization techniques such as scanning electron microscope (SEM) and energy dispersive X-ray analysis (EDAX) elemental analysis have been used to observe the changes in the material composition of HC.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7094-7098"},"PeriodicalIF":2.9,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Testing of Metal Photocathode X-Ray Source Based on Microchannel Plate 基于微通道板的金属光电阴极 X 射线源的设计与测试

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3465463

Hao Yu;Yunpeng Liu;Xiushan Wang;Junxu Mu;Jiaxin Bai;Ao Xia;Kang Wang;Xiaobin Tang

{"title":"Design and Testing of Metal Photocathode X-Ray Source Based on Microchannel Plate","authors":"Hao Yu;Yunpeng Liu;Xiushan Wang;Junxu Mu;Jiaxin Bai;Ao Xia;Kang Wang;Xiaobin Tang","doi":"10.1109/TED.2024.3465463","DOIUrl":"https://doi.org/10.1109/TED.2024.3465463","url":null,"abstract":"This work developed a microchannel plate-based metal photocathode X-ray source (MCP-MPXS). The MCP-MPXS structure was optimized using the non-dominated sorting genetic algorithm (NSGA)-II algorithm. A prototype was then built based on the optimization results, and the current characteristics, X-ray pulse properties, and X-ray imaging performance of the MCP-MPXS were investigated using a dynamic vacuum system. The MCP-MPXS achieved a current gain exceeding \u0000<inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula>\u0000 and had not yet reached its performance limit. With an X-ray pulse modulation frequency (MF) exceeding 10 MHz, the MCP-MPXS outperformed current grid-controlled modulated and most photocathode X-ray sources (PXSs). Modulation rates of several tens of megahertz can be achieved by refining the LED drive circuit. Furthermore, the MCP-MPXS obtained the best focal spot with a focusing ring voltage of 2000 V, which was consistent with the simulation results and verified the effectiveness of the optimization algorithm. The optimal focal spot is \u0000<inline-formula> <tex-math>$0.53times 0.79$ </tex-math></inline-formula>\u0000 mm with an imaging resolution of up to 3.9 lp/mm. The system is also capable of dynamic imaging with X-ray pulse widths as short as \u0000<inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>\u0000s. Results show that the developed MCP-MPXS solves the problem of insufficient output intensity of traditional MPXSs, realizes high-speed X-ray modulation, and is capable of high-resolution X-ray imaging. This X-ray source has broad application prospects in X-ray communication and high-speed X-ray imaging.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7099-7105"},"PeriodicalIF":2.9,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modulating the Cathode by Back-Gate for Planar Nanoscale Vacuum/Air Channel Electron Tube 平面纳米级真空/空气通道电子管的背栅调制阴极

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3462678

Yuelin Wang;Wenjing Ying;Tie Li;Zebo Fang;Qiufeng Ye

{"title":"Modulating the Cathode by Back-Gate for Planar Nanoscale Vacuum/Air Channel Electron Tube","authors":"Yuelin Wang;Wenjing Ying;Tie Li;Zebo Fang;Qiufeng Ye","doi":"10.1109/TED.2024.3462678","DOIUrl":"https://doi.org/10.1109/TED.2024.3462678","url":null,"abstract":"Nanoscale vacuum/air channel electron tubes (VETs) keep emerging owing to their superior performance in high-temperature and high-frequency working environments. However, in VETs the edge field of the gate with inferior modulation efficiency, nonnegligible leakage or accumulation, and poor compatibility with integrated circuits (ICs) technology limits the realization of VET IC. In this work, an original cathode-modulated VET (CMVET) is proposed, which can efficiently control the field emission current of the cathode by directly regulating the electron density of the cathode by back-gate, resulting in regulating the anode current. As a result, we obtain a transconductance of \u0000<inline-formula> <tex-math>$4.6 ; mu $ </tex-math></inline-formula>\u0000S and a suppressed gate leakage current of no more than \u0000<inline-formula> <tex-math>$10^{-{11}}$ </tex-math></inline-formula>\u0000 A for the CMVET device, which is completely fabricated by traditional microelectronic process, being compatible with IC processes. On the basis of this strategy, it is promising to realize the CMVET IC with great resistance to high frequency, high temperature, and high radiation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7082-7086"},"PeriodicalIF":2.9,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sub-60 mV/Decade Dynamic Subthreshold Swing in Bulk Negative Capacitance Junctionless MOSFET 块状负电容无结 MOSFET 中低于 60 mV/Decade 的动态次阈值波动

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3462373

Ruma S. R.;Manish Gupta

{"title":"Sub-60 mV/Decade Dynamic Subthreshold Swing in Bulk Negative Capacitance Junctionless MOSFET","authors":"Ruma S. R.;Manish Gupta","doi":"10.1109/TED.2024.3462373","DOIUrl":"https://doi.org/10.1109/TED.2024.3462373","url":null,"abstract":"Through well-calibrated simulations, this work provides physical insights into the occurrence of dynamic sub-60 mV/decade switching in a negative capacitance (NC) junctionless (JL) transistor designed on a bulk substrate. Recognizing that the location of the conduction channel is a key factor governing the matching between ferroelectric and gate capacitances, we showcase the outperformance of bulk NCJL transistors compared to NCJL devices designed on a silicon-on-insulator (SOI) substrate. Results highlight that NCJL transistors designed with relatively higher bulk doping can achieve better dynamic \u0000<inline-formula> <tex-math>${S}_{text {swing}}$ </tex-math></inline-formula>\u0000 along with a higheron-to-off current ratio. We also investigate the short-channel performance comparison of bulk and SOI NCJL transistors. The results demonstrate the superiority of bulk NCJL transistors due to the enhanced NC effect resulting from the better ferroelectric and gate capacitances matching. The work provides a new viewpoint for designing of NCJL transistor on bulk substrate to facilitate steep \u0000<inline-formula> <tex-math>${S}_{text {swing}}$ </tex-math></inline-formula>\u0000 at scaled gate lengths.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7156-7161"},"PeriodicalIF":2.9,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142524134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Giant Tunneling Electroresistance in 2-D In-Plane Ferroelectric Tunnel Junctions Based on a α -In₂Se₃/Cd₃C₂ Heterostructure 基于 α -In₂Se₃/Cd₃C₂ 异质结构的二维平面内铁电隧道结中的巨隧道电阻

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3462378

Ziqi Han;Xiaohong Zheng;Chun-Sheng Liu;Lei Zhang;Weiyang Wang;Zhi Zeng

{"title":"Giant Tunneling Electroresistance in 2-D In-Plane Ferroelectric Tunnel Junctions Based on a α -In₂Se₃/Cd₃C₂ Heterostructure","authors":"Ziqi Han;Xiaohong Zheng;Chun-Sheng Liu;Lei Zhang;Weiyang Wang;Zhi Zeng","doi":"10.1109/TED.2024.3462378","DOIUrl":"https://doi.org/10.1109/TED.2024.3462378","url":null,"abstract":"Ferroelectric tunnel junctions (FTJs), composed of two metallic or semiconductor leads separated by a thin ferroelectric tunnel barrier, demonstrate significant potential for nonvolatile memory devices. With the development of device miniaturization, 2-D FTJs have attracted increasing attention due to the unique characteristics of material stability, atomic thickness, and high tunnel electroresistance (TER) ratio. In this work, a 2-D in-plane van der Waals (vdW) FTJ constructed using a In2Se3/Cd3C2 heterostructure is designed, and its electron transport properties have been investigated based on density functional calculations combined with a nonequilibrium Green’s function (NEGF) technique. The results demonstrate that a TER ratio of 106% is achieved due to the change from Schottky- to Ohmic-type contact at the In2Se3/Cd3C2 interface accompanied by ferroelectric polarization reversal. Meanwhile, the current-voltage (I–V) characteristics at low bias voltages indicate significant amplitude differences between currents under different polarization states. The TER can be stably maintained above 106%, indicating two ideal states “0” and “1” for data storage. The mechanism for the Schottky to Ohmic switching is explained by different charge transfers between the contacted surfaces of the two materials under different polarization directions, which are further controlled by the work functions of them. Consequently, work function engineering offers a promising method for constructing 2-D ferroelectric vdW heterostructures and FTJs, which has promising application potential in nanoscale high-density ferroelectric memory devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7169-7176"},"PeriodicalIF":2.9,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Space Mapping Augmented Compact Model for Uncertainty Quantification of GaN HEMT Devices and Circuits in the Presence of Trap Effects 用于陷阱效应下 GaN HEMT 器件和电路不确定性量化的空间映射增强紧凑模型

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3462888

Mohd. Yusuf;Smriti Singh;Avirup Dasgupta;Biplab Sarkar;Sourajeet Roy

引用次数: 0

A Single MEMS Sensor Based on SnO₂ Nanosheets for Selective Gas Identification 基于 SnO₂ 纳米片的单一 MEMS 传感器用于选择性气体识别

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-10-01 DOI: 10.1109/TED.2024.3464573

Wenxin Luo;Jianhao Li;Mingjie Li

引用次数: 0

Nano-Meter Resolution Line-Offset Detector Arrays (LODAs) for Pattern Monitoring in EUV Lithography System 用于监测 EUV 光刻系统图案的纳米级分辨率线偏移探测器阵列 (LODAs)

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-09-30 DOI: 10.1109/TED.2024.3462670

Wei Chang;Burn Jeng Lin;Pin-Jiun Wu;Jiaw-Ren Shih;Yue-Der Chih;Jonathan Chang;Chrong Jung Lin;Ya-Chin King

引用次数: 0

Bias and Temperature Stress Effects in IGZO TFTs and the Application of Step-Stress Testing to Increase Reliability Test Throughput IGZO TFT 的偏压和温度应力效应以及应用阶跃应力测试提高可靠性测试吞吐量

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-09-30 DOI: 10.1109/TED.2024.3462693

Navid Mohammadian;Dinesh Kumar;Lucas Fugikawa-Santos;Gabriel Leonardo Nogueira;Shouzhou Zhang;Neri Alves;David Ballantine;Jeff Kettle

{"title":"Bias and Temperature Stress Effects in IGZO TFTs and the Application of Step-Stress Testing to Increase Reliability Test Throughput","authors":"Navid Mohammadian;Dinesh Kumar;Lucas Fugikawa-Santos;Gabriel Leonardo Nogueira;Shouzhou Zhang;Neri Alves;David Ballantine;Jeff Kettle","doi":"10.1109/TED.2024.3462693","DOIUrl":"https://doi.org/10.1109/TED.2024.3462693","url":null,"abstract":"Indium-gallium–zinc-oxide thin-film transistors (IGZO TFTs) are widely used in numerous applications including displays and are emerging as a promising alternative for flexible IC production due to their high transparency, superior field-effect mobility, and low-temperature processability. However, their stability under different voltage stresses remains a concern, primarily due to carrier trapping in the gate dielectric and point defect creation. This study involves the fabrication of IGZO TFTs and their subsequent bias stress testing in linear and saturation regions. The impact of a passivation layer on top of the active channel is investigated to mitigate bias stress susceptibility. The passivated thin-film transistors (TFTs) exhibit reduced bias stress susceptance, with \u0000<inline-formula> <tex-math>$Delta {V}_{T}$ </tex-math></inline-formula>\u0000 only moderately affected by the positive gate-bias stress (PGBS). This suggests that fewer electrons are being trapped at the interface between the dielectric/semiconductor. Conventional bias stress testing methods for TFTs are time-consuming and depend on air-stable devices. To address this, we introduce a “voltage step-stress” (VSS) approach. This method offers an accelerated way to conduct bias stress measurements without compromising test accuracy, reducing testing time by 8 hours (a 45% relative reduction).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6756-6763"},"PeriodicalIF":2.9,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evaluation Methods for ReRAM Potentiation on Sub-Nanosecond Timescales 亚纳秒时间尺度 ReRAM 潜能的评估方法

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2024-09-30 DOI: 10.1109/TED.2024.3461676

Faisal Munir;Daniel Schön;Stephan Menzel;Pascal Stasner;Rainer Waser;Stefan Wiefels

{"title":"Evaluation Methods for ReRAM Potentiation on Sub-Nanosecond Timescales","authors":"Faisal Munir;Daniel Schön;Stephan Menzel;Pascal Stasner;Rainer Waser;Stefan Wiefels","doi":"10.1109/TED.2024.3461676","DOIUrl":"https://doi.org/10.1109/TED.2024.3461676","url":null,"abstract":"Neuromorphic computing, inspired by the processing capabilities of the brain, aims to overcome the limitations of conventional computing architectures. Valence change memory (VCM), along with other emerging redox-based resistive random-access memory (ReRAM) devices, is a promising candidate for this endeavor due to its features, including fast write times. Moreover, VCM devices are also suitable for neuromorphic applications, such as long-term potentiation (LTP), short-term plasticity (STP), and gradual switching. However, the evaluation of these schemes on sub-100ps timescales presents significant challenges, as the capacitive current dominates the device current, obscuring the true conductance state. Therefore, robust methods are required to analyze the current response of ReRAM cells to ultrashort pulses and varying delays, which is critical for advanced neuromorphic applications. To address the challenge of dominating capacitive current, this study proposes two methods: the integration method and the reference method. The integration method integrates the current and eliminates capacitive charges across a full charge/discharge cycle, proving to be more reliable for longer pulses and delays exceeding 200ps. On the other hand, the reference method determines the device current by subtracting the capacitive current from the measured current, using a reference measurement. This method is particularly adept at analyzing shorter pulses and delays below 200ps. These methods provide effective solutions to the challenge of capacitive current dominance to ultrashort pulses and varying delays.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6691-6697"},"PeriodicalIF":2.9,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10697966","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0