Haimeng Huang;Xiao Wang;Haoyue Zhang;Zhentao Xiao;Juncheng Xiong;Hongqiang Yang
{"title":"考虑温度依赖性的绝缘柱超结比导通电阻优化","authors":"Haimeng Huang;Xiao Wang;Haoyue Zhang;Zhentao Xiao;Juncheng Xiong;Hongqiang Yang","doi":"10.1109/TED.2025.3588149","DOIUrl":null,"url":null,"abstract":"Unified temperature-dependent models are developed to optimize <inline-formula> <tex-math>${R} {_{\\text {sp}}}$ </tex-math></inline-formula> for the insulating pillar superjunction (IP-SJ) MOSFETs. The insulating pillar (i-pillar) could be intrinsic silicon in the compensated pillar SJ (CP-SJ) structure, oxide in the oxide pillar SJ (OP-SJ) structure, or even air in the air pillar SJ (AP-SJ) structure. These three typical structures are investigated and compared. Extensive investigations reveal that CP-SJ exhibits no improvement <inline-formula> <tex-math>${R} {_{\\text {sp}}}$ </tex-math></inline-formula> compared with the conventional SJ (C-SJ) structure. The AP-SJ (with the lowest relative dielectric constant of unity) possesses the best <inline-formula> <tex-math>${R} {_{\\text {sp}}}$ </tex-math></inline-formula>, especially with high BV and narrow half cell width b, and large drain-to-source voltage (<inline-formula> <tex-math>${V} {_{\\text {DS}}}$ </tex-math></inline-formula>), due to better suppression of JFET effect. For BV <inline-formula> <tex-math>${=}1250$ </tex-math></inline-formula> V and <inline-formula> <tex-math>${b}{=}0.6~{\\mu }$ </tex-math></inline-formula>m, theoretical optimization predicts a largest reduction up to 20.5% in <inline-formula> <tex-math>${R} {_{\\text {sp}}}$ </tex-math></inline-formula> with <inline-formula> <tex-math>${V} {_{\\text {DS}} =}5$ </tex-math></inline-formula> V for the AP-SJ at room temperature. The effects of temperature (T) on the optimization results and the temperature-dependent application are also investigated.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5097-5103"},"PeriodicalIF":3.2000,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimization of Specific On-Resistance for Superjunction With Insulating Pillar Including Temperature Dependence\",\"authors\":\"Haimeng Huang;Xiao Wang;Haoyue Zhang;Zhentao Xiao;Juncheng Xiong;Hongqiang Yang\",\"doi\":\"10.1109/TED.2025.3588149\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Unified temperature-dependent models are developed to optimize <inline-formula> <tex-math>${R} {_{\\\\text {sp}}}$ </tex-math></inline-formula> for the insulating pillar superjunction (IP-SJ) MOSFETs. The insulating pillar (i-pillar) could be intrinsic silicon in the compensated pillar SJ (CP-SJ) structure, oxide in the oxide pillar SJ (OP-SJ) structure, or even air in the air pillar SJ (AP-SJ) structure. These three typical structures are investigated and compared. Extensive investigations reveal that CP-SJ exhibits no improvement <inline-formula> <tex-math>${R} {_{\\\\text {sp}}}$ </tex-math></inline-formula> compared with the conventional SJ (C-SJ) structure. The AP-SJ (with the lowest relative dielectric constant of unity) possesses the best <inline-formula> <tex-math>${R} {_{\\\\text {sp}}}$ </tex-math></inline-formula>, especially with high BV and narrow half cell width b, and large drain-to-source voltage (<inline-formula> <tex-math>${V} {_{\\\\text {DS}}}$ </tex-math></inline-formula>), due to better suppression of JFET effect. For BV <inline-formula> <tex-math>${=}1250$ </tex-math></inline-formula> V and <inline-formula> <tex-math>${b}{=}0.6~{\\\\mu }$ </tex-math></inline-formula>m, theoretical optimization predicts a largest reduction up to 20.5% in <inline-formula> <tex-math>${R} {_{\\\\text {sp}}}$ </tex-math></inline-formula> with <inline-formula> <tex-math>${V} {_{\\\\text {DS}} =}5$ </tex-math></inline-formula> V for the AP-SJ at room temperature. The effects of temperature (T) on the optimization results and the temperature-dependent application are also investigated.\",\"PeriodicalId\":13092,\"journal\":{\"name\":\"IEEE Transactions on Electron Devices\",\"volume\":\"72 9\",\"pages\":\"5097-5103\"},\"PeriodicalIF\":3.2000,\"publicationDate\":\"2025-07-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Electron Devices\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11099093/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11099093/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Optimization of Specific On-Resistance for Superjunction With Insulating Pillar Including Temperature Dependence
Unified temperature-dependent models are developed to optimize ${R} {_{\text {sp}}}$ for the insulating pillar superjunction (IP-SJ) MOSFETs. The insulating pillar (i-pillar) could be intrinsic silicon in the compensated pillar SJ (CP-SJ) structure, oxide in the oxide pillar SJ (OP-SJ) structure, or even air in the air pillar SJ (AP-SJ) structure. These three typical structures are investigated and compared. Extensive investigations reveal that CP-SJ exhibits no improvement ${R} {_{\text {sp}}}$ compared with the conventional SJ (C-SJ) structure. The AP-SJ (with the lowest relative dielectric constant of unity) possesses the best ${R} {_{\text {sp}}}$ , especially with high BV and narrow half cell width b, and large drain-to-source voltage (${V} {_{\text {DS}}}$ ), due to better suppression of JFET effect. For BV ${=}1250$ V and ${b}{=}0.6~{\mu }$ m, theoretical optimization predicts a largest reduction up to 20.5% in ${R} {_{\text {sp}}}$ with ${V} {_{\text {DS}} =}5$ V for the AP-SJ at room temperature. The effects of temperature (T) on the optimization results and the temperature-dependent application are also investigated.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.