High-Resistivity Substrates in 22-nm FD-SOI—Part I: Wideband Modeling and Impact on RF Losses

This article examines how the bulk and interface resistivity of silicon substrates influence the RF performance of devices fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. To investigate this, coplanar waveguides (CPWs) were designed and manufactured using GlobalFoundries’ 22FDX (Registered trademark) process on a range of substrates, from standard 10- $\Omega $ cm silicon wafers to high-resistivity (HR) 620- $\Omega $ cm wafers. In addition, various silicon-interface conditions were explored, introducing process variations in interface resistivity alongside changes in bulk resistivity. To achieve high interfacial resistivity, a series of p-n junctions were implemented at the interface, and these are proven to drastically reduce RF losses. From the CPW line measurement data, interface and bulk resistivity values were extracted for all six considered substrate variations. The extraction of these properties enables modeling of the materials present in all substrate stacks and permits electromagnetic (EM) simulations of various RF layouts of various shapes, functions and characteristic dimensions, such as spiral inductors and mm-wave single-pole double-throw (SPDT) switches. Such simulations are shown to correlate well to the measured data using the calibrated material stack description. This work demonstrates the impact of the substrate’s bulk and interface properties on the losses and quality of these devices and highlights the necessity for an effective interface passivation technique and appropriate modeling.