High-Resistivity Substrates in 22-nm FD-SOI—Part II: Impact on mm-Wave SPDT Performance

Abstract

This article delves into the detailed design and performance analysis of a mm-wave single-pole double-throw (SPDT) switch, fabricated in the GlobalFoundries 22-nm fully depleted silicon-on-insulator (FD-SOI) process on several types on silicon wafer, from standard-resistivity $10~\Omega \cdot $ cm ones to high-resistivity 620- $\Omega \cdot $ cm variants. Building upon the foundational results presented in Part I, this work investigates the specific impedance paths and parasitic effects introduced by the substrate in a full SPDT switch layout and highlights the radio frequency (RF) performance gains that are achievable by employing silicon substrates that have simultaneously high interface and bulk resistivity values. A detailed extraction of equivalent impedance paths is performed to quantify the contributions of both the bulk and interface resistivity, with a particular emphasis on the regions of the layout where these parasitics have the most significant effect on insertion loss (IL) and signal integrity. Electromagnetic (EM) simulations are used to model the switch layout with accuracy, enabling a thorough analysis of the coupling mechanisms. The impact of the optimized high-resistivity (HR) substrate and interface passivation techniques is explored further, showing their critical role in mitigating parasitic losses at mm-wave frequencies. This work provides valuable insights into substrate-induced performance degradation in high-frequency circuit modules and presents a comprehensive modeling approach to predict and mitigate these effects.