Characterization Methods of TMD Transistor Gate Dielectrics Targeting 1 nm EOT for 2-D CMOS Scaling

Abstract

2-D materials show promise to possibly replace Si channel material to continue Moore’s Law scaling of transistors down to 5 nm gate lengths. The scaling opportunities of 2-D materials arise due to their ultra-thin monolayer thickness of sub-1 nm, which allows for strong electrostatic gate control while maintaining high mobility with virtually no surface roughness scattering from the intrinsically passivated van der Waals (vdW) surfaces. The scaling benefits of 2-D materials, however, can only be realized with the development of a highly scaled, low-defect gate oxide growth method compatible with vdW surfaces. This has thus far proven to be challenging as the vdW surfaces lack the dangling bonds required for standard ALD oxide growth nucleation. Furthermore, gate oxide films grown on vdW surfaces are rarely characterized following industry standard capacitance–voltage (CV) methods, primarily due to high leakage or resistance often present in today’s 2-D transistors, rendering CV measurements very difficult. While 2-D MOSFET gate leakage and contact resistances are improving rapidly, researchers still resort to inferring equivalent oxide thickness (EOT) from I–V characterization rather than standard CV. In this work, we show through both technology computer aided design (TCAD) simulations and experiments that I–V based methods of 2-D MOSFET EOT measurements have several pitfalls which may lead to inaccurate conclusions. We provide techniques to improve accuracy for both I–V and CV-based gate oxide characterization, which will help accelerate the field of 2-D transistor development closer toward a feasible CMOS technology.