{"title":"Effects of Gate Offset on Negative Capacitance Field-Effect Transistors With Self-Heating Effect","authors":"Yangjin Jung;Hyeongu Lee;Mincheol Shin","doi":"10.1109/TED.2025.3558728","DOIUrl":"https://doi.org/10.1109/TED.2025.3558728","url":null,"abstract":"We have investigated the performance of gate-all-around negative-capacitance field effect transistors (GAA-NCFETs) with self-heating effects (SHEs) by self-consistently solving nonequilibrium Green’s function (NEGF), time-dependent Ginzburg-Landau (TDGL) equation, Poisson’s equation, and heat equation. The local hot spot caused by SHE degrades the performance of the ferroelectric material, resulting in a reduction of the <sc>on</small> current (<inline-formula> <tex-math>${I}_{mathrm {scriptstyle {ON}}}$ </tex-math></inline-formula>) by approximately 30%. To mitigate this thermal degradation, a gate offset structure is proposed in this work, which leads to an improvement in the subthreshold swing (SS) and an increase in the <inline-formula> <tex-math>${I}_{mathrm {scriptstyle {ON}}}$ </tex-math></inline-formula>. The gate offset is also effective in reducing the drain-induced barrier rising, but it decreases the cut-off frequency, presenting a trade-off relationship between the figure of merit (FOM).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2789-2794"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effect of Process Gradients and Process Parameter Correlation on Mismatch Modeling for Analog IC Design","authors":"Colin C. McAndrew","doi":"10.1109/TED.2025.3558156","DOIUrl":"https://doi.org/10.1109/TED.2025.3558156","url":null,"abstract":"The effect of across-wafer process gradients on pair mismatch is generally considered to add an additional, normally distributed, stochastic component. We analyze radial process parameter distributions, which, wafer maps show, are predominant and prove that they give rise to a semi-elliptical, not normal, distribution. Additionally, we discuss different approaches to modeling parameter correlations and the geometry dependence of mismatch and present data that show how the correlation in key mismatch parameters has changed over technology generations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2801-2806"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Circular p-GaN/p-AlGaN Rods With Metal/Thin Dielectric-Type p-Contact to Increase the Wall-Plug Efficiency for 258-nm AlGaN-Based Deep Ultraviolet Light Emitting Diodes","authors":"Wenjie Li;Zhaoqiang Liu;Chunshuang Chu;Kangkai Tian;Fuping Huang;Yonghui Zhang;Xiao Wei Sun;Zi-Hui Zhang","doi":"10.1109/TED.2025.3558159","DOIUrl":"https://doi.org/10.1109/TED.2025.3558159","url":null,"abstract":"Very strong optical absorption and the poor hole injection efficiency make AlGaN-based deep-ultraviolet light-emitting diodes (DUV LEDs) encounter low external quantum efficiency (EQE) and poor light output power (LOP). To solve these issues, we design and fabricate circular p-GaN/p-AlGaN rods with a metal/thin dielectric-type p-contact for DUV LEDs. We find that the local removal of the p-GaN layer can significantly increase the light extraction efficiency (LEE). However, direct p-type contact on the exposed p-AlGaN layer causes the increased energy band barrier height. Hence, we utilize metal/thin low-k insulator/semiconductor (MIS)-based p-type contact on the p-AlGaN layer to reduce the energy band barrier height. The results show that the MIS structure effectively facilitates intraband tunneling effect and increase the hole injection efficiency. Therefore, the forward voltage is decreased and the wall-plug efficiency (WPE) gets improved. The proposed MIS-based p-type contact also favors the reduce leakage current before the devices are turned on, which is reflected by the reduced ideality factor. By investigating the rod sizes and the gap between the neighboring rods, we also find that the enhanced WPE shall take the tradeoff between the LEE and the hole injection efficiency into account.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3017-3022"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-Frequency Noise Investigation of Organic Field-Effect Transistors Based on N-Type Donor-Acceptor Conjugated Copolymer","authors":"Lijian Chen;Quanhua Chen;Hong Zhu;Walid Boukhili;Binhong Li;Xing Zhao;Chee Leong Tan;Huabin Sun;Stefan Mannsfeld;Yong Xu;Dongyoon Khim","doi":"10.1109/TED.2025.3555262","DOIUrl":"https://doi.org/10.1109/TED.2025.3555262","url":null,"abstract":"Organic field-effect transistors (OFETs) based on n-type donor-acceptor (D-A) conjugated copolymer are at the forefront of research in organic electronics. Yet, an understanding of the fundamental aspects of their charge transport, in particular the relevant traps, remains limited. In this study, we show that the low-frequency noise (LFN) of n-type OFETs based on N2200 exhibits 1/f behavior. The normalized power spectrum density of the drain current (<inline-formula> <tex-math>${I} _{text {D}}$ </tex-math></inline-formula>), namely (<inline-formula> <tex-math>${S} _{text {Id}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I} _{text {D}}^{{2}}$ </tex-math></inline-formula>), varies similarly as (<inline-formula> <tex-math>${g} _{text {m}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I} _{text {D}}$ </tex-math></inline-formula>)2 with gm being the transconductance, indicating the carrier number fluctuations. Examination on the annealing temperature and air stability of the devices with different contacts using LFN reveal sizably varied trap density, conforming the correlation between performance degradation and defect states. Thus, LFN provides quantitative insight into the charge transport behind.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2747-2750"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shuhan Liu;Robert M. Radway;Xinxin Wang;Filippo Moro;Jean-Francois Nodin;Koustav Jana;Lixian Yan;Shuting Du;Luke R. Upton;Wei-Chen Chen;Jimin Kang;Jian Chen;Haitong Li;Francois Andrieu;Elisa Vianello;Priyanka Raina;Subhasish Mitra;H.-S. Philip Wong
{"title":"Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS","authors":"Shuhan Liu;Robert M. Radway;Xinxin Wang;Filippo Moro;Jean-Francois Nodin;Koustav Jana;Lixian Yan;Shuting Du;Luke R. Upton;Wei-Chen Chen;Jimin Kang;Jian Chen;Haitong Li;Francois Andrieu;Elisa Vianello;Priyanka Raina;Subhasish Mitra;H.-S. Philip Wong","doi":"10.1109/TED.2025.3556113","DOIUrl":"https://doi.org/10.1109/TED.2025.3556113","url":null,"abstract":"The future memory is massive, diverse, and tightly integrated with computing. This research presents tight integration, both physically and architecturally, of two on-chip memory technologies, resistive switching random access memory (RRAM) and gain cell (GC) memory. HfO2 RRAM and indium tin oxide (ITO) GC memory are monolithically integrated on 130-nm Si CMOS technology to form a joint memory that enables low-energy training and low-standby-power inference for edge devices. High-bandwidth on-chip data transfer can have a bandwidth that is <inline-formula> <tex-math>$90times $ </tex-math></inline-formula> state-of-the-art (SoTA) HBM3E and <inline-formula> <tex-math>$211times $ </tex-math></inline-formula> PCIe 7.0, enabled by high-density monolithic 3-D interconnections between memory arrays and high-speed transfer circuit within the integrated joint memory macro. Fabricated atomic layer deposition (ALD) ITO FET exhibits positive <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> of 0.67 V, excellent subthreshold slope (SS) of 65 mV/dec, high <sc>on</small>-current of <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and low <sc>off</small>-current of <inline-formula> <tex-math>$5times 10^{-{18}}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, as extracted from >5000 s retention. The joint memory macro consumes 78% less standby power and 95% less training energy for MobileBERT compared to SRAM with iso-capacity. This RRAM-GC joint memory facilitates efficient continual learning in edge devices, addressing the challenges of a resource-constrained environment while supporting adaptive artificial intelligence (AI) model updates.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2685-2690"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Layout Optimization of Dual-Directional SCR for Holding Voltage Equilibrium in ESD Applications","authors":"Feibo Du;Ruibo Chen;Yi Liu;Fei Hou;Xiaoyu Dong;Dongxing Gao;Jiaqiang Zheng;Zihan Zheng;Yimu Yang;Xuyao Wang;Zhiwei Liu","doi":"10.1109/TED.2025.3558487","DOIUrl":"https://doi.org/10.1109/TED.2025.3558487","url":null,"abstract":"The reverse holding voltage of high-voltage (HV) dual-directional silicon-controlled rectifier (DDSCR) is usually degraded to a very low level due to the ubiquitous substrate guard ring. In this article, two symmetrical dual-finger layout configurations of DDSCR (DDSCR-DF1 and DDSCR-DF2) are proposed to restrain the degradation of negative holding voltage. By suppressing the parasitic current paths associated with the p-type guard ring (PGR) in all directions, experimental results indicate that the DDSCR-DF2 can effectively shield the substrate parasitic effects, thereby restoring the high holding voltage characteristic inherent in DDSCR kernel. Moreover, the dual-finger layout configuration presented here can be extended to various existing HV DDSCRs, thus providing a very useful layout optimization method for HV Electrostatic discharge (ESD) engineering.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2783-2788"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2-D Hydrodynamic Simulation of TeraFETs Beyond the Gradual-Channel Approximation for Transient, Large-Signal, or Ultrahigh-Frequency Simulations","authors":"Florian Ludwig;Hartmut G. Roskos;Raul Borsche","doi":"10.1109/TED.2025.3558157","DOIUrl":"https://doi.org/10.1109/TED.2025.3558157","url":null,"abstract":"In the past decade, detection of THz radiation by plasma-wave-assisted mixing in antenna-coupled field-effect transistors (TeraFETs)—implemented in various semiconductor material systems (Si CMOS, GaN/AlGaN, GaAs/AlGaAs, and graphene)—has matured and led to a practically applied detector technology. This has been supported by the development of powerful device simulation tools which take into account relevant collective carrier dynamics and mixing processes in various approximations. These tools mostly model carrier transport in one-dimension (1-D) and they are usually geared toward continuous-wave illumination of the device and small-signal response. Depending on their implementation, it may not be possible readily to simulate large-signal and pulsed operation. Another approximation which may lead to unsatisfactory results is the 1-D restriction to calculate only the longitudinal electric field components. Especially at the edges of the gate electrode, solving of the 2-D Poisson equation promises better results. This contribution introduces a stable way to solve the 2-D Poisson equation self-consistently with the hydrodynamic transport equations including the numerically challenging convection term. We employ a well-balanced approximate Harten-Lax-van-Leer-Contact (HLLC) Riemann solver. The approach is well suited for the future treatment of transient and large-signal cases. The 2-D treatment also generically extends the model beyond the gradual-channel approximation and allows to calculate the FET’s response at high THz frequencies where the gate-to-channel potential acquires a nonlocal character. Model calculations are performed for the exemplary case of a 65-nm Si CMOS TeraFET in the isothermal approximation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3090-3098"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10965757","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of Back-Gate Bias on the Total Ionizing Dose and Hot Carrier Injection Effects in Double SOI nMOSFETs","authors":"Yuan Gao;Zihan Wang;Yongwei Chang;Zhongying Xue;Xing Wei","doi":"10.1109/TED.2025.3552744","DOIUrl":"https://doi.org/10.1109/TED.2025.3552744","url":null,"abstract":"Double silicon-on-insulator (DSOI) device exhibits high tolerance to total ionizing dose (TID) effect due to back gate bias (<inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula>) modulation. Negative <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula> is required to compensate for the performance degradation caused by the TID effect, while positive <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula> is required to compensate for the degradation caused by hot carrier injection (HCI) effect. This article focuses on the synergistic effect between TID and HCI under different back-gate voltage and modulation effect of <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula>. The HCI effect is exacerbated by TID effect owing to the trapped charges in the oxide, which enhance the impact of ionizing in channel region. <inline-formula> <tex-math>${Delta } {V}_{text {th}}$ </tex-math></inline-formula> [<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> at 3 Mrad(Si) <inline-formula> <tex-math>$- {V}_{text {th}}$ </tex-math></inline-formula> at 0 Mrad(Si)] of DSOI MOSFET without stress is approximately −0.215 V, larger than that of stressed device. Additionally, applying a back-gate bias to mid-Si is an effective method to suppress the degradation in synergistic experiments.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2159-2164"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting Quasi-Volatility in Silver-Doped RRAMs for Physical Unclonable Functions Toward Robust Security Primitives","authors":"Guobin Zhang;Zhen Wang;Qi Luo;Bin Yu;Can Li;Qing Wan;Yishu Zhang","doi":"10.1109/TED.2025.3556101","DOIUrl":"https://doi.org/10.1109/TED.2025.3556101","url":null,"abstract":"Resistance random access memory (RRAM)-based physical unclonable functions (PUFs) have emerged as promising security primitives owing to their ability to generate reliable, unpredictable maps. In this study, we propose a novel PUF architecture that leverages the quasi-volatility of temporal and spatial randomness in a <inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula> crossbar array composed of silver-doped RRAM devices. The proposed PUF constructs a unique identifier based on the intrinsic switching variability and temporal retention characteristics of the RRAM devices. This dual source of randomness ensures high unpredictability and robustness against environmental noise and common modeling attacks. In optimized experiments, the PUF achieved uniformity, inter-hamming distance (inter-HD), and intra-hamming distance (intra-HD) metrics of 49.9%, 50.11%, and 0%, respectively, demonstrating strong stability and resistance to bit errors. The architecture incorporates a temporal majority voting (TMV) scheme to correct bit errors without additional hardware, achieving a bit error rate (BER) of 0%. These results highlight the potential of this RRAM-based PUF for secure key and identification-generation applications, especially in demanding internet of things (IoT) and embedded systems. Future work will focus on further evaluating the resilience against advanced attacks and integrating the PUF into complete security systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2347-2353"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dabok Lee;Jonghyeon Ha;Minki Suh;Minsang Ryu;Mikaël Cassé;Sergio Nicoletti;Dae-Young Jeon;Jungsik Kim
{"title":"Investigation of TID and DD Effects on FD SOI Nanowire FET Induced by Proton Irradiation","authors":"Dabok Lee;Jonghyeon Ha;Minki Suh;Minsang Ryu;Mikaël Cassé;Sergio Nicoletti;Dae-Young Jeon;Jungsik Kim","doi":"10.1109/TED.2025.3558489","DOIUrl":"https://doi.org/10.1109/TED.2025.3558489","url":null,"abstract":"In this study, radiation-induced degradation, which is caused by total ionizing dose (TID) and displacement defect (DD) effect, is investigated in fully depleted silicon-on-insulator (FD SOI) nanowire field-effect transistors (NWFETs) under 25-MeV proton irradiation. The combined effect of TID and DD degraded the subthresh old swing (SS) and <sc>off</small>-state current (Ioff) of n-type FD SOI NWFETs, while it degraded the threshold voltage (Vth) and <sc>on</small>-state current (Ion) of p-type FD SOI NWFETs. This degradation was sensitive to increases in proton fluence. Additionally, as the gate length (Lg) decreased, the degradation due to DD effect increased, aggravating the degradation due to the combined effects of TID and DD. However, narrow devices with improved side gate control mitigated the effects of the interface traps, oxide traps, positive charge trapped in the spacer, and DD.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2795-2800"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144196870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}