IEEE Transactions on Electron Devices最新文献

{"title":"Optimization of InGaAs/GaAsSb on InP Type-II Superlattice Photodiode for Extended-SWIR: A Comprehensive Study From Simulation to Photodiode Characterization","authors":"Jordi Roubichou;Jean-Luc Reverchon;Axel Evirgen;Vincent Gueriaux;Gérard Berginc;Jean-Luc Gach;Jean-Luc Beuzit","doi":"10.1109/TED.2025.3587664","DOIUrl":"https://doi.org/10.1109/TED.2025.3587664","url":null,"abstract":"In recent years, interest in the extended short-wave infrared (eSWIR) band has grown significantly. The current state-of-the-art III–V short-wave infrared detectors are InGaAs photodiodes (PDs) lattice-matched to InP substrates, limited by a cutoff wavelength of <inline-formula> <tex-math>$1.7~mu $ </tex-math></inline-formula>m. Superlattice-based detectors have the potential to extend detection beyond this limit while offering higher operating temperatures, simplified epitaxial growth, and reduced manufacturing costs compared to II–VI technologies. Such solutions could push the boundaries of short-wave infrared detection and enable new applications in defense, astronomy, and other fields requiring enhanced infrared imaging. In this context, a collaborative effort involving Thales, III–V Lab, and the Marseille Astrophysics Laboratory is exploring a novel approach to extend the SWIR detection range using superlattices. Building on the well-established InGaAs-on-InP technology, a three-layer strain-compensated superlattice structure has been proposed to mitigate limitations such as carrier localization and restricted vertical transport. This article presents recent results demonstrating significant improvements in quantum efficiency (QE) and carrier delocalization, achieving detection performance up to <inline-formula> <tex-math>$2.5~mu $ </tex-math></inline-formula>m. Simulations and experimental characterizations at the PD level were performed to assess the solution’s performance. The study particularly focuses on vertical transport, carrier localization, and minority carrier lifetime, examining their influence on overall imager performance to highlight the benefits and challenges of the proposed eSWIR detector architecture.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5024-5030"},"PeriodicalIF":3.2,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Backside Contact Misalignment-Induced TDDB in BSPDN CFET","authors":"Dabin Park;Eungyo Jang;Myeongjae Choi;Changhwan Shin","doi":"10.1109/TED.2025.3588518","DOIUrl":"https://doi.org/10.1109/TED.2025.3588518","url":null,"abstract":"Complementary field-effect transistors (CFETs) and backside contacts (BSCs) are the effective approaches for reducing cell layout size. However, since BSC is formed post wafer bonding and extreme wafer thinning, bonding-induced wafer distortion inevitably introduces BSC alignment challenges, with control of its misalignment toward the layers on the wafer’s frontside requiring careful attention. As misalignment increases, the distance between the BSC and the gate decreases, resulting in a strong electric field concentration in the bottom oxide of the CFET. In this study, metal–insulator–metal (MIM) capacitors with gate-to-BSC overlap caused by misalignment were fabricated and used to calibrate a time-dependent dielectric breakdown (TDDB) simulation. Additionally, using 3-D technology computer-aided design (TCAD), we extracted the electric field applied to the bottom oxide as a function of misalignment, based on both experimental data and the calibrated CFET model. By inputting the extracted electric field into the TDDB simulator, we evaluated the degradation of oxide lifetime. The results show that using Mo metal for the BSC significantly reduces the electric field compared to W metal, thereby leading to an overall increase in TDDB lifetime. These findings provide valuable insights into the impact of BSC misalignment on CFET reliability and highlight the importance of material selection and precise alignment control for process optimization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4648-4654"},"PeriodicalIF":3.2,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of Electrical Properties for Vertical Vacuum Diodes With Multiregion Electron Emission Structures","authors":"Wenhua Tang;Zhenfei Hou;Kerun Chen;Jie Li;Zhihua Shen;Xiao Wang;Gang Niu;Shengli Wu","doi":"10.1109/TED.2025.3588139","DOIUrl":"https://doi.org/10.1109/TED.2025.3588139","url":null,"abstract":"Vertical nanoscale channel vacuum diode (VNCVD) with multiregion electron emission structures was constructed using ion beam etching and photolithography. The influence of multiregion electron emission on the electrical characteristics of VNCVD was investigated through simulations and experiments. Compared with the conventional annular single-region electron emission structure, the proposed multiannular design increases the number of emission regions and effectively expands the electron transport channel within the same plane. The optimized triple-ring electron emission structure possesses an emission current of <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>A at the bias of 1.1 V (n-type Si cathode) under atmospheric conditions. It is proposed that the multiedge effect and interring electric field superposition is primarily responsible for the emission current enhancement in multiring structures. In the design of multiring structures, a reasonable ring spacing (<inline-formula> <tex-math>$gt 2~mu $ </tex-math></inline-formula>m) should be chosen to avoid field shielding effects. This study demonstrates a nanoscale multichannel vacuum diode that effectively enhances electron emission performance, which paves the way for the development of high-performance vacuum microelectronic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5189-5194"},"PeriodicalIF":3.2,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Method for Measurement of Source Resistance of Top-Contact Pentacene Organic Thin-Film Transistors","authors":"Umang Singh;Hitesh Kumar;Ram Krishna Dewangan;Abhishek Kumar Verma;Somendra Kumar Soni;Vinay Kumar Singh","doi":"10.1109/TED.2025.3588145","DOIUrl":"https://doi.org/10.1109/TED.2025.3588145","url":null,"abstract":"In this article, the source resistance of top-contact bottom gate (TCBG) organic thin-film transistor (OTFT) was directly measured using another contact parallel to source contact. Three-dimensional numerical simulation was used to validate the proposed method. TCBG OTFT with pentacene as active layer and poly(4-vinyl phenol) (PVP) as dielectric layer was used to calculate the source resistance. Gold was deposited through shadow mask to fabricate OTFT and contacts.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5118-5122"},"PeriodicalIF":3.2,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synthetic Antiferromagnet Reversal—Role of Thermal and Magnetic Stress and Impact on Functionality of STT-MRAM","authors":"Meike Hindenberg;Johannes Müller;Christoph Durner;Daniel Sanchez Hazen;Martin Weisheit;Thomas Mikolajick","doi":"10.1109/TED.2025.3586827","DOIUrl":"https://doi.org/10.1109/TED.2025.3586827","url":null,"abstract":"We investigate the response of magnetic tunnel junction (MTJ) devices based on GlobalFoundries 22FDX <xref>1</xref> embedded-magnetic random access memory (MRAM) technology to external thermal and magnetic stress. An anomalous reversal of the reference system was observed in some devices when subjected to a constant static external magnetic field at temperatures as high as <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C. The strength of the external magnetic field, ambient temperature, MTJ diameter, and composition of the synthetic antiferromagnet (SAF) reference system all affect the severity of the reference system’s instability. In this study, we show that while a SAF reversal in single-bit MTJ devices reverses the direction of their <italic>R</i>–<italic>H</i> hysteresis loop and so their switching field and offset field polarity, it does not significantly impact their electrical switching behavior. Furthermore, we experimentally show that the functionality of 40-Mbit MRAM arrays with a pitch of approximately 200 nm remains unaffected by the SAF configuration and consequent offset field polarity of the individual devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4844-4850"},"PeriodicalIF":3.2,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11080341","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress in Single- and Multiribbon Complementary FETs (CFETs): Evolution in Process Flow and Impact on Drive Current","authors":"Achintya Dutta;Geert Eneman;Nicole K. Thomas;Philippe Matagne;Marko Radosavljević","doi":"10.1109/TED.2025.3584743","DOIUrl":"https://doi.org/10.1109/TED.2025.3584743","url":null,"abstract":"It is anticipated that strain engineering in nanosheet architectures, including complementary FETs (CFETs), will be challenging using conventional S/D epitaxy methods. This work investigates strain retention in CFETs through coupled mechanical and device simulations, offering integration-relevant suggestions for scalable strain engineering. A self-aligned process flow was simulated to identify stress-inducing steps: 1) S/D recess; 2) Si<inline-formula> <tex-math>${}_{{0}.{4}}$ </tex-math></inline-formula>Ge<inline-formula> <tex-math>${}_{{0}.{6}}$ </tex-math></inline-formula> S/D epitaxy; and 3) nanoribbon (NR) release. The final device is projected to retain 1.3-GPa (compressive) and +500-MPa (tensile) stress in the pMOS and nMOS channel, respectively. Even without S/D engineering, for nMOS, tensile channel stress arises due to strain imparted by the sacrificial layers (SLs), which also counteracts compressive stress in the pMOS channel. Consequently, Ge% in SLs is identified as a critical knob for tuning stress, as lowering it may enhance compressive stress in pMOS NRs, while employing different Ge% for nMOS/pMOS SLs could enable independent stress modulation. Furthermore, stress transfer in pMOS NRs is projected to rely on substrate anchoring of the S/D epi, thereby confining them to the bottom. The retained stress is predicted to remain unaffected by backside processing. Channel stress is also observed to scale with S/D volume, with multiribbon pMOS featuring increased compressive stress, albeit with 15%20% reduction in topmost ribbons. Simulated transfer characteristics estimate negligible drive current differences between (100)- and (110)-surfaces at high compressive stress (<inline-formula> <tex-math>$ge 1$ </tex-math></inline-formula> GPa), while (110) remains favorable under lower stress. The simulations presented provide insights to guide technological choices for integrating strained channels in CFETs and outlines directions for experimental validation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4735-4741"},"PeriodicalIF":3.2,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Method for High Power Sheet Beam Traveling Wave Tube by Rotating the Beam Tunnel","authors":"Wuyang Fan;Pengcheng Yin;Jin Xu;Jian Zhang;Yue Ouyang;Zixuan Su;Jinchi Cai;Lingna Yue;Hairong Yin;Yong Xu;Guoqing Zhao;Wenxiang Wang;Yanyu Wei","doi":"10.1109/TED.2025.3585903","DOIUrl":"https://doi.org/10.1109/TED.2025.3585903","url":null,"abstract":"The instability of the sheet electron beam (SEB) is an essential factor for limiting the power of the SEB traveling wave tube (TWT). To solve this issue, this article proposes a method to improve the output power of SEB TWTs, which introduces a rotating electron tunnel, following the SEB’s deflection instability, to significantly increase the input current and output power. In addition, the outer profile of the slow wave structure (SWS) is formed as a cylindrical to prevent this rotation from changing the high-frequency characteristics. To verify this method, a novel staggered double vane with a rotating tunnel (SDV-RT) SWS is proposed in this article. Moreover, a W-band TWT employing this new SWS is designed and simulated. The results illustrate that the beam current increases by approximately 57% under a uniform magnetic field of 0.85 T. Simulation results indicate that the designed SDV-RT TWT, operating with 1.1-A beam current and 27-kV beam voltage, achieves an output power over 2400 W, with a maximum power of 2759 W at 92 GHz. The output power is approximately 60% higher than that of conventional SDV devices under the same magnetic field. Additionally, an electron optical system (EOS) is designed to validate the effect of the RT method on enhancing output power under conditions of nonideal SEB and nonideal uniform magnetic fields. At last, the designed SWS has been fabricated, and the cold test results indicate that the S11 is below −16.5 dB and the S21 is above −2 dB in the frequency range of 90–100 GHz, showing good agreement with the simulation results.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5169-5175"},"PeriodicalIF":3.2,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unique Surface Passivation Stoichiometry Dependence of Dynamic On-Resistance and Its Suppression in p-GaN Gate AlGaN/GaN HEMTs","authors":"Rasik Rashid Malik;Vipin Joshi;Saniya Syed Wani;Simran R. Karthik;Rajarshi Roy Chaudhuri;Avinas N. Shaji;Zubear Khan;Mayank Shrivastava","doi":"10.1109/TED.2025.3585910","DOIUrl":"https://doi.org/10.1109/TED.2025.3585910","url":null,"abstract":"In this work, we demonstrate the mitigation of dynamic <sc>on</small>-resistance in p-GaN gate AlGaN/GaN HEMTs by tuning the stoichiometry of an ex-situ deposited surface passivation layer. Detailed experiments using high-voltage nanosecond pulsed measurements and a fast-switching train of pulses are employed to analyze the dynamic <sc>on</small>-resistance behavior of the devices. Frequency-based analysis, electroluminescence analysis, substrate bias dependence, and self-heating profile analysis are used in conjunction with electrical characterization to gain insights into the physical mechanisms related to the dynamic <sc>on</small>-resistance dependence on surface passivation stoichiometry. Finally, X-ray photoelectron spectroscopy, cathodoluminescence, and capacitance–voltage analysis reveal that the reduction in surface trap density with nonstoichiometric SiOX passivation leads to improved dynamic <sc>on</small>-resistance. These findings establish surface passivation stoichiometry as a critical design parameter for alleviating the problem of dynamic <sc>on</small>-resistance in GaN-based power devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5073-5079"},"PeriodicalIF":3.2,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization Methods of TMD Transistor Gate Dielectrics Targeting 1 nm EOT for 2-D CMOS Scaling","authors":"Chelsey Dorow;Aniruddha Konar;Ande Kitamura;Ashish Penumatcha;Sudarat Lee;Adedapo Oni;Chi-Yin Cheng;Nazmul Arefin;Kevin O'Brien;Scott B. Clendenning;David Kencke;Uygar Avci","doi":"10.1109/TED.2025.3586220","DOIUrl":"https://doi.org/10.1109/TED.2025.3586220","url":null,"abstract":"2-D materials show promise to possibly replace Si channel material to continue Moore’s Law scaling of transistors down to 5 nm gate lengths. The scaling opportunities of 2-D materials arise due to their ultra-thin monolayer thickness of sub-1 nm, which allows for strong electrostatic gate control while maintaining high mobility with virtually no surface roughness scattering from the intrinsically passivated van der Waals (vdW) surfaces. The scaling benefits of 2-D materials, however, can only be realized with the development of a highly scaled, low-defect gate oxide growth method compatible with vdW surfaces. This has thus far proven to be challenging as the vdW surfaces lack the dangling bonds required for standard ALD oxide growth nucleation. Furthermore, gate oxide films grown on vdW surfaces are rarely characterized following industry standard capacitance–voltage (CV) methods, primarily due to high leakage or resistance often present in today’s 2-D transistors, rendering CV measurements very difficult. While 2-D MOSFET gate leakage and contact resistances are improving rapidly, researchers still resort to inferring equivalent oxide thickness (EOT) from I–V characterization rather than standard CV. In this work, we show through both technology computer aided design (TCAD) simulations and experiments that I–V based methods of 2-D MOSFET EOT measurements have several pitfalls which may lead to inaccurate conclusions. We provide techniques to improve accuracy for both I–V and CV-based gate oxide characterization, which will help accelerate the field of 2-D transistor development closer toward a feasible CMOS technology.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"3974-3980"},"PeriodicalIF":2.9,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Enhancement of InGaZnO Thin-Film Transistors via Rapid Cooling Process and Their Application in Logic Circuits","authors":"Shuo Zhang;Bin Liu;Xianwen Liu;Xuyang Li;Dan Kuang;Qi Yao;Congyang Wen;Xiaorui Zi;Ziyan Jia;Guangcai Yuan;Jian Guo;Ce Ning;Daiwei Shi;Feng Wang;Zhinong Yu","doi":"10.1109/TED.2025.3587676","DOIUrl":"https://doi.org/10.1109/TED.2025.3587676","url":null,"abstract":"Nowadays, metal oxide thin-film transistors (TFTs) widely utilized in the driving circuits of various high-technology display products. Enhancing the electrical performance of metal oxide TFTs to meet the requirements of rapidly developing display products is a prominent research focus at present. In this article, we present a process of rapid cooling of annealed indium gallium zinc oxide (IGZO) TFTs using low-temperature deionized water for the first time. Compared to samples fabricated using conventional processes, the treated samples exhibited significantly enhanced electrical performance. The mobility has doubled (10.6 cm2V<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{-{1}} to {25.3}$ </tex-math></inline-formula> cm2V<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>). The threshold voltage and subthreshold swing (S.S) were also very small (0.27 V, 0.25 V/dec). Drawing on semiconductor energy band theory, we developed a theoretical model to elucidate the evolution of defect states in IGZO during rapid cooling by integrating device electrical characterization and thin-film analysis of the active layer. The observed improvement in electrical performance was attributed to the rapid cooling process, which mitigated the formation of active layer defect states and reduced carrier trapping at trap energy levels. The enhanced devices were also applied to logic circuits, realizing the functions of inverters, NAND gates, and NOR gates. This work introduces a simple and environmentally friendly method, offering a novel strategy to enhance the performance of TFTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4955-4962"},"PeriodicalIF":3.2,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}