IEEE Transactions on Electron Devices最新文献_第9页

Enhanced Performance of FeFETs With TiN/SiO2/Hf0.5Zr0.5O2/SiO2/Si Gate Structure via Oxygen Post-Deposition Annealing Tailoring 氧沉积后退火裁剪TiN/SiO2/Hf0.5Zr0.5O2/SiO2/Si栅极结构增强fefet性能

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-06-22 DOI: 10.1109/TED.2026.3702648

Yuhan Li;Xianzhou Shao;Tao Hu;Ruoyao Ji;Mengwei Zhao;Zeqi Chen;Xiaoyu Ke;Kai Han;Hao Xu;Xiaolei Wang;Wenwu Wang;Tianchun Ye

{"title":"Enhanced Performance of FeFETs With TiN/SiO2/Hf0.5Zr0.5O2/SiO2/Si Gate Structure via Oxygen Post-Deposition Annealing Tailoring","authors":"Yuhan Li;Xianzhou Shao;Tao Hu;Ruoyao Ji;Mengwei Zhao;Zeqi Chen;Xiaoyu Ke;Kai Han;Hao Xu;Xiaolei Wang;Wenwu Wang;Tianchun Ye","doi":"10.1109/TED.2026.3702648","DOIUrl":"https://doi.org/10.1109/TED.2026.3702648","url":null,"abstract":"In this study, an oxygen atmosphere post-deposition annealing (O2 PDA) method is proposed to enhance the performance of ferroelectric field-effect transistors (FeFETs) with the TiN/SiO2/Hf0.5Zr0.5 O2/SiO2/Si gate structure. The O2 treatment duration was varied, ranging from 0 s (without PDA) to 120 s, with 30 and 60 s as intermediate conditions, and the key findings are as follows: 1) the memory window (MW) first increases and then decreases as O2 PDA duration increases. The maximum MW is achieved under 60 s O2 PDA, which exhibits a 16% enhancement compared to the 0 s condition, attributed to the increased charge trapping at the SiO2/Hf0.5Zr0.5 O2 interface; and 2) the O2 PDA treatment improves endurance from <inline-formula> <tex-math>$3times 10^{{4}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$2times 10^{{5}}$ </tex-math></inline-formula> cycles, which is attributed to suppressing defect generation near the channel-side interface. The linear extrapolation suggests all devices with different O2 PDA durations achieve a data retention of ten years. This study provides a viable strategy for advancing the development of MIFIS-FeFETs targeting 3-D VNAND applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4841-4848"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reduced Operating Voltage and Enhanced Endurance in Defect-Engineered HZO MFS Ferroelectric Capacitors With Nondestructive Read 缺陷工程HZO MFS非破坏性读取铁电电容器的工作电压降低和寿命提高

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-06-18 DOI: 10.1109/TED.2026.3701863

Peiyuan Du;Huan Liu;Dongya Li;Yutai Man;Fei Yu;Hongrui Zhang;Bing Chen;Ran Cheng;Mengnan Ke;Yan Liu;Xiao Yu;Yue Hao;Genquan Han

{"title":"Reduced Operating Voltage and Enhanced Endurance in Defect-Engineered HZO MFS Ferroelectric Capacitors With Nondestructive Read","authors":"Peiyuan Du;Huan Liu;Dongya Li;Yutai Man;Fei Yu;Hongrui Zhang;Bing Chen;Ran Cheng;Mengnan Ke;Yan Liu;Xiao Yu;Yue Hao;Genquan Han","doi":"10.1109/TED.2026.3701863","DOIUrl":"https://doi.org/10.1109/TED.2026.3701863","url":null,"abstract":"In this work, a novel inversion-type ferroelectric memory featuring a TiAlO<inline-formula> <tex-math>${}_{x}$ </tex-math></inline-formula>/HfO2-ZrO2 superlattice (SL) structure on germanium is proposed, demonstrating nondestructive readout and industrial-grade endurance. The optimized device achieves a high capacitance modulation ratio (<inline-formula> <tex-math>${C}_{text {HCS}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${C}_{text {LCS}}text {)}$ </tex-math></inline-formula> exceeding 14, with stable four-state operation sustained over <inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula> cycles and two-state endurance extended to <inline-formula> <tex-math>$10^{{8}}$ </tex-math></inline-formula> cycles at 50 kHz. Key innovations include a TiO2-induced TiAlO<inline-formula> <tex-math>${}_{x}$ </tex-math></inline-formula> interlayer that suppresses interfacial oxygen-vacancy migration and an engineered HfO2/ZrO2 SL that promotes a more uniform distribution of defects within the ferroelectric stack. Low-frequency noise analysis and depth-resolved trap profiling corroborate the reduced interfacial defect density and the more uniform defect landscape, together explaining the improved endurance and reliability. The proposed devices also exhibit reduced read voltage requirements while enabling four-state operation, highlighting their potential for low-power neuromorphic hardware and energy-constrained edge computing applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4849-4855"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

AC Reliability in Advanced CMOS Technology: From Trap Behavior to Circuit Aging Simulation 先进CMOS技术中的交流可靠性：从陷阱行为到电路老化模拟

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-03-17 DOI: 10.1109/TED.2026.3671738

Zixuan Sun;Yu Li;Anyi Zhu;Hongbo Wang;Hengyi Liu;Lining Zhang;Runsheng Wang

{"title":"AC Reliability in Advanced CMOS Technology: From Trap Behavior to Circuit Aging Simulation","authors":"Zixuan Sun;Yu Li;Anyi Zhu;Hongbo Wang;Hengyi Liu;Lining Zhang;Runsheng Wang","doi":"10.1109/TED.2026.3671738","DOIUrl":"https://doi.org/10.1109/TED.2026.3671738","url":null,"abstract":"With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanoscale regime, the reliability of devices under dynamic operating conditions has emerged as a critical challenge determining the performance and lifespan of integrated circuits. Traditional assessment methods based on direct current (DC) stress are inadequate for accurately capturing device degradation behaviors during actual alternating current (AC) operation. This article systematically reviews recent research progress in AC reliability from the perspective of trap dynamics, highlighting its crucial role in reliability-aware circuit design. Beginning with as-grown traps responsible for random telegraph noise (RTN) and bias temperature instability (BTI), the article delves into the dynamic characteristics of AC RTN and AC BTI. It elucidates that AC RTN exhibits complex frequency dependencies in its capture/emission time constants and effective occupancy probability, which directly impacts the timing integrity of digital circuits. Then, this review subsequently extends to the dynamic behavior of generated traps, covering AC hot carrier degradation (HCD) and AC time-dependent dielectric breakdown (TDDB). Furthermore, we summarize and compare circuit-level simulation frameworks developed to evaluate these reliability mechanisms, along with their application in predicting performance degradation in key circuit modules such as ring oscillators (ROs). This review aims to provide a clear and comprehensive overview of AC reliability physics and emphasizes the urgency and importance of integrating dynamic, electro-thermal co-simulation methodologies into the design for reliability of future ICs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4588-4597"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Correction of Self-Heating Effects in Hot Carrier Reliability Assessment of Gate-All-Around Nanosheet Devices 栅极纳米片器件热载流子可靠性评估中自热效应的修正

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-07-08 DOI: 10.1109/TED.2026.3700573

Y. Song;M. Wang;H. Zhou;Y. Isobe;N. Fokas;K. Takano;K. Okada;H. Miki;Y. Liu;G. Jaramillo;J. Satterlee

{"title":"Correction of Self-Heating Effects in Hot Carrier Reliability Assessment of Gate-All-Around Nanosheet Devices","authors":"Y. Song;M. Wang;H. Zhou;Y. Isobe;N. Fokas;K. Takano;K. Okada;H. Miki;Y. Liu;G. Jaramillo;J. Satterlee","doi":"10.1109/TED.2026.3700573","DOIUrl":"https://doi.org/10.1109/TED.2026.3700573","url":null,"abstract":"Self-heating effects (SHEs) are substantially more pronounced in gate-all-around (GAA) nanosheet (NS) devices compared to their FinFET predecessors. This behavior arises from the absence of a bulk thermal path for active channels, which limits heat dissipation, combined with aggressive channel length scaling and the higher drive currents enabled by the GAA architecture. Elevated device temperatures not only increase reliability concerns but also complicate accurate evaluation of hot-carrier injection (HCI) degradation. In this work, we investigate the influence of SHE during DC hot-carrier stress (HCS) and assess the impact of SHE correction on HCI kinetics and the extraction of key modeling parameters. Our results demonstrate that proper SHE correction is critical for accurate determination of activation energy (Ea) and voltage acceleration factor (VAF) in NS devices. Furthermore, we show that the time exponent exhibits minimal temperature dependence and is only slightly affected by SHE correction. Testing at temperatures up to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C remains suitable for mid-VG DC HCS when appropriate SH correction is applied. These findings provide essential guidance for reliability assessment and qualification in NS technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4581-4587"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dual-Mode n-Type Electrochemical Transistors for Dynamic-Static Fused Vision Perception 动态-静态融合视觉感知双模n型电化学晶体管

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-06-23 DOI: 10.1109/TED.2026.3703769

Zhuoxiao Xie;Yujie Peng;Lin Gao;Changjian Liu;Canghao Xu;Yuhong Yang;Haihong Guo;Haozhe Liu;Ding Zheng;Junsheng Yu

{"title":"Dual-Mode n-Type Electrochemical Transistors for Dynamic-Static Fused Vision Perception","authors":"Zhuoxiao Xie;Yujie Peng;Lin Gao;Changjian Liu;Canghao Xu;Yuhong Yang;Haihong Guo;Haozhe Liu;Ding Zheng;Junsheng Yu","doi":"10.1109/TED.2026.3703769","DOIUrl":"https://doi.org/10.1109/TED.2026.3703769","url":null,"abstract":"Artificial vision systems must sense both static spatial cues and dynamic temporal trajectories, but hardware-efficient fusion at the sensory front end remains challenging. We demonstrate dual-mode static-dynamic fused perception using ion-modulated vertical organic electrochemical transistors (vOECTs) integrated with a photosensor light-dependent resistor (LDR), enabling deterministic switching between photodetection (PD) and photosynaptic (PS) functions. By swapping the dominant cation from Na+ to Ca<inline-formula> <tex-math>${}^{text {2} +}$ </tex-math></inline-formula> in a physically (hydrogen-bond) crosslinked biogel electrolyte, we explore electrochemical (de)doping kinetics via controlled ion mobility, penetration, and retention. Na+-based vOECT-LDR circuit yields fast, high-sensitivity photoresponse for static sensing, whereas the Ca<inline-formula> <tex-math>${}^{{2}+}$ </tex-math></inline-formula>-based circuit exhibits robust synaptic plasticity for dynamic perception. Moreover, we implement both arrays and validate static-dynamic fusion perception in high-speed badminton monitoring, achieving simultaneous trajectory reconstruction and landing-point determination. These results establish vOECT-LDR front ends as a scalable path to neuromorphic vision for mixed scenes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5062-5065"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Anode Thermal Management in Pulsed Field Emission via Carbon Nanotube Cold Cathodes 碳纳米管冷阴极脉冲场发射的阳极热管理

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-06-17 DOI: 10.1109/TED.2026.3701342

Jiaqi Wang;Fred Sun;Guanxuan Lu;Lang Wang;John T. W. Yeow

{"title":"Anode Thermal Management in Pulsed Field Emission via Carbon Nanotube Cold Cathodes","authors":"Jiaqi Wang;Fred Sun;Guanxuan Lu;Lang Wang;John T. W. Yeow","doi":"10.1109/TED.2026.3701342","DOIUrl":"https://doi.org/10.1109/TED.2026.3701342","url":null,"abstract":"Thermal management in high-power electron sources is constrained by the continuous heat load of traditional thermionic cathodes, leading to severe thermal stress and anode degradation. Here, we demonstrate an efficient thermal-management strategy using a carbon nanotube (CNT) cold cathode operated in a pulsed field emission regime. Spatiotemporal thermodynamic simulations show that low duty-cycle operation promotes rapid radial heat diffusion and enables thermal relaxation between consecutive pulses, thereby preventing cumulative temperature rise. Then, we demonstrate this thermally decoupled mechanism experimentally in a high-vacuum environment by directly measuring the anode temperature. At a constant time-averaged emission current of 1 mA, continuous stability tests confirm stable CNT-array operation across a range of pulsed conditions. Moreover, the measured power consumption exhibits a nonlinear dependence on duty cycle. Extracting a 10-mA peak current at a 10% duty cycle minimizes the integrated energy deposited on the anode and suppresses the anode temperature to approximately <inline-formula> <tex-math>$190~^{circ }$ </tex-math></inline-formula>C. This approach eliminates time-integrated thermal accumulation and mitigates thermal damage, enabling a highly stable electron-source architecture for advanced high-voltage applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5179-5187"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Frequency-Tunable Magnetron Using Barium Strontium Titanate Ceramics 钛酸钡锶陶瓷的频率可调磁控管

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-06-23 DOI: 10.1109/TED.2026.3702989

Zheng Yang;Jianlong Liu;Zhaoyang Tang;Kongyi Hu;Dayang Wang;Zhijianmucuo Dong;Yong Tao;Baoqing Zeng

{"title":"Frequency-Tunable Magnetron Using Barium Strontium Titanate Ceramics","authors":"Zheng Yang;Jianlong Liu;Zhaoyang Tang;Kongyi Hu;Dayang Wang;Zhijianmucuo Dong;Yong Tao;Baoqing Zeng","doi":"10.1109/TED.2026.3702989","DOIUrl":"https://doi.org/10.1109/TED.2026.3702989","url":null,"abstract":"Frequency tunability is of great significance for improving the heating uniformity of food in microwave ovens, but existing tunable magnetrons face challenges in large-scale application within microwave ovens. In this article, we study a tunable magnetron utilizing barium strontium titanate (BST) ceramics. Three-dimensional particle-in-cell (PIC) simulations predict that this magnetron maintains a power output of 3.4 kW, an efficiency of 69.2%, and a high mode separation ratio of 67% while achieving a tuning bandwidth of 63 MHz, demonstrating pure and stable <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-mode oscillation. Furthermore, the feasibility of the design is indirectly validated using structurally simple BST ceramic plates, achieving a tuning bandwidth of 39.2 MHz under a 1.6 kV negative bias. This design not only conveniently and rapidly achieves a relatively wide tuning bandwidth but also largely preserves some core advantages of microwave oven magnetrons: simple, compact structure, and low cost. Therefore, this design provides a promising technical pathway for improving food heating uniformity in microwave ovens. Meanwhile, its rapid electrical frequency tuning capability also offers potential application prospects in enhancing the information dimension of radar system detection.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"5188-5194"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Transactions on Electron Devices Publication Information IEEE电子设备出版信息汇刊

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-08-10 DOI: 10.1109/TED.2026.3711234

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Guest Editorial: T-ED Special Issue on Reliability of Advanced Nodes 嘉宾评论：T-ED高级节点可靠性专题

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-08-10 DOI: 10.1109/TED.2026.3711245

Francesco Maria Puglisi;Zakariae Chbili

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Toward Suppression of Bias Instability in Monolayer WSe2 Top-Gate pFETs 抑制单层WSe2顶栅pfet偏置不稳定性的研究

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-08-01 Epub Date: 2026-03-28 DOI: 10.1109/TED.2026.3693214

Yu-Wei Hsu;Chen-Hsun Hsu;Ching-Shuan Huang;Nien-En Chiang;Yun-Cheng Liu;Ting-Hua Wei;Sin-Yue Lee;Chris Yeh;I-Chih Ni;Hung-Li Chiang;Chih-I Wu;Tsung-En Lee

{"title":"Toward Suppression of Bias Instability in Monolayer WSe2 Top-Gate pFETs","authors":"Yu-Wei Hsu;Chen-Hsun Hsu;Ching-Shuan Huang;Nien-En Chiang;Yun-Cheng Liu;Ting-Hua Wei;Sin-Yue Lee;Chris Yeh;I-Chih Ni;Hung-Li Chiang;Chih-I Wu;Tsung-En Lee","doi":"10.1109/TED.2026.3693214","DOIUrl":"https://doi.org/10.1109/TED.2026.3693214","url":null,"abstract":"This work presents the first systematic investigation of the bias instability of monolayer (1L) WSe2 top-gate p-type field-effect transistors (pFETs). A multilayer gate-stack is proposed to address the unique reliability challenges of 2D semiconductors, leveraging their van der Waals (<italic>vdW) interface for low interface trap density (D<inline-formula> <tex-math>${}_{text {it}}text {)}$ </tex-math></inline-formula> and improved bias stability. The proposed stack integrates a 1 nm post-oxidized physical vapor deposition (PVD) AlOx interfacial layer (IL) to enhance hole density and suppress hydroxyl-related defects, a two-step atomic layer deposition (ALD) temperature for Hf/Zr-based higher-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> dielectrics to balance dielectric strength and channel degradation, and post-metallization annealing (PMA) for passivation of vacancy and hydrogen-related traps. With an equivalent oxide thickness (EOT) scaled to 0.8 nm, the fabricated long-channel devices achieve near-ideal subthreshold swing (S.S.) (S.S.<inline-formula> <tex-math>$approx$ </tex-math></inline-formula>65 mV/dec) and negligible hysteresis at room temperature. The extrapolated lifetime projection indicates excellent bias stability, with the threshold voltage shift (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}_{text {T}}text {)}$ </tex-math></inline-formula> remaining below 90 mV under negative bias stress (NBS) and below 70 mV under positive bias stress (PBS) after ten years of operation at an effective stress field <inline-formula> <tex-math>$vert $ </tex-math></inline-formula>E<inline-formula> <tex-math>${}_{text {ox}}vert =5$ </tex-math></inline-formula> MV/cm. These results establish a scalable and thermally compatible gate dielectric integration for low-power 2D CMOS logic applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 8","pages":"4531-4536"},"PeriodicalIF":3.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148699430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0