IEEE Transactions on Electron Devices最新文献

{"title":"Higher Order Thermal Impedance Extraction of GaN Power HEMTs by I–V Measurements","authors":"Richard Reiner;Akshay G. Nambiar;Stefan Mönch;Michael Basler;Daniel Grieshaber;Philipp Döring;Patrick Waltereit;Rüdiger Quay","doi":"10.1109/TED.2025.3539594","DOIUrl":"https://doi.org/10.1109/TED.2025.3539594","url":null,"abstract":"This work presents a method for extracting higher order thermal models of GaN power high-electron mobility transistors (HEMTs) from I–V measurements using a typical commercial power analyzer. The approach involves deriving and fitting an electrothermal model function to measure data using a nonlinear least squares solver, yielding the thermal parameters for a higher order thermal model. Measurements are conducted using a parameter analyzer and a controlled thermal chuck, with a transient drain current response signal. The method is employed to derive the thermal impedance parameters of a 5th-order thermal Foster model for a GaN power transistor. The Foster model parameters are presented in both time and frequency domains and are subsequently transformed into Cauer model parameters. The results demonstrate strong agreement with data obtained from an on-chip temperature sensor, confirming the method’s validity. This new extraction method can be executed using standard laboratory equipment typically available for the electrical characterization of GaN power transistors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1650-1656"},"PeriodicalIF":2.9,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10887231","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Theoretical Model of Transient Current in CMOS Inverter Under IR Laser Pulse Responsible of Bitflip in FDSOI Technology","authors":"L. Pichon;L. Le Brizoual;H. Djeha;E. Ferrucho Alvarez;L. Claudepierre;J. L. Autran","doi":"10.1109/TED.2025.3538002","DOIUrl":"https://doi.org/10.1109/TED.2025.3538002","url":null,"abstract":"A theoretical model of the induced transient photocurrent in MOS transistor under laser illumination is proposed to predict an estimation of the incident power surface density of the laser required to create a bitflip. This model based on the physical effect of the laser interaction with the semiconductor material (silicon) takes into account the laser characteristics, the physical properties of the silicon, and the geometrical and technological parameters. The results highlight the volume effects, with a higher photocurrent level due to a higher total electron/hole pair generation for a thicker active layer, making the structures more sensitive to fault injection by pulsed IR laser, particularly for conventional bulk CMOS technologies and for FDSOI technologies based on FINFETs. This theoretical model combined with electrical model based on phototransistor is a good predictive tool in complements with TCAD simulations for studies of vulnerability analysis in advanced FDSOI silicon technologies and enables parametric analysis of physical phenomena related to the technology, in order to anticipate experimental studies of the vulnerability by laser fault injection of complex electronic systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1919-1925"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Extraction of the Specific Contact Resistance of GaN p-i-n Diodes up to 40 GHz","authors":"Kevin Nadaud;Zihao Lyu;Daniel Alquier;Quentin Paoli;Julien Ladroue;Arnaud Yvon;Eric Frayssinet;Yvon Cordier;Jérôme Billoué","doi":"10.1109/TED.2025.3539644","DOIUrl":"https://doi.org/10.1109/TED.2025.3539644","url":null,"abstract":"In this article, we propose a high-frequency model taking into account the series resistance of pseudo-vertical gallium nitride (GaN)-based p-i-n diodes. This model relies on the specific contact resistance on p-type GaN and the sheet resistance of the bottom n-type GaN. Those two quantities are obtained while fitting the RF experimental data and are slightly different from the dc values. The interest of this model is that the effective values, at the working frequency instead of “only” the dc values, are extracted using only a few devices. The novelty of the work resides in the consideration of the geometrical dimensions of the diode (anode radius and distance between anode and cathode) in the model. Furthermore, the model allows the determination of the most limiting geometrical parameters and can predict the series resistance of other topologies. In the present case, we show the most limiting factor is the radius of the anode due to the difficulties of achieving low specific contact resistance on p-type GaN. The parasitic capacitance is also extracted using the measured devices, allowing the modeling of the effective capacitance as a function of the frequency.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1657-1662"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstration of High-Performance 0.17-mΩ⋅cm²/800-V 4H-SiC Super-Junction Schottky Diodes via Multiepitaxial Growth and Channeled Implantation Techniques","authors":"Fengyu Du;Haobo Kang;Hao Yuan;Boyi Bai;Tianyu Shu;Jingyu Li;Yu Zhou;Chao Han;Xiaoyan Tang;Qingwen Song;Yuming Zhang","doi":"10.1109/TED.2025.3537070","DOIUrl":"https://doi.org/10.1109/TED.2025.3537070","url":null,"abstract":"This article demonstrates the fabrication of high-performance 4H-silicon carbide (SiC) super-junction (SJ) Schottky diodes utilizing channeled implantation and double epitaxial growth. The diodes, featuring a <inline-formula> <tex-math>$4.5-mu $ </tex-math></inline-formula>m-thick drift region and a <inline-formula> <tex-math>$4-mu $ </tex-math></inline-formula>m-thick SJ structure, underwent characterization encompassing both material and electrical attributes. After double epitaxial growth, the epitaxial layer showcased a maximum stress of 25.9 MPa. The full-width at half-maximum (FWHM) analysis underscored the exceptional quality of the 4H-SiC crystals across the entire wafer surface (FWHM < 25 arcsec), paralleled by atomic force microscopy (AFM) outcomes revealing an epitaxial layer with excellent smoothness (<inline-formula> <tex-math>${R}_{text {q}} lt 0.35$ </tex-math></inline-formula> nm). Devices fabricated on these high-quality wafers exhibited consistent performance and superior yield. Electrical property distributions revealed a breakdown voltage (BV) of 800 V alongside a specific <sc>on</small>-resistance (<inline-formula> <tex-math>${R}_{text {on},text {sp}})$ </tex-math></inline-formula> of 0.17 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2 and a record Baliga figure of merit (BFOM) value of 3.76 GW/cm2 (800 V), subtracting the substrate resistance, exceeding the 1-D theoretical limit of 4H-SiC successfully. Moreover, it is inferred that the channeled implantation technology is an attractive process for fabricating SiC SJ devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1872-1877"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical Analysis of Atomic Layer Deposited Thin HfO2 and HfO2/Ta2O5-Based Memristive Devices","authors":"Sanjay Kumar;Deepika Yadav;Rahul Ramesh;Spyros Stathopoulos;Andreas Tsiamis;Themis Prodromakis","doi":"10.1109/TED.2025.3539256","DOIUrl":"https://doi.org/10.1109/TED.2025.3539256","url":null,"abstract":"Here, we report the detailed fabrication and electrical analysis of atomic layer deposited single (i.e., HfO2) and bilayer (i.e., HfO2/Ta2O5)-based memristive devices. The bilayer devices show stable retention properties <inline-formula> <tex-math>$gt 10^{{3}}$ </tex-math></inline-formula> s with an improved <sc>on</small>/<sc>off</small> ratio. Moreover, the bilayer devices also exhibit higher change in the device resistance (25%–30%) as compared to resistance change (~12%) in single-layer devices under the same electrical programming scheme. The least values of coefficient of variability (<inline-formula> <tex-math>${C} _{text {V}}$ </tex-math></inline-formula>) in cycle-to-cycle (C2C) in the device resistance states are 0.19% low-resistance state (LRS) and 0.28% high-resistance state (HRS) for single-layer device, while in the case of bilayer devices, these values are 1.10% (LRS) and 0.29% (HRS). Furthermore, the impedance spectroscopy (EIS) analysis reveals that the switching mechanism is more dominant due to the change in the device resistance rather than the device capacitance. Therefore, this work opens a new way to further explore the ac analysis of memristive devices and their potential applications in various fields.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1780-1787"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Benchmarks for SPICE Modeling and Parameter Extraction Based on AI/ML","authors":"Colin C. McAndrew;Andries J. Scholten;Kiran K. Gullapalli;Yogesh Chauhan;Kejun Xia","doi":"10.1109/TED.2025.3537952","DOIUrl":"https://doi.org/10.1109/TED.2025.3537952","url":null,"abstract":"Over the past decades, the number of submitted articles that use numerical approaches for SPICE models or for characterization (extraction) of parameters of existing SPICE models has grown significantly. Many of those articles rely on synthetic data, generated either from technology computer-aided design (TCAD) or from physical SPICE model simulations; most do not model/fit measured data. Furthermore, those articles do not evaluate the physical correctness, smoothness/monotonicity, or asymptotic correctness of the approach they propose. That is sufficient for initial evaluation of proposed techniques. However, it does not prove that they are “industrial strength.” This article presents benchmarks/guidelines for the proposed artificial intelligence (AI)/machine learning (ML) SPICE modeling and characterization techniques to try to help them become practical and useful.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1551-1559"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward Understanding the Positive Shift of Reverse Turn-on Voltage in the Third Quadrant Operation in Planar SiC Power MOSFETs After Avalanche Breakdown","authors":"Wei-Cheng Lin;Yu-Sheng Hsiao;Chen Sung;Chu Thị Bích Ngọc;Rustam Kumar;Pei-Jie Chang;Surya Elangovan;Sheng-Shiuan Yeh;Chia-Lung Hung;Yi-Kai Hsiao;Hao-Chung Kuo;Chang-Ching Tu;Tian-Li Wu","doi":"10.1109/TED.2025.3536447","DOIUrl":"https://doi.org/10.1109/TED.2025.3536447","url":null,"abstract":"In this study, we explore the stability of third-quadrant characteristics in planar SiC power MOSFETs under high drain bias above the avalanche breakdown condition. By using experimental measurements and TCAD simulations, we analyze the mechanisms responsible for the positive shift of reverse turn-on voltage (<inline-formula> <tex-math>${V}_{text {rev}, text {on}}$ </tex-math></inline-formula>) during the third-quadrant operation. When the drain bias is increased from 1500 to 1620 V, obvious negative shifts in threshold voltage (<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>) and positive shifts in <inline-formula> <tex-math>${V}_{text {rev}, text {on}}$ </tex-math></inline-formula> are observed. The TCAD simulations attribute these shifts to the impact ionization caused by the high electric field inside the p-well regions. Furthermore, with the inclusion of positive fixed charges as the hole traps in the gate oxide near the SiO2/SiC interface, the simulation results show positive shifts of <inline-formula> <tex-math>${V}_{text {rev}, text {on}}$ </tex-math></inline-formula> consistent with the experimental results. These findings suggest that hole trapping caused by high drain bias above the avalanche breakdown condition can affect the stability of third-quadrant operation in planar SiC power MOSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1270-1275"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143519865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physics-Based Compact Modeling of Quantum Confinement and Quasi-Ballistic Transport in Ultra-Scaled GAAFETs","authors":"Yusi Zhao;Zhongshan Xu;Rongzheng Ding;Huawei Tang;Shaofeng Yu","doi":"10.1109/TED.2025.3537585","DOIUrl":"https://doi.org/10.1109/TED.2025.3537585","url":null,"abstract":"A physics-based compact model is developed for ultra-scaled gate-all-around field-effect transistors (GAAFETs), addressing increasingly prominent physical effects: quantum confinement, quasi-ballistic transport, and short channel effects (SCEs). The model employs approximate analytical solutions to the fundamental physical equations, mimicking true device physics while maintaining computational efficiency. In addition to predicting terminal characteristics, it accurately computes subband energies, quantum centroid, quasi-ballistic transmission coefficient, and electrostatic scaling length. Through these internal physical quantities, the model serves not merely as a concise representation of device behaviors but also reveals fundamental physical insights. The model’s verified consistency with TCAD simulations and experimental data confirms its accuracy across a wide range of bias conditions and GAAFET dimensions, while also highlighting the physical mechanisms captured by the model for leading-edge technology nodes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1560-1568"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of High-Performance Dual-Channel-Layered InGaZnO Thin-Film Transistors With Different Indium Contents","authors":"Muhpul Alip;Ablat Abliz;Da Wan","doi":"10.1109/TED.2025.3538524","DOIUrl":"https://doi.org/10.1109/TED.2025.3538524","url":null,"abstract":"In this study, dual-channel-layered amorphous indium gallium zinc oxide (a-IGZO) based thin-film transistors (TFTs) with different In contents were fabricated using the RF magnetron sputtering technique to improve the performance and stability of single-layer a-IGZO TFTs. The optimum electrical performance of the dual-channel layered a-IGZO (2:1:1)/a-IGZO (1:1:1) TFT was obtained at a low <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> of 0.5 V, <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$1times 10^{{8}}$ </tex-math></inline-formula>, low subthreshold swing (SS) of 0.35 V/decade, high <inline-formula> <tex-math>$mu _{text {FE}}$ </tex-math></inline-formula> of 40.5 cm2/Vs, and best stability with small <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> shifts (1.4 and −1.2 V) under positive gate bias stress (PBS) and negative gate bias stress (NBS) test. This performance improvement, attributed to electron transfer from the a-IGZO (2:1:1) layer to the a-IGZO (1:1:1) layer, resulted in the accumulation of free carriers near at a-IGZO (2:1:1) and a-IGZO (1:1:1) interface. Thus, the charges were mainly concentrated within the barrier at the interface, improving performance (controlling <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${N}_{e}$ </tex-math></inline-formula>), while maintaining high <inline-formula> <tex-math>$mu _{text {FE}}$ </tex-math></inline-formula> in a-IGZO (2:1:1)/a-IGZO (1:1:1) TFTs. In addition, the oxygen interstitial defects (Oi) of a-IGZO TFTs were calculated, and the inherent mechanism of stability improvement was examined. The degradation caused by Oi increased with increasing In content in a-IGZO TFTs. Further analysis showed that dual-channel layered a-IGZO (2:1:1)/a-IGZO (1:1:1) TFTs significantly reduced Oi and suppressed electron capture at the interface, resulting in enhanced device stability. Overall, the findings of this study are valuable for the advancement of dual-channel-layered a-IGZO TFTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1802-1808"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Boosting Performance of AlGaN-Based Ultraviolet-C Light-Emitting Diodes via High-Quality AlN Template","authors":"Xu Liu;Shengjun Zhou;Zhenxing Lv;Bin Tang;Hansong Geng;Zhefu Liao;Jingjing Jiang;Ziqi Zhang;Shengli Qi;Sheng Liu","doi":"10.1109/TED.2025.3538815","DOIUrl":"https://doi.org/10.1109/TED.2025.3538815","url":null,"abstract":"Ultraviolet-C light-emitting diodes (UVC LEDs) have exhibited promising future on the pursuit of sustainable and environmental-friendly germicidal irradiation source for the next generation. Nevertheless, owing to the large lattice mismatch between the AlN buffer template and sapphire substrate, the current AlGaN-based UVC LEDs are subjected to severe compressive strain and high dislocation density. Here we propose a paradigm to achieve high-quality AlN buffer template via the nucleation layer (NL) modification, growth mode regulation, and indium (In) doping modulation. Consequently, a defect-reduced, strain-controlled, and atomically flatten AlN film is achieved on the flat sapphire substrate (FSS). Furthermore, a remarkable enhancement on electroluminescence performance was observed in our UVC LED via using the proposed AlN buffer template. It is noted that our UVC LED presents a remarkable improvement on the external quantum efficiency (EQE), which is almost 90% greater than that of its referred UVC LED grown on the conventional AlN buffer template. Our work is able to supply a new horizon in the development of the excellent UVC light sources for biomedical testing, water/air purification, and another relevant fields.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1833-1838"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}