Localized GaN Cap Etching With Gate-Recessed Structure for Enhanced High-PAE Performance and Trap Analysis in 0.15- μ m AlGaN/GaN HEMTs

Abstract

This article presents a comprehensive study on the impact of gate recessing strategies on the electrical performances and trap dynamics of 0.15- $\mu $ m aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high-electron-mobility transistors (HEMTs) for high power-added efficiency (PAE) applications. By comparing devices with varying recess depths and their standard nonrecessed counterpart, we systematically investigate the trade-offs between device performance and process-induced damage. Device with GaN cap removal achieves a record output current density of 1393 mA/mm and a peak transconductance of 661 mS/mm, with reduced short-channel effects (SCEs) due to an increase in carrier concentration and a higher ${L}_{\text {g}}$ / ${t}_{\text {AlGaN}}$ . Notably, the gate-recessed device obtains an optimal recess depth with a PAE of 81.6% and Pout of 27.1 dBm at 10 GHz. Through stress measurement and RF transconductance analysis, we quantify the current collapse and the spatial distribution of border traps induced by inductively coupled plasma (ICP) etching. The results highlight that localized GaN cap removal offers a damage-mitigated pathway to enhance gate control, while excessive barrier thinning decreases the 2DEG concentration and exacerbates trap formation, leading to performance degradation. This work provides critical insights into optimizing gate-recessed designs for high-frequency power amplifiers by balancing structural benefits and process-induced defects.