Investigation of Nanoscale Bonding-Based Complementary FETs

Abstract

In this article, the nanoscale bonding-based complementary field-effect transistor (B-CFET) is proposed as a high-performance alternative to sequential CFETs (S-CFETs) for next-generation technology nodes. Unlike S-CFETs, which suffer from thermal budget constraints that lead to junction abruptness degradation, B-CFET mitigates these issues by employing low-temperature bonding techniques for CFET integration. This approach enables the use of heterogeneous channel materials and allows independent nMOS/pMOS optimization. To assess its performance feasibility, B-CFET is compared with S-CFET. 3-D TCAD simulations indicate that, when accounting for the junction abruptness degradation of S-CFET’s bottom transistor due to dopant diffusion (assuming an increase of 1 nm per decade), B-CFET achieves an 11.1% improvement in operating frequency at the same leakage power ( ${f}_{\text {ISOLEAK}}\text {)}$ compared to S-CFET. Although additional bonding bump layers extend vertical interconnects or cause misalignment and void formation, potentially increasing external resistance, segmented resistance analysis indicates that these factors have a negligible impact on overall performance. Even under extreme conditions, where the bonding resistance increases significantly from 17.5 to $60.7~\Omega $ (a 247% increase), B-CFET exhibits excellent robustness, with only a 1.0% degradation in ${f}_{\text {ISOLEAK}}$ . This minimal degradation highlights the negligible influence of ( ${R}_{\text {BUMP}}\text {)}$ on overall performance and reinforces its potential as a scalable and resilient architecture for future CFET technologies.