Operation Voltage Reduction of Silicon Based Light Sources by Surface Texturing

Silicon-rich oxide (SRO) light-emitting capacitors (LECs) have proven to be good candidates to be monolithically integrated in electrophotonic (Eph) circuits due to their complementary metal-oxide–semiconductor (CMOS) fabrication compatibility and broadband emission spectra. However, their relatively high operating voltage (i.e., the voltage required to emit detectable light) limits their use in applications where portability and low energy consumption are imperative. Among the strategies to overcome this problem, the interlayering of SRO films with different electrical and light-emitting properties has been explored besides the use of metal-assisted chemical etching (MACE)-textured Si substrates to improve carrier injection into the active material. In this study, a combination of both the strategies is analyzed by fabricating LECs featuring SRO multilayer (ML) structures on top of Si textured substrates to reduce the operating voltage of the LECs even farther. The textured Si surfaces were studied to determine an improved arrangement of different SRO layers to ensure complete coverage of Si peaks formed during texturing of the substrate. For comparison, the same LEC structures were fabricated on polished substrates showing an increased operating voltage of around ${V} _{\text {op}} =50$ V in contrast to the new proposed LECs, which presented light emission at only ${V} _{\text {op}} =15$ V. These results open promising application opportunities to monolithically integrate Si-based light emitters in photonic and electronic devices and circuits.