Modeling the Parasitic Capacitance of Nanosheet FETs With Backside Power Delivery Network

This article presents a parasitic capacitance model for gate-all-around (GAA) nanosheet FETs (NsFETs) with backside power delivery network (BSPDN) including three types of techniques buried power rail (BPR), through Silicon Via in MOL (TSVM), and backside contact (BSC). Based on the electrical field analysis and elliptical integral method, the different parasitic capacitance components are extracted and accurately modeled. In addition, the variation in parasitic capacitance components with the structural parameters is also investigated for design optimization of NsFETs with BSPDN. The extra parasitic capacitance induced by the TSVM, BPR, and BSC accounts for about 19.4%, 14.1%, and 7.4% in the ${C}_{\textit {gs}\_{\textit {para}}}$ (or ${C}_{\textit {gd}\_{\textit {para}}}\text {)}$ , respectively. Furthermore, the proposed models were integrated into a calibrated NsFET model, enabling an analysis of the parasitic capacitance induced by the BSPDN in the MEOL at the prelayout stage. The dynamic performance of the circuits, such as ring oscillators, is evaluated under various geometric parameters. This work provides insight into the design technology co-optimization of BSPDN technology in advanced nodes.