IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"A Signal Integrity (SI)-Driven Comprehensive Framework for High-Speed Interconnect Designs and Evaluations in Advanced System-in-Package (SiP) Systems","authors":"Hyunwoo Kim;Seunghun Ryu;Sanguk Lee;Seonghi Lee;Dongryul Park;Jinwook Lee;Jongwook Kim;Seungyoung Ahn","doi":"10.1109/TCPMT.2026.3688530","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3688530","url":null,"abstract":"Advanced system-in-package (SiP) systems, which integrate multiple chiplets, have recently expanded with regard to their design flexibility by utilizing diverse package platforms and interface technologies, though this has also significantly increased the design space complexity. However, exploring this expanded design space to identify optimal design configurations through traditional methods requires a significant amount of time and incurs a high cost. To address this challenge, this article proposes a signal integrity (SI)-driven comprehensive framework for the design and evaluation of high-speed interconnects in chiplet-based SiP systems. Interconnect design and evaluation comprise the two key stages of the proposed framework. The design stage systematically integrates routability analysis, channel design, and reference plane design to provide package platform-independent design guidelines while ensuring implementation feasibility under high-density routing constraints. The evaluation stage introduces frequency-domain voltage transfer function (VTF)-based SI metrics that efficiently estimate eye aperture and overshoot characteristics without time-consuming time-domain simulations. The proposed metrics are validated across various SiP system configurations, demonstrating strong correlations with eye diagram simulations under different channel locations, structures, and data rates. The integrated framework enables the efficient exploration of complex SiP interconnect design spaces and provides a systematic design methodology for next-generation heterogeneous integration platforms.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1940-1955"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparative Study of DRIE-Based Fabrication Strategies for Silicon-Micromachined Subterahertz Waveguide Components","authors":"Suxian Yu;Xu Tian;Umer Shah;Joachim Oberhammer","doi":"10.1109/TCPMT.2026.3712118","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3712118","url":null,"abstract":"Deep reactive-ion etching (DRIE) is widely used to realize high-aspect-ratio silicon waveguide components for terahertz (THz) and sub-THz applications. However, fabrication-induced variations in the waveguide cavity surface quality and geometry can significantly influence the conductor loss and device performance. At sub-THz frequencies, the electromagnetic (EM) skin depth becomes comparable to the characteristic scale of the surface roughness, while geometrical deviations can alter the EM behavior. In this work, two distinct DRIE-based fabrication strategies—a direct-etching approach and a release-assisted etching approach—are implemented to isolate the fabrication-induced surface morphology from the geometric integrity in silicon-micromachined waveguide cavities, providing insight into DRIE-based micromachining process optimization. Detailed geometrical and surface characterizations using scanning electron microscopy (SEM) and an optical profilometer reveal that the release-assisted etching approach effectively reduces the waveguide sidewall underetch from a maximum of 10.4–<inline-formula> <tex-math>$2.8~mu $ </tex-math></inline-formula>m while introducing increased sidewall surface roughness from 41.4 to 107.0 nm. A 163–183-GHz silicon-micromachined microelectromechanical system (MEMS) waveguide crossover switch is used as the test vehicle for RF characterization. The measurements show that, despite the reduction of the sidewall underetch, the measured isolation remains at a similar level for the two strategies. On the contrary, the increased sidewall roughness is accompanied by an approximately 33% increase in the crossover-state insertion loss (IL). These results indicate that, for the investigated device, surface roughness has a stronger impact on RF performance than sidewall underetch. The findings provide practical fabrication-level guidelines for DRIE process optimization and for the future development of increasingly complex high-frequency silicon-micromachined waveguide devices and microsystems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1956-1966"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11603796","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2026.3719806","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3719806","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"C3-C3"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11670497","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MINNs: MNA-Informed Neural Networks for Fast Transient Simulation of Nonlinear Transmission Lines Subject to Parametric Uncertainty","authors":"Dyuti Basu;Aakanksha Verma;Avirup Dasgupta;Sourajeet Roy","doi":"10.1109/TCPMT.2026.3666902","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3666902","url":null,"abstract":"In this article, a new artificial neural network (ANN) formulation is presented for the transient simulation of nonlinear transmission lines (NLTLs) in the presence of parametric uncertainty. The key attribute of the proposed formulation is that it minimizes a loss function expressed as the sum of the residuals of the modified nodal analysis (MNA) equations and the initial conditions describing NLTLs instead of the classical data-driven loss function. The resultant ANNs are referred to as MNA-informed neural networks (MINNs). MINNs exhibit a completely data-free and highly efficient training, unlike conventional ANNs that are trained on large datasets extracted from time and memory-intensive SPICE simulations of NLTLs. Furthermore, in virtue of its more fundamental MNA-based training, MINNs are more accurate than conventional ANNs when predicting NLTL responses for parameter values lying outside the training range. In this article, additional techniques such as dynamic weighting and multistep multifidelity training are developed to mitigate the inherently slow convergence of MINNs. Overall, MINNs are demonstrated to enable highly accurate and efficient Monte Carlo-driven uncertainty quantification (UQ) of NLTLs that is not possible using conventional ANNs or brute force SPICE simulations.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1789-1803"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Multistage Multisection Microstrip Line-Based 8-Way Wilkinson Power Divider for Wideband Linear Antenna Array Applications","authors":"Thokala Latha;Gopi Ram;G. Arun Kumar;M. Chakravarthy","doi":"10.1109/TCPMT.2026.3682939","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3682939","url":null,"abstract":"This article presents an 8-way three-stage Wilkinson power divider optimized for ultra-wideband (UWB), with emphasis on C- to Ku-band applications. It achieves an amplitude imbalance of ±1 dB and a phase imbalance of ±5°, ensuring uniform power distribution for systems like phased arrays. A three-stage four-section topology enhances bandwidth and maintains high port isolation using resistors. Scattering parameters were optimized using Agilent ADS. The design, implemented on RT Duroid 5880 (10 mil), shows good agreement between simulated and measured results.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1894-1900"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid Package for Millimeter-Wave Heterogeneous Integration Based on Flip-Chip, Embedded Chip Fan-Out and Wire-Bonding Techniques","authors":"Zhiyu Qian;Weiwei Zhou;Haoning Zou;Yongrong Shi","doi":"10.1109/TCPMT.2026.3707195","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3707195","url":null,"abstract":"The hybrid heterogeneous integration scheme for millimeter-wave packages is investigated in this letter utilizing a combination of gold ball flip-chip, embedded chip fan-out, and wire-bonding techniques on a high-resistivity silicon (HRSi)/polyimide (PI) interposer. To validate the proposed architecture, a 1-to-4 power divider (PD) network operating in the 30–40 GHz band is designed and implemented by integrating three 1-to-2 GaAs PD chips. The package design for this hybrid configuration is systematically investigated. Through comprehensive simulation analysis and experimental characterization, the feasibility and effectiveness of this hybrid packaging scheme are demonstrated at millimeter-wave frequencies.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1997-2000"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Benchmarking the Thermal Impact of 2.5-D/3-D Copackaged Optics on Si Photonic Devices","authors":"David Coenen;Herman Oprins;Yoojin Ban;Joris Van Campenhout","doi":"10.1109/TCPMT.2026.3705221","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3705221","url":null,"abstract":"The ever-increasing demand for data and internet usage has put a strain on data center infrastructure. Optical I/O (OIO) promises to meet these demands, but this requires dense (2.5-D or 3-D) electronic-photonic integration and advanced packaging schemes. In this article, a thermal modeling study is presented for two advanced copackaged optics (CPOs) scenarios. First, a 2.5-D OIO case is considered (OIO2.5D), and second, a 3-D OIO case is considered (OIO3D). Computational fluid dynamics (CFD) simulations are carried out to accurately determine the cooling performance of Si <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>channels that act as a liquid-cooled cold plate. A convective heat transfer coefficient (HTC) of <inline-formula> <tex-math>$7cdot 10^{4}$ </tex-math></inline-formula> W/m<inline-formula> <tex-math>${}^{2} cdot $ </tex-math></inline-formula>K is extracted and used as a boundary condition for the thermal simulations. With this heat sink performance, the thermal wall of the system is investigated, and it is found to be very sensitive to the XPU power map: 823 W (CPU) and 1146 W (GPU). The thermal impact of this high-power XPU on the photonic layer is then benchmarked for both OIO2.5D/OIO3D. Thermal finite element simulations reveal strong thermal crosstalk from XPU to photonics: <inline-formula> <tex-math>$Delta T_{OIO2.5D} =10$ </tex-math></inline-formula> K and <inline-formula> <tex-math>$Delta T_{OIO3D} =60$ </tex-math></inline-formula> K, as well as strong thermal gradients <inline-formula> <tex-math>$nabla T_{OIO2.5D} =0.9$ </tex-math></inline-formula> K/mm and 0.03 K/ms, <inline-formula> <tex-math>$nabla T_{OIO3D} =12$ </tex-math></inline-formula> K/mm and 1.78 K/ms. These crosstalk and thermal gradient results are of high importance in photonic and electronic circuit design, as they determine the requirements for the thermal tuning of the ring-based photonic devices.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1735-1741"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Distributional Reinforcement Learning With Information Bottleneck for Uncertainty-Aware DRAM Equalization","authors":"Muhammad Usama;Dong Eui Chang","doi":"10.1109/TCPMT.2026.3674506","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3674506","url":null,"abstract":"Equalizer parameter optimization is critical for signal integrity in high-speed memory systems operating at multi-gigabit data rates. However, existing methods suffer from computationally expensive eye diagram evaluation, optimization of expected rather than worst-case performance, and the absence of uncertainty quantification for deployment decisions. In this paper, we propose a distributional risk-sensitive reinforcement learning framework integrating Information Bottleneck (IB) latent representations with conditional value-at-risk optimization. We introduce rate-distortion optimal signal compression, achieving 51 times speedup over eye diagrams while quantifying epistemic uncertainty through Monte Carlo dropout. Distributional reinforcement learning with quantile regression enables explicit worst-case optimization, while probably approximately correct (PAC)-Bayesian regularization certifies generalization bounds. Experimental validation on 2.4 million waveforms from eight memory units demonstrated mean improvements of 37.1% and 41.5% for four-tap and eight-tap equalizer configurations with worst case guarantees of 33.8% and 38.2%, representing 80.7% and 89.1% improvements over Q-learning baselines. The framework achieved 62.5% high-reliability classification, eliminating manual validation for most configurations. These results suggest the proposed framework provides a practical solution for production-scale equalizer optimization with certified worst-case guarantees.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1912-1929"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the Design Techniques of High-Gain Packaged Printed Circuit Board (PCB)-Based Antennas for Sensing and Internet of Things (IoT) Millimeter-Wave Applications: Challenges and Analysis","authors":"Yazan Al-Alem;Yahia M. M. Antar;Ahmed A. Kishk","doi":"10.1109/TCPMT.2026.3684884","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3684884","url":null,"abstract":"Advanced wireless integrated systems are highly based on printed circuit board (PCB) technology. Thus, antennas should be designed based on the same technology for full and straightforward integration with these systems. On the other hand, antennas with waveguides and metallic feeds are very bulky and hard to integrate with PCB-based solutions, as they require complex transitions that increase the system cost and losses. Therefore, we shed light and review thoroughly the challenges and the main strategies and techniques used to design low-cost, high-gain PCB-based antenna solutions for sensing and the Internet of Things (IoT) millimeter-Wave (mm-Wave) applications. Several crucial techniques to counter the design impairments of PCB antennas at mm-Wave frequencies are discussed, including: 1) the utilization of diffracted fields to increase the main radiating element gain, and reduce the feeding network size; 2) the utilization of microstrip line (MSL) radiation losses to implement high-gain radiating antenna elements; 3) the utilization of high characteristic impedance lines to feed antenna array elements, and to reduce the radiation effects of the feeding network drastically; and 4) the utilization of superstrates and polarizers to enlarge the element spacing in an array configuration and enhance the gain and sidelobe level performance. An elaborate design and analysis example of a packaged printed feed with symmetric radiation characteristics is detailed, capitalizing on the advantages of such a feed as a replacement for horn antennas and open-ended waveguide feeds for lenses and reflectors.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1863-1880"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing Thermal Uniformity in Liquid-Cooled Inverters: Adjoint-Based Optimization of a Manifold Microchannel Coldplate","authors":"Bin He;Gongyue Tang","doi":"10.1109/TCPMT.2026.3670867","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3670867","url":null,"abstract":"Power electronics inverters are a cornerstone of modern electric vehicle systems, where thermal management has emerged as a key barrier to achieving ambitious power density targets. This study addresses the critical issue of thermal nonuniformity in liquid-cooled inverters containing multiple discrete chips by optimizing coolant flow distribution. A cost-effective thermal test vehicle (TTV) was developed, utilizing stacked platinum ceramic heaters to accurately simulate the thermal behavior of a commercial inverter. Initial experiments with a baseline cooling manifold revealed a significant flow imbalance, resulting in chip-to-chip temperature variations of up to <inline-formula> <tex-math>$3.7~^{circ }$ </tex-math></inline-formula>C. An adjoint-based shape optimization methodology was employed to redesign the manifold geometry for superior flow uniformity. Experimental validation of the optimized design, tested across three distinct microchannel configurations, confirmed a substantial improvement in thermal performance. The maximum chip-to-chip temperature difference was reduced to approximately <inline-formula> <tex-math>$1~^{circ }$ </tex-math></inline-formula>C while maintaining high cooling effectiveness and reducing pumping power by 3.4%–9.9%. The optimized system demonstrates a viable and manufacturable path toward high-performance thermal management in compact, power-dense inverter designs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1762-1771"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}