IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献_第9页

Self-Packaged Compact Filter Array: Innovations Based on Modified Substrate Integrated Suspension Line Technology 自封装紧凑型滤波器阵列：基于改进基板集成悬浮线技术的创新

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-24 DOI: 10.1109/TCPMT.2025.3554181

Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef

{"title":"Self-Packaged Compact Filter Array: Innovations Based on Modified Substrate Integrated Suspension Line Technology","authors":"Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef","doi":"10.1109/TCPMT.2025.3554181","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3554181","url":null,"abstract":"This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1025-1031"},"PeriodicalIF":2.3,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration 基于多物理场的机器学习辅助芯片布局异构集成

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-24 DOI: 10.1109/TCPMT.2025.3553840

Vinicius C. Do Nascimento;Seunghyun Hwang;Michael Joseph Smith;Tejas Kulkarni;Qiang Qiu;Cheng-Kok Koh;Ganesh Subbarayan;Dan Jiao

{"title":"Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration","authors":"Vinicius C. Do Nascimento;Seunghyun Hwang;Michael Joseph Smith;Tejas Kulkarni;Qiang Qiu;Cheng-Kok Koh;Ganesh Subbarayan;Dan Jiao","doi":"10.1109/TCPMT.2025.3553840","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553840","url":null,"abstract":"The floorplan of chiplets in heterogeneously integrated systems-in-package (SiPs) must consider multiphysics (electrical, thermal, and mechanical) performance and meet positional constraints during optimization. This article sets forth an efficient framework for chiplet floorplanning subject to positional and multiphysics-performance-based constraints. Traditional multiphysics simulations, often impractical in optimization due to high computational cost, are replaced by a high-fidelity and efficient conditional image generative model via image-based machine learning (ML). This model is accurate and capable of performing real-time prediction of multiphysics performance throughout 3-D SiPs. Utilizing the image-based ML model for fast performance assessment, we further accelerate the physical design by developing a novel and highly parallelizable dynamic rank-revealing (RR) algorithm for solving the underlying constrained optimization problem. We leverage this algorithm to optimize the position of the chiplets subject to multiphysics performance directly without floorplan representation or convexification techniques while meeting a multitude of constraints. The same ML model and constraints are also integrated into a state-of-the-art corner block list (CBL) floorplan representation under a simulated annealing (SA) optimization framework. The accuracy and efficiency of the proposed optimization method are demonstrated in the floorplanning of chiplets on an interposer subject to thermal constraints, and by comparisons against ML-assisted SA-CBL for performing the same task.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"959-973"},"PeriodicalIF":2.3,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE元件、封装与制造技术资讯汇刊

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-20 DOI: 10.1109/TCPMT.2025.3546007

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-20 DOI: 10.1109/TCPMT.2025.3546009

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information IEEE元件、包装与制造技术汇刊信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-20 DOI: 10.1109/TCPMT.2025.3546005

引用次数: 0

Fast Heatsink Topology Optimization for RF Power Amplifier Chip Heat Dissipation Enhancement 射频功率放大器芯片散热增强的快速散热器拓扑优化

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-20 DOI: 10.1109/TCPMT.2025.3553317

Huazhi Xiang;Jialong Fu;Yaocheng Shang;Daniele Inserra;Rui Guo;Guangjun Wen

{"title":"Fast Heatsink Topology Optimization for RF Power Amplifier Chip Heat Dissipation Enhancement","authors":"Huazhi Xiang;Jialong Fu;Yaocheng Shang;Daniele Inserra;Rui Guo;Guangjun Wen","doi":"10.1109/TCPMT.2025.3553317","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553317","url":null,"abstract":"This article proposes a fast topology optimization algorithm methodology for the design of heatsinks for RF power amplifier circuits based on a thermal resistance network model. This methodology can achieve heatsinks lightweight design while keeping the temperature within an allowable range. The solid isotropic materials with punishments (SIMPs) method is applied within the design area of the heatsink, while the impact of the RF power amplifier circuit on heat dissipation is represented by a thermal resistance network model. The main advantage of this methodology is that it avoids the use of conventionally employed finite element method (FEM) thermal simulation of the whole chip/heat dissipation structure, which requires very long simulation time and high computational effort. On the contrary, the thermal resistance network calculation method offers a very fast and sufficiently accurate temperature distribution analysis tool, speeding up the heatsink structure design when employed within the optimization routine. Compared with a traditional heatsink, the volume (mass) of the heatsink optimized through the aforementioned method has been reduced of more than 20% while satisfying the highest temperature requirements.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1953-1963"},"PeriodicalIF":3.0,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Signal Integrity Analysis of Tapered Through Packaging Multibit Glass Vias Using Exponential Matrix–Rational Approximation Technique 用指数矩阵-有理逼近技术分析锥形通孔封装多比特玻璃通孔的信号完整性

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-20 DOI: 10.1109/TCPMT.2025.3553362

Ajay Kumar;Rohit Dhiman

{"title":"Signal Integrity Analysis of Tapered Through Packaging Multibit Glass Vias Using Exponential Matrix–Rational Approximation Technique","authors":"Ajay Kumar;Rohit Dhiman","doi":"10.1109/TCPMT.2025.3553362","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553362","url":null,"abstract":"In this article, we develop a wideband scalable analytical model of tapered through packaging differential multibit vias (TP-DMVs) with pads in glass interposer by developing an exponential matrix-rational approximation (EM-RA) technique. An electrical <italic>RLGC</i> model, which also includes the skin effect, is proposed as a function of geometric parameters of tapered through glass vias. The scalability of <italic>RLGC</i> equivalent circuit is verified in terms of <italic>S</i>-parameters against the 3-D electromagnetic (EM) high-frequency structure simulator (HFSS) up to 100 GHz, for a wide variety of tapered TP-DMV dimensions, including the effects of slope angle and aspect ratio. The maximum reduction in capacitance and conductance values of tapered TP-DMVs with a slope angle is ~75%, while the maximum increase in resistance and inductance value is ~93%. The signal integrity parameters, such as crosstalk, time to reach peak crosstalk, and propagation delay under the influence of surface roughness (SR) and temperature variations, are computed using the EM-RA technique and industry-level simulator SPICE. The variations include temperature and glass SR ranges from (300–500 K) and (150–<inline-formula> <tex-math>$1.5~mu $ </tex-math></inline-formula>m). The comparison shows excellent conformity with less than 1% error. Through the proposed EM-RA technique and Nyquist stability criterion, it is shown that, by increasing the slope angle and pitch, the tapered TP-DMVs become relatively more stable.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1014-1024"},"PeriodicalIF":2.3,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143927360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 3-D Phased Array Transmitter With Circuit and Package Codesign of a Phase Shifter and a Power Amplifier at W Band W波段移相器和功率放大器电路和封装协同设计的三维相控阵发射机

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-20 DOI: 10.1109/TCPMT.2025.3553253

Zhe Zhao;Dong-Xin Ni;Wang-Wen Xu;Yin-Shan Huang;Cheng-Rui Zhang;Liang Zhou

{"title":"A 3-D Phased Array Transmitter With Circuit and Package Codesign of a Phase Shifter and a Power Amplifier at W Band","authors":"Zhe Zhao;Dong-Xin Ni;Wang-Wen Xu;Yin-Shan Huang;Cheng-Rui Zhang;Liang Zhou","doi":"10.1109/TCPMT.2025.3553253","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553253","url":null,"abstract":"This study proposes the design, fabrication, and testing of a 3-D integrated transmitter operating at the W band. Detailed analyses of the performance variations before and after packaging of the phase shifter (PS) and power amplifier (PA) are provided, along with specific design processes. The circuit and packaging of the PS and PA are codesigned to maintain their performance and minimize proximity effects during 3-D integration at millimeter-wave frequencies. The PS achieves a −6.4-dB loss at 100GHz, with a phase root mean square (rms) error of 1.11° and a gain rms error of 0.855dB. The PA achieves a maximum gain of 19.5dB at 103GHz, with a bandwidth from 99.2 to 106.7GHz and a saturated output power of 13dBm. Both the PS and PA are individually packaged using proprietary silicon-based micro-electro-mechanical system (MEMS) through-silicon-trench technology and multilayer photosensitive composite film. Finally, a 3-D integration of the transmitter system is realized using microbumps based on 3-D transition structures.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1060-1071"},"PeriodicalIF":2.3,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Simplified Radiation Model for Amplitude-Only Near-Field Reconstruction of Multiple Sources on Package Interconnects 封装互连多源仅幅近场重建的简化辐射模型

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-19 DOI: 10.1109/TCPMT.2025.3553054

Wei-Jen Chen;Wei-Kai Chen;Ming-Chung Huang;Ruey-Beei Wu

{"title":"A Simplified Radiation Model for Amplitude-Only Near-Field Reconstruction of Multiple Sources on Package Interconnects","authors":"Wei-Jen Chen;Wei-Kai Chen;Ming-Chung Huang;Ruey-Beei Wu","doi":"10.1109/TCPMT.2025.3553054","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553054","url":null,"abstract":"This study proposes a novel modal decomposition method to allow reconstructing principal components of radiation sources in multi-interconnect systems from the amplitude-only near magnetic field measurement. Singular value decomposition (SVD) is used to express any radiation field as a linear combination of modes of multiple coupled interconnects. The same method is used for arbitrary dipole distribution. A suitable noise model is determined using only a few principal modes, rather than a large quantity of dipoles. For amplitude-only field data, the dipole model is solved by determining the coefficients of modes using a pattern search optimization, which is a relatively simple and time-saving algorithm. The proposed method is validated using a numerical example of multi-interconnect radiation. The field that is reconstructed using the proposed model exhibits a high degree of consistency with the actual spatial fields in terms of field amplitude and phase. Thence, the de-sense issues of the multi-interconnect systems can be effectively determined by the superposition of the effects from a few principal modes.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1044-1051"},"PeriodicalIF":2.3,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Out-of-Plane Optical Coupling to Photonic Integrated Circuits Using Turning-Mirror Lens Arrays 利用转镜透镜阵列实现光子集成电路的面外光耦合

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-19 DOI: 10.1109/TCPMT.2025.3552840

Kamil Gradkowski;Peter O'Brien

引用次数: 0