IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Hybrid Stripline Guiding Structure Integrating Dual Right-Angle Coaxial Transitions for Wideband Crossover Implementation","authors":"Mohamed Mamdouh M. Ali;Larbi Talbi;Khelifa Hettak;Ke Wu","doi":"10.1109/TCPMT.2026.3704889","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3704889","url":null,"abstract":"As 6G networks transition toward centimeter-wave (cmWave) frequencies, signal routing components with ultrawide bandwidth and high isolation have become critical bottlenecks for next-generation system performance. This article presents a hybrid printed circuit board (PCB)–computer numerical control (CNC) asymmetric stripline architecture that establishes a new performance standard with a 200% fractional bandwidth (0–20 GHz). The design utilizes a dual-transition system featuring specialized top and bottom right-angle coaxial transitions that are specifically designed to overcome the inherent challenges of asymmetrical guiding structures. While wideband characteristics are more easily achieved in end-launch configurations, this work achieves a 20:1 bandwidth ratio through a right-angle-based transition, which is technically significant due to the complex compensation required for 90° signal turns. Experimental validation of the standalone transitions demonstrates a 20:1 bandwidth ratio with a −15-dB matching level and a low insertion loss of 0.25 dB/in. As a core application, a wideband crossover prototype is demonstrated, leveraging these transitions to achieve a 3:1 bandwidth (7–21 GHz) with a −20-dB matching level, 0.5-dB insertion loss, and a high isolation of 70 dB. Unlike conventional planar crossovers that suffer from parasitic coupling and phase imbalance, this hybrid approach ensures mechanical stability and phase integrity, providing a high-performance solution for 6G beam-scanning feeding networks. The results provide a validated framework for scalable and manufacturable signal routing, outperforming existing state-of-the-art methodologies in both bandwidth and isolation.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1844-1862"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Wafer Warpage Prediction Method Considering Characteristics of Back-End-of-Line Layers and Nonlinear Stress–Strain Relation of Cu Under Large Temperature Variations","authors":"Chong Ma;Hongli Liu;Fei Qin;Yanwei Dai","doi":"10.1109/TCPMT.2025.3645192","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3645192","url":null,"abstract":"For the challenges and difficulties of warpage prediction brought by complex and cross-scale back-end-of-line (BEOL) layers, as well as nonlinear stress–strain relations of Cu, this article proposes new representative volume element (RVE) models considering complex BEOL layers and different mechanical behaviors of Cu. It creates the corresponding wafer model with equivalent BEOL layers to predict the warpage evolution during thermal cycling. Three RVE models with different geometric fineness and three RVE models with elastic, temperature-dependent, and plastic behaviors of Cu are discussed in view of the applicability of the equivalent model. To verify the validity of equivalent models, the warpage during thermal cycling is measured and compared with the simulated warpage. It can be known from the results of the comparative analysis that the wafer model considering plastic Cu can accurately predict wafer warpage and characterize the influence of plastic behavior of Cu on warpage during thermal cycling. At <inline-formula> <tex-math>$30~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$380~^{circ }$ </tex-math></inline-formula>C, the predicted warpage of the wafer model considering plastic Cu is +193 and <inline-formula> <tex-math>$- 148~mu $ </tex-math></inline-formula>m, respectively, which has only less than 1% deviation compared with the measured warpage. In conclusion, this research provides a novel insight into solving the problem of wafer warpage prediction caused by complex structures such as BEOL and redistribution layer (RDL).","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1772-1780"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine Learning Predictive Modeling and Multiobjective Optimization of 2.3-D Chip-Last Fan-Out Wafer-Level Packages","authors":"Mohammad Rafiee;Hao Liu;Zhongtian Xia","doi":"10.1109/TCPMT.2026.3663333","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3663333","url":null,"abstract":"This article presents a surrogate-driven, multiobjective co-design methodology combined with multicriteria decision-making for 2.3-D chip-last (redistribution layer (RDL)-first) fan-out wafer-level packaging (FOWLP). A 500-point finite-element dataset spanning discrete materials and geometries is used to learn random forest (RF) and extreme gradient boosting (XGBoost) surrogates for four objectives: junction-to-ambient thermal resistance (<inline-formula> <tex-math>$Theta _{mathrm {JA}}$ </tex-math></inline-formula>) and volume-averaged strain-energy density at the flip-chip bump, C4, and BGA (<inline-formula> <tex-math>$Delta W_{mathrm {bump}},Delta W_{C4},~text {and}~Delta W_{mathrm {BGA}}$ </tex-math></inline-formula>). The surrogates guide Nondominated Sorting Genetic Algorithm II (NSGA-II) exploration; RadViz provides a compact four-objective view; a NetFlow-based decision step selects a balanced design. Feature-importance analyses agree across models and match packaging physics. <inline-formula> <tex-math>$Theta _{mathrm {JA}}$ </tex-math></inline-formula> is governed primarily by the mold path—mold thermal conductivity and mold cap thickness—followed by heatsink and TIM resistances; board-downward terms are secondary. Reliability metrics are controlled by levers local to each tier: silicon thickness and underfill CTEs near the die/interposer region, and BGA alloy with board/package CTEs at the board interface. A cooperative trend is observed for die thickness: within the explored range, thinning the die reduces <inline-formula> <tex-math>$Delta W$ </tex-math></inline-formula> near the die side without materially degrading <inline-formula> <tex-math>$Theta _{mathrm {JA}}$ </tex-math></inline-formula> in a mold-dominated stack. Pareto sets and their RadViz embeddings reveal broad regions of low <inline-formula> <tex-math>$Theta _{mathrm {JA}}$ </tex-math></inline-formula> coexisting with acceptable <inline-formula> <tex-math>$Delta W$ </tex-math></inline-formula>, from which a reliability-first champion is selected. The framework yields interpretable tradeoffs and accelerates search for manufacturable 2.3-D FOWLP configurations while reducing the reliance on exhaustive finite-element analysis (FEA) sweeps.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1804-1813"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Influencing Factors of Electromigration in TSV-RDL Interconnect Structures","authors":"Xiaoting Chen;Xiangjun Lu;Xiaodong Jian;Bin Zhou;An Xie","doi":"10.1109/TCPMT.2025.3648743","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3648743","url":null,"abstract":"In 3-D packaging architectures, the through-silicon via-redistributed layer (TSV-RDL) interconnect structure serves as the critical conductive pathway and is continuously subjected to combined thermoelectric coupling loads, making it a vulnerable zone for electromigration failures. This research adopts a multidimensional methodology to analyze the influencing factors of electromigration in TSV-RDL. First, the study designs electromigration acceleration experiments based on the dual factors of temperature and current density to establish the time-varying resistance characteristic curves of the TSV-RDL. Second, scanning electron microscopy is employed to characterize the failure interfaces and to analyze the morphological differences between thermally dominant and electrically dominant failure modes. Finally, a thermal–electrical–mechanical multiphysics coupling model is constructed using the ANSYS Workbench platform. In conclusion, the study unequivocally demonstrates that the failure mechanisms in TSV-RDL structures are governed by two distinct regimes, dictated by the dominant driving force. The invariant locations of current crowding and stress concentration serve as inherent weaknesses of the structure. Crucially, the research establishes that the current density-dominated regime leads to gradual, predictable degradation, whereas the temperature-dominated regime triggers rapid, catastrophic failure. These findings provide a critical foundation for designing reliable 3-D integrations. By actively controlling the operational regime to favor current density dominance, designers can significantly extend the interconnect lifespan. Furthermore, the identified failure hotspots offer precise targets for structural reinforcement and reliability monitoring.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1754-1761"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress Analysis and Reliability Investigation of Ultradeep Cu-Filled TSVs for System-in-Package Applications","authors":"J. Zou;L. Liu;W. Xie;X. Li;X. Luo;T. Gong;C. Ma;J. Li","doi":"10.1109/TCPMT.2026.3708099","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3708099","url":null,"abstract":"While fabrication processes for Cu-filled through-silicon vias (TSVs) with depths <inline-formula> <tex-math>$le 200~mu $ </tex-math></inline-formula>m are relatively mature, the complete filling of ultradeep blind TSVs with depths up to <inline-formula> <tex-math>$300~mu $ </tex-math></inline-formula>m remains challenging. In silicon-based embedded fan-out integration technology, constrained by the thickness of heterogeneous chips, the maximum thickness of the embedded silicon interposer can reach <inline-formula> <tex-math>$300~mu $ </tex-math></inline-formula>m, resulting in a corresponding TSV depth of up to <inline-formula> <tex-math>$300~mu $ </tex-math></inline-formula>m. The fabrication processes and reliability mechanisms of such ultradeep TSVs differ significantly from those of conventional TSVs. In particular, the substantial increase in copper fill volume exacerbates the issues of copper extrusion and thermal stress, which have a more pronounced impact on interconnect reliability. The most direct manifestation of these effects is wafer cracking during back-end-of-line (BEOL) processing. This study successfully demonstrates the fabrication of solid Cu-filled TSVs with dimensions of 300 (depth) <inline-formula> <tex-math>$times 70~mu $ </tex-math></inline-formula>m (diameter) on 4-in silicon wafers. A controlled annealing rate of <inline-formula> <tex-math>$1~^{circ }$ </tex-math></inline-formula>C/min effectively mitigates cracking during back-end processing. Furthermore, in comparison with nonsolid via filling, the crystal structure evolution, residual stress variation, and copper extrusion behavior of TSVs at different annealing temperatures were systematically characterized using techniques such as electron backscatter diffraction (EBSD) and micro-Raman spectroscopy. The underlying mechanisms governing these phenomena were also investigated in depth, providing guiding recommendations for the process development and reliability enhancement of ultradeep and large-diameter TSV structures. The results indicate that the grain evolution in the central region of large-diameter TSVs exhibits a radial gradient due to the weak pinning effect from the sidewalls. The primary cause of copper extrusion is grain growth, and the driving force for grain growth undergoes a stagewise transition with temperature. At approximately <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C, thermal stress relief dominates as the driving force; when the temperature rises to <inline-formula> <tex-math>$300~^{circ }$ </tex-math></inline-formula>C, the minimization of grain boundary energy becomes the predominant driving force.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1729-1734"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bandwidth Enhancement of Low-Profile Glass-Based Substrate Integrated Cavity Antenna-in-Package","authors":"Yin-Shan Huang;Wang-Wen Xu;Shang Zhang;Liang Zhou","doi":"10.1109/TCPMT.2026.3698088","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3698088","url":null,"abstract":"This article proposes a wideband, low-profile, glass-based antenna-in-package (AiP) by loading an asymmetrical artificial magnetic conductor (AMC). A compact substrate integrated cavity (SIC) antenna element with a low profile of <inline-formula> <tex-math>$0.09~lambda _{0}$ </tex-math></inline-formula> is designed by incorporating an AMC structure on the top surface. By employing an asymmetrical AMC, the antenna mode is modified to operate at two different frequencies, thereby extending the impedance bandwidth. Therefore, the antenna’s impedance bandwidth is improved from 13.7% to 20%. A <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> SIC antenna array is also designed, using a two-stage balun based on thin-film benzocyclobutene (BCB) to ensure high boresight gain across different frequency points. The SIC antenna array is fabricated using through-glass via (TGV) technology and a silicon-based micro-electromechanical systems (MEMS) photosensitive composite film. The measured relative impedance bandwidth of the proposed antenna array is 27.9% (83–110 GHz). The measured peak gain reaches 10.2 dBi, with a 3-dB gain bandwidth exceeding 27 GHz. The proposed antenna can be further integrated using 3-D heterogeneous processes with other components to achieve low interconnection loss, thereby enhancing high-frequency performance for future millimeter-wave radar and communication systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1576-1584"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148516795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Coupled Thermal and Mechanical Analysis of Thermal Interface Materials in Electronic Packaging","authors":"Onur Yenigun;Mario Gonzalez;Vladimir Cherman;Melina Lofrano;Yao Yao;Geert Van der Plas;Eric Beyne;Herman Oprins","doi":"10.1109/TCPMT.2025.3633174","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3633174","url":null,"abstract":"Nowadays, the AI<inline-formula> <tex-math>$backslash $ </tex-math></inline-formula>HPC devices are becoming more advanced; therefore, the demand for larger packages is rising. However, increased package sizes are causing larger warpage levels to occur. As a result of larger warpage levels, the effects of warpage on the thermal performance of thermal interface materials (TIMs) inside the packages become more critical. However, current thermal characterization methodologies (e.g., ASTM D5470) use ideal surface conditions during testing and overlook the effects of chip package interactions, such as temperature- and pressure-dependent warpage during operation. Such conditions could deteriorate the contact or coverage of TIMs with the die and the heat spreader/heat sink elements in the package. In addition, the lack of a fully coupled thermal and mechanical analysis of TIMs inside IC packages increases the risk of selecting improper TIMs, which might cause thermal performance issues. To address these problems, we combine in situ thermal characterization of TIMs using packaged thermal test vehicles (TTVs) and fully coupled thermal and mechanical modeling of the package in realistic application conditions. Fully coupled thermal and mechanical modeling includes the assembly-induced warpage, warpage-induced gaps at the TIM cold plate interface, pressure-dependent TIM coverage, and their overall effects on the thermal performance of both the TIM and the packaging. The results of this study show that warpage of the die can play a crucial role in the thermal performance of the package based on the mechanical properties of the TIMs, bond line thickness (BLT), and pressure. Using the coupled thermal and mechanical modeling, the mechanisms behind the nonuniform temperature distributions measured by packaged TTV are explained, as the temperature difference between the center and the corner of the chip can increase up to a factor of 2, caused by warpage-induced gaps. Outcomes of this work can be used as a guideline for selecting proper TIMs for improved thermal management of IC packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1567-1575"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-Packaged Air-Filled Full-Metal Quasi-Lumped Elements Wideband Wilkinson Power Divider","authors":"Ahmed A. Abdel Aziz;Hui-Kun Yang;Jin Xu;Zi-Hao Zhou;Hao Wan;Jia-Hao Zhao","doi":"10.1109/TCPMT.2026.3678970","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3678970","url":null,"abstract":"In this article, broadband self-packaged negative-coupled integrated Wilkinson power dividers (WPDs) using microstructure electrochemical fabrication (MEFAB) process are introduced. Analysis of the performance of WPDs with and without using negative-coupled inductance is conducted. To realize a compact WPD with broadband performance, quasi-lumped elements using negative-coupled inductors and metal–insulator–metal (MIM) capacitances are introduced. Single-stage WPD using a commercial capacitor operates from 3 to 8 GHz with an insertion loss of 0.76 dB, while the MIM-based WPD exhibits an insertion loss of 1 dB over the same band. The amplitude imbalance is within ±0.12 and ±0.21 dB, and the phase imbalance is below 3° and 2°, respectively, across the operating band. Furthermore, to extend the operating bandwidth, a two-stage WPD based on negative-coupled inductors and MIM capacitors is developed. The two-stage WPD covers 2–10.5 GHz with an insertion loss of 0.96 dB, amplitude imbalance within ±0.35 dB, and phase imbalance below 4.1°. All inductors and MIM capacitors are designed and implemented in the MEFAB process, and all the proposed WPDs are showing good agreement between simulated and experimental results.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1619-1626"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalable D-Band Antenna With Coplanar and Stacked Parasitic Elements for Low-Cost Antenna-in-Package","authors":"Yuyan Cao;Dongseop Lee;Sining An;Wonbin Hong;Buon Kiong Lau","doi":"10.1109/TCPMT.2026.3681875","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3681875","url":null,"abstract":"The unquenchable thirst for bandwidth to support next-generation wireless systems is increasingly bringing D-band into the spotlight. This work proposes a scalable D-band patch antenna that features both coplanar and stacked parasitic patch structures. By leveraging interpatch coupling, different coplanar parasitic elements are excited across different frequency bands, enabling multimode operation and, thus, a wideband response. To mitigate gain fluctuations caused by modal discontinuities, stacked parasitic patches are added and progressively shifted inward to improve the continuity and consistency of modal patterns by suppressing the undesired currents and, hence, aligning the modal patterns. The resulting antenna element achieves a flat gain of up to 10 dBi over a 28% impedance bandwidth in simulation. To demonstrate the scalability of the design, a <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> array with a hybrid feed network was fabricated with a high-density interconnect (HDI) PCB process featuring one buildup layer on each side of a two-layer core. The array prototype yields an impedance bandwidth of 29%, a peak gain of 12.3 dB, and a gain bandwidth of 17.8%. These results highlight the strong potential of low-cost HDI-based antenna fabrication for D-band applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1652-1662"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic Current Sharing Analysis and Optimization for SiC Power Modules Considering Commutation Current and Kelvin-Source Circulating Current","authors":"Zicong Li;Yifei Luo;Xin Li;Fei Xiao","doi":"10.1109/TCPMT.2026.3669393","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3669393","url":null,"abstract":"Layout-dominated dynamic current imbalance of paralleled silicon carbide (SiC) MOSFETs results in uneven losses, limiting the available capacity. In this article, an analysis that considers the commutation current from the complementary switch is performed, and a more accurate coupling parasitic circuit model that considers the Kelvin-source circulating current is applied to analyze the current sharing and guide optimizations. The superiority of the proposed model is discussed and verified by mathematical derivations, coupling inductance extractions, and current simulations. The newly defined equivalent inductance coefficients (EICs) and current sharing influence coefficients (ICs) are proposed to perform dynamic current analysis and bonding points optimization. The effectiveness of the optimization is verified by experiments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1585-1598"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148516796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}