IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Fusion Neural Networks for High-Precision Design and Ultrawideband Shielding in Frequency Selective Surfaces","authors":"S. D. Sairam;D. Sriram Kumar","doi":"10.1109/TCPMT.2024.3517666","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3517666","url":null,"abstract":"This article advances a multi-input multi-output regression approach for continually optimizing the physical design of frequency selective surfaces (FSSs) to enhance shielding effectiveness (SE) over an ultrawide bandwidth. The classical models of neural networks (NNs) are frequently used for such regression tasks due to their capacity to extract features from average datasets; however, they struggle with complex design parameters and broad responses. To accomplish this, a hybrid NN technique is developed, which combines convolutional neural networks (CNNs) for deep feature capture with long short-term memory (LSTM) networks and an attention mechanism for processing. This method makes efficient use of linear information in design dimensions while also consistently computing S-parameters. The FSS design employs a double square loop that resonates at two frequencies, resulting in a wideband response; by adding four stubs between the loops, it becomes an ultrawideband (UWB) response. The equivalent lumped circuit (ELC) model is applied for estimating capacitance (C) and inductance (L), which are then transformed to ABCD and S-parameters. The model obtained an <inline-formula> <tex-math>$r^{2}$ </tex-math></inline-formula> value of 99.3% and a mean squared error (mse) of <inline-formula> <tex-math>$1 times 10^{-3}$ </tex-math></inline-formula> after optimizing the design parameters in 124.25 s. The design, implemented on Rogers 5880LZ with a thickness of 1.27 mm and unit-cell dimensions of <inline-formula> <tex-math>$11 times 11$ </tex-math></inline-formula> mm, is stable across varied incidence angles and polarization insensitive, allowing for downsizing. Comparative research demonstrates that the CNN-LSTM hybrid model surpasses traditional techniques, illustrating higher SE.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"810-820"},"PeriodicalIF":2.3,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Millimeter-Wave Multilayer Ultrawideband Common-Mode Filters Using Defected Ground Structure","authors":"Yijun Weng;Wenjie Feng;Yongrong Shi;Guangxu Shen;Yunfei Cao;Yixi Tang;Haoshen Zhu;Lin-Sheng Wu;Wenquan Che;Quan Xue","doi":"10.1109/TCPMT.2024.3517734","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3517734","url":null,"abstract":"This article proposes two innovative millimeter-wave multilayer ultrawideband common-mode filters (CMFs). Microstrip lines and striplines are employed in CMFs to accomplish more comprehensive research. Common-mode (CM) suppression can be substantially strengthened by introducing a sandwich-like stack-up structure. The equivalent circuits expressed by the transmission line model are provided and analyzed. Analysis of electric/magnetic field is also given. For the proposed microstrip line CMF, a 13.04-GHz wide stopband response covering 17.91–30.95 GHz can be obtained. For the proposed stripline CMF, the 10-dB bandwidth can reach up to 20.12 GHz (17.39–37.51 GHz). Moreover, the differential-mode (DM) insertion loss of CMFs within 40 GHz is less than 3 dB. The proposed CMFs exhibit excellent DM matching level, ultrawide CM stopband bandwidth, low mode conversion level, and compact size.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"800-809"},"PeriodicalIF":2.3,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward TSV-Compatible Microfluidic Cooling for 3D ICs","authors":"Geyu Yan;Euichul Chung;Erik Masselink;Shane Oh;Muneeb Zia;Bharath Ramakrishnan;Vaidehi Oruganti;Husam Alissa;Christian Belady;Yunhyeok Im;Yogendra Joshi;Muhannad S. Bakir","doi":"10.1109/TCPMT.2024.3516653","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3516653","url":null,"abstract":"Cooling presents a significant challenge for high-performance 3-D integrated circuits (3D ICs). To this end, this research explores through-silicon via (TSV)-compatible micropin-fin heat sink (MPFHS) for high-power 3-D chip stacks. Copper TSVs with a diameter of <inline-formula> <tex-math>$5.2~mu $ </tex-math></inline-formula>m and a high aspect ratio (HAR) of 29:1 are developed. An extensive experimental and computational investigation of the MPFHS under varying flow rates and power conditions was conducted, showing that the MPFHS maintains an average chip temperature below <inline-formula> <tex-math>$72~^{circ }$ </tex-math></inline-formula>C, even with a total power dissipation of 500 W and a power density of 312 W/cm2 at a flow rate of 117 mL/min. The minimum total thermal resistance achieved was <inline-formula> <tex-math>$0.286~^{circ }$ </tex-math></inline-formula>C<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/W.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"104-112"},"PeriodicalIF":2.3,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Less Is More: Non-TIM Air-Cooled Ceramic Packaging for SiC Power Modules to Extend Thermal Performance and Mechanical Reliability Boundaries","authors":"Zhaobo Zhang;Xibo Yuan;Wenzhi Zhou;Mudan Chen;Elaheh Arjmand;Bohao Zhang;Wenbo Wang","doi":"10.1109/TCPMT.2024.3513944","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3513944","url":null,"abstract":"Power module packaging remains one of the constraints preventing silicon carbide (SiC) devices from realizing high power density and optimal reliability in converters. This article proposes a non-thermal interface material (TIM) air-cooled power module architecture, i.e., chip-on-heatsink, to enhance both thermal performance and structural reliability. The chip-on-heatsink packaging bonds conductive copper traces and an aluminum nitride (AlN) ceramic heatsink together without requiring TIM. This non-TIM packaging design streamlines the manufacturing process by eliminating certain steps, such as attaching the bottom copper layer on substrates and assembling heatsinks, since there are few layer stacks between chips and the heatsink. Two types of 1200 V, 36 A power modules are manufactured and experimentally compared. One utilizes the non-TIM structure integrated with <inline-formula> <tex-math>$50times 38times 24$ </tex-math></inline-formula> mm AlN ceramic heatsink, while the other follows the standard conventional packaging equipped with the same size 6063 Al Alloy heatsink. Tested under various air cooling and power loss conditions, the non-TIM power module consistently exhibits approximately a 2% reduction in junction-to-ambient thermal resistance compared to the traditional module, indicating the enhanced thermal performance of the non-TIM packaging. Furthermore, continuous performance testing confirms the suitability of the non-TIM power module packaging for operation at 650 V dc-link with 2 kW, making it a feasible choice for power converter applications. Moreover, an electro-thermal-mechanical finite element analysis (FEA) model and the digital image correlation (DIC) test are employed to evaluate the in-plane deformation. Results reveal that the maximum stress of the MOSFETs for the non-TIM packaging is significantly reduced by up to 40.2% along the defined path compared to the conventional structure, demonstrating the potential for better reliability with the proposed packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"512-524"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic IGBT Compact Thermal Network Model Over Long Time Scales","authors":"Mingyao Ma;Qian Zhang;Weisheng Guo;Qiwei Song","doi":"10.1109/TCPMT.2024.3513323","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3513323","url":null,"abstract":"The cause of failures in insulated gate bipolar transistor (IGBT) modules is primarily attributed to temperature-related factors. Accurately estimating the junction temperature of IGBT modules is crucial for enhancing their reliability. Currently, thermal network models stand as commonly used tools for estimating the junction temperature of IGBT modules. However, prevailing thermal models exhibit certain limitations in accurately predicting the junction temperature, particularly when considering the degradation of chip solder within IGBT modules. This article presents a practical degradation model of the chip solder layer, establishing a functional correlation between the chip solder degradation rate and the number of power cycles. A dynamic compact thermal network model over long time scales is established, and the method for thermal parameter extraction is discussed. The finite-element simulation and experimental results show that the dynamic compact thermal network model can accurately estimate the junction temperature.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"123-130"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2024.3500721","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500721","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C4-C4"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Noncontact Integration of Photonic IC and Electronic IC via Inductively Coupled Interconnects","authors":"Tongchuan Ma;Liyiming Yang;Yanlu Li;Yuan Du","doi":"10.1109/TCPMT.2024.3511042","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3511042","url":null,"abstract":"This letter presents an innovative noncontact packaging technique for photonic integrated circuits (PICs) and electronic integrated circuits (EICs) through inductively coupled interconnects. The primary aim of this approach is to enhance thermal isolation between the heat-generating electrical logic die and the thermally sensitive optical interferometer die. The feasibility of this contactless transceiver, which fulfills information transmission from the laser Doppler vibrometry (LDV) to the EIC, is substantiated via electromagnetic simulations. Furthermore, thermal simulations conducted by COMSOL prove that this packaging configuration could potentially reduce the temperature of PICs by up to <inline-formula> <tex-math>$4.6~^{circ }$ </tex-math></inline-formula>C when compared to the conventional 3-D stack packaging, underlining its potential for improved thermal performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"232-234"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142992901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2024.3500719","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500719","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778114","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2024.3500715","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500715","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778162","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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