IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Composite Right-/Left-Handed Bandpass Filters With Enhanced Out-of-Band Rejection Using Slow Wave Metamaterial Structure","authors":"Bukun Xu;Yazi Cao;Bo Yuan;Yanzhu Qi;Shichang Chen;Peng Zhao;Gaofeng Wang","doi":"10.1109/TCPMT.2025.3552681","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3552681","url":null,"abstract":"A compact and easy-to-fabricate metamaterial by virtue of multilayer slow wave structure is introduced to effectively enhance the out-of-band rejection of composite right-/left-handed (CRLH) bandpass filters (BPFs). An equivalent circuit model of this multilayer slow wave metamaterial structure is derived and discussed. Four BPFs are designed and fabricated using 3-D glass integrated passive device (IPD) technology. The first two BPFs consist only of novel CRLH resonator unit cells, and the last two BPFs are composed of multilayer slow wave metamaterial structures introduced with the same parameters as the first two BPFs. The electromagnetic field in the BPFs is redistributed due to the presence of this metamaterial structure, which can significantly improve the filter attenuation capability at high-frequency spurious. Through simulations and measurements, the two BPFs incorporating multilayer slow wave metamaterial structures enhance the out-of-band attenuation capability at the high-frequency end by nearly 3 and nearly 18 times compared to the first two BPFs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1468-1478"},"PeriodicalIF":2.3,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Complex Permittivity Characterization of Low-Loss SlabsUsing Time-Gating Technique","authors":"Bing Xue","doi":"10.1109/TCPMT.2025.3551958","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3551958","url":null,"abstract":"This letter presents an innovative method for assessing the complex dielectric constants of low-loss dielectric slabs at sub-terahertz (THz) frequencies. Differing from conventional free-space techniques, the proposed approach removes the need for precise thickness knowledge of the material under test (MUT) and reference plane calibration. Even when the MUT thickness varies in a single sample, the proposed method effectively reduces the relevant estimate uncertainty. When applying it to estimate the permittivity of thick plexiglass and nylon plates across the 140–210-GHz frequency range, it demonstrates good agreement with published articles and lower uncertainty of the estimates. The proposed method is well-suited for permittivity characterizations at THz frequencies, particularly in scenarios where precise rulers are lacking or MUT thickness varies in a single sample.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1151-1154"},"PeriodicalIF":2.3,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10929045","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143932259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel 3-D-Printed Passive Microfluidic Temperature Sensor for Medical Applications","authors":"Issam El Gmati;Yosra Gmati;Wided Amara;Ridha Ghayoula;Amor Smida;Mohamed Ibrahim Waly;Jaouhar Fattahi;Jamil Satouri","doi":"10.1109/TCPMT.2025.3552029","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3552029","url":null,"abstract":"The electrical response of a novel passive 3-D-printed temperature sensor could significantly broaden its scope of applications and enhance the integration of microelectro-mechanical system (MEMS) microfluidic-based laboratory-on-a-chip (LOC) technologies. This article introduces an innovative temperature sensor based on the microfluidic technology which is well-suited for medical applications. The sensor’s design and optimization were conducted using multiphysics modeling and finite element method (FEM) simulations, implemented through FreeFEM++ software. Samples were produced using stereolithographic 3-D printing. A metal carrier was constructed to secure the chips during tank heating and the flow visualization with a microscope. X-ray microtomography tests were performed on chips to compare real parts with CAD models. Filling tests were conducted to position the liquid within the microfluidic channel. Furthermore, several types of liquids were tested, and contact angle (CA) measurements were employed to characterize the microfluidic chip’s structural material (DS3000) and various liquids, aiding in discerning the dielectric liquid were applied also. Among the liquids tested, water emerged as the most promising for this type of temperature sensor. Volume expansion calculations for different temperature values were performed, revealing a measured linear thermal expansion exceeding <inline-formula> <tex-math>$40~mu $ </tex-math></inline-formula>m/°C within the range of <inline-formula> <tex-math>$20~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$55~^{circ }$ </tex-math></inline-formula>C. This study paves the way for microfluidic devices capable of measuring low flow rates using a temperature effect, thereby providing access to 16 an electrical response.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1432-1445"},"PeriodicalIF":2.3,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Simplified Method for Analyzing PCB Warpage During Reflow: Focusing on Warpage Change and Initial Warpage Shape","authors":"Zhenyang Lei;Jinyong Li;Dayuan Wan;Chunmin Cheng;Daowei Wu;Wei Shen;Kang Liang;Sheng Liu","doi":"10.1109/TCPMT.2025.3570867","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3570867","url":null,"abstract":"Printed circuit boards (PCBs) often experience warpage during reflow soldering due to thermal stresses. This study presents a simplified approach to analyze PCB warpage by focusing on warpage change instead of absolute warpage. Absolute warpage is difficult to simulate accurately due to challenges in defining temperature loads, boundary conditions, and the zero stress-strain temperature. Warpage change, which compares warpage at elevated temperatures (e.g., <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C) with a baseline (<inline-formula> <tex-math>$30~^{circ }$ </tex-math></inline-formula>C), isolates thermal deformation and simplifies the simulation process. The study also introduces an image processing method to accurately identify the Cu distribution in each PCB layer, which is critical for determining material properties. Using finite element method (FEM) and incorporating both Cu distribution and initial warpage, this method provides more consistent and reliable warpage predictions. Simulation and experimental results demonstrate that warpage change is a more effective metric for evaluating PCB thermal deformation, offering valuable insights for improving PCB design and manufacturing.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1502-1510"},"PeriodicalIF":2.3,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring Efficient Thermal Management Solutions for Backside Power Delivery Network (BSPDN) Systems Using Multiscale Modeling","authors":"Feifan Xie;Tiwei Wei","doi":"10.1109/TCPMT.2025.3551225","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3551225","url":null,"abstract":"The backside power delivery network (BSPDN) is seen as a transformative technology for the next generation of chip designs. However, it introduces significant thermal challenges compared to the conventional frontside power delivery network (FSPDN). Modeling analysis of CPU hotspot areas indicates that BSPDN results in temperatures approximately 45% higher than FSPDN. To address these thermal challenges, we have systematically explored both conduction and convection cooling solutions. These include the use of advanced bonding interfaces with thermal conductivity [ranging from 0.2 to 1000 W/(m <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> K)], various back end of line (BEOL) layer configurations (stacked, staggered, and isolated), advanced BEOL metal materials (such as Cu, Ru, and Co interconnects), and embedded microchannel cooling within the backside metal (BSM) region to effectively dissipate heat toward the bottom substrate. The microchannel design is inspired by the geometric similarities between the airgap-BEOL structure and cutting-edge 3-D manifold microchannel coolers. To address the modeling challenges posed by the multiscale (ranging from 20 nm to <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>m) and multiphysics (thermal and fluid dynamics) simulations within the BSPDN system, we have adopted an integrated modeling framework proposed by IMEC. This framework serves as a research tool to support our in-depth thermal solution exploration and analysis. For studying the effective BEOL properties, a small-scale model of <inline-formula> <tex-math>$1times 1~mumathrm{m}^{2}$ </tex-math></inline-formula> is used to extract the equivalent thermal conductivity of an eight-layer Mint-M8 BEOL, which is then applied for thermal analysis under different BEOL interconnect configurations. A <inline-formula> <tex-math>$0.12times 0.12~mumathrm{m}^{2}$ </tex-math></inline-formula> model containing Mint-M3 is employed for material matrix studies. For hotspot analysis, a larger <inline-formula> <tex-math>$10times 25~mumathrm{m}^{2}$ </tex-math></inline-formula> model is used to generate temperature distribution maps with various heat-spreading materials and embedded microchannel cooling parameter investigations. These proposed solutions are expected to significantly enhance the thermal performance of BSPDN. Ultimately, this article aims to provide a comprehensive set of thermal design guidelines for the BSPDN architecture, advancing chip power, performance, and area (PPA) in advanced technology nodes.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1237-1247"},"PeriodicalIF":2.3,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Experimental Study on a Barrier-Less Cu Interconnect Scheme With Polyimide Insulator for Cost-Effective 3-D Packaging","authors":"Han Wang;Yingtao Ding;Ziyue Zhang;Ziru Cai;Lei Xiao;Yangyang Yan;Zhiming Chen","doi":"10.1109/TCPMT.2025.3569685","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3569685","url":null,"abstract":"Polyimide (PI) has been widely used as the insulator material in the Cu interconnect system for 3-D advanced packaging. In general, a barrier layer is required between PI and Cu to suppress Cu diffusion, which increases the fabrication cost and complexity. In this article, we experimentally investigate the feasibility of a barrier-less Cu interconnect scheme with PI insulator while omitting the typical barrier layer. The diffusion phenomenon of sputtered Cu in PI is evaluated by the energy dispersive X-ray spectroscopy (EDX) analyses and the Fourier transform infrared spectroscopy (FTIR) tests. It is revealed that the PI layer with sufficient thickness can prevent the Cu atoms from diffusing into the Si substrate even after annealing at <inline-formula> <tex-math>$300~^{circ }$ </tex-math></inline-formula>C for 1 h. Electrical measurement results based on the Cu–PI–Si structure show that the leakage currents are relatively small across various test temperatures, and there is little degradation in the insulating performance of PI after annealing. Moreover, time-dependent dielectric breakdown (TDDB) tests are carried out, and the mean-time-to-failure (MTTF) of PI before or after annealing is estimated to be more than ten years for electric fields less than 1.45 or 1.25 MV/cm, respectively. Therefore, the proposed barrier-less Cu interconnect scheme with PI insulator demonstrates feasibility in terms of insulating performance and long-term reliability. This scheme is further implemented in the vertical through-silicon-via (TSV) structure by a low-cost fabrication flow, which exhibits good electrical performance in both the leakage current and the parasitic capacitance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1385-1391"},"PeriodicalIF":2.3,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Achieving High Reliability in Silicon Photonics Optical Transceivers for Harsh Environments Over 100 °C in Excess of Ten-Year Operation","authors":"K. Kurata;S. Kobayashi;T. Nakamura;K. Yashiki;T. Muto;M. Kuwata;D. Okamoto;Y. Hagihara;R. Pitwon","doi":"10.1109/TCPMT.2025.3549758","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3549758","url":null,"abstract":"In this article, we report on the design and performance of a silicon photonics microtransceiver, which is designed to operate in harsh environments including high-temperature environments above <inline-formula> <tex-math>$105~^{circ }$ </tex-math></inline-formula>C and space environments. In addition, we demonstrated that the microtransceiver modules have been applied to immersion cooling, which must be considered another harsh environmental condition due to its novelty for optical active components. The four-channel “IOCore (Registered trademark)” microtransceiver incorporates a 1310-nm quantum dot (QD) laser system and operates at a symbol rate of 32 GBd and higher. The <inline-formula> <tex-math>$5times 5$ </tex-math></inline-formula> mm microtransceiver chip benefits from a multimode coupling interface for low-cost assembly and robust connectivity at high temperatures.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1592-1600"},"PeriodicalIF":3.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10922121","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine Learning-Based Diagnosis of Defects in 2.5-D and 3-D Interconnects","authors":"Junming Li;Huaguo Liang;Hao Lv;Yuqi Pan;Zhengfeng Huang;Tian Chen;Yingchun Lu","doi":"10.1109/TCPMT.2025.3550201","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3550201","url":null,"abstract":"Diagnosing interconnect line defects becomes increasingly challenging in advanced chiplet integration due to the immaturity of fabrication processes, reduced interconnect spacing, and increased density. In this article, a nondestructive interconnect defect diagnosis method is proposed. First, redistribution layers (RDLs) on the 2.5-D silicon interposer and 3-D through silicon via-RDL (TSV-RDL) interconnect channels are simulated by ANSYS HFSS, with open and short defects injected at various positions to analyze signal integrity; utilizing <italic>S</i> parameters and group delay time (GDT) as feature vectors, machine learning algorithms are employed specifically for the classification and identification of defects. For defect localization, a novel high-precision scheme driven by adaptive regression and clustering is proposed, achieving highly accurate and reliable localization of defects. The results show that the algorithm can accurately identify open and short defects. In defect localization, the mean relative error (MRE) of the proposed method is less than 8%, and the maximum relative error (MaxRE) does not exceed 13%. Compared with the related algorithms, the localization accuracy is significantly improved, providing a novel perspective for the identification and localization of defects within package interconnect lines.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1104-1116"},"PeriodicalIF":2.3,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Antenna-Integrated and PA-Embedded Glass Substrates for D-Band InP Power Amplifier Modules","authors":"Xiaofan Jia;Xingchen Li;Joon Woo Kim;Kyoung-Sik Moon;Mark J. W. Rodwell;Madhavan Swaminathan","doi":"10.1109/TCPMT.2025.3549371","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3549371","url":null,"abstract":"This article presents an innovative antenna-in-package (AiP) solution designed for 140-GHz indium phosphide (InP) power amplifier (PA) front-end modules. In this design, InP PAs are strategically embedded at the center of a glass substrate (AGC EN-A1) sandwiched by low-loss dielectric layers (ABF-GL102) on both sides. This arrangement facilitates ultrashort die-to-package interconnects through 20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m dielectric vias, achieving a remarkably low simulated loss of 0.2–0.3 dB at 140 GHz and an impressive <inline-formula> <tex-math>$S11$ </tex-math></inline-formula>/<inline-formula> <tex-math>$S22$ </tex-math></inline-formula> of less than −15 dB across a wide frequency range from 110 to 170 GHz. We conducted a thorough evaluation of various PA designs with two-stage and three-stage amplifying circuits embedded within this package. The findings reveal that the embedded InP PAs deliver consistent small signal gains of 11.1 dB for the two-stage and 15.8 dB for the three-stage PAs at 140 GHz, comparable with their bare die performance and other existing packaging technologies. A key feature of this design is the integration of a 5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick copper heat spreader on the PA backside, which significantly enhances thermal management. In addition, the design accommodates the seamless integration of a <inline-formula> <tex-math>$1times 8$ </tex-math></inline-formula> microstrip patch antenna array. Directly connected to the PA output, this array achieves maximum broadside gains of 12.9, 25.3, and 29.7 dB for the standalone antenna, and the PA-antenna modules with two-stage and three-stage PAs at 139 GHz, respectively, over a 3-dB bandwidth of 5 GHz (136–141 GHz). Moreover, the radiation pattern of the PA-antenna module has been meticulously characterized, showcasing a <inline-formula> <tex-math>$13^{circ } ~3$ </tex-math></inline-formula>-dB <italic>E</i>-plane beamwidth and <inline-formula> <tex-math>$64^{circ } ~3$ </tex-math></inline-formula>-dB <italic>H</i>-plane beamwidth from the broadside. With its superior electrical and thermal performance, scalability, and cost-effectiveness, this package presents a promising solution for developing D-band beamforming arrays in next-generation communication systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"782-791"},"PeriodicalIF":2.3,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Artificial Intelligence-Driven Optimization for 3-D Integrated Circuit Manufacturing: A System of Systems Framework","authors":"Arifuzzaman Sheikh;Edwin K. P. Chong","doi":"10.1109/TCPMT.2025.3549707","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3549707","url":null,"abstract":"This article introduces an artificial intelligence (AI)-driven framework for optimizing 3-D integrated circuit (3D-IC) manufacturing through a system of systems (SoS) approach. Our framework integrates defect detection, process optimization, and electrical failure prediction using advanced methodologies, notably convolutional neural networks (CNNs), Random Forest classifiers, and long short-term memory (LSTM) networks. By dynamically aligning subsystem outputs with global manufacturing objectives, our framework addresses key challenges in through-silicon via (TSV) formation, defect reduction, and yield enhancement. Adaptive optimization techniques—including simulated annealing and dual annealing—are employed to refine critical parameters such as TSV depth, deposition rate, and etching temperature. Achieving a global yield of 58.48%, the proposed approach demonstrates its scalability and effectiveness in reducing defect rates while ensuring high manufacturing reliability. This article establishes a foundation for advancing AI-driven decision-making in complex manufacturing systems, bridging theoretical innovations and practical implementation.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1538-1552"},"PeriodicalIF":2.3,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}