IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Geometry Optimization of Nonideal Through-Glass Vias (TGVs) for Enhanced Electrical and Mechanical Performance","authors":"Zhen Fang;Jinxu Liu;Borui Li;Wenlei Li;Jihua Zhang","doi":"10.1109/TCPMT.2026.3700943","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3700943","url":null,"abstract":"Through-glass vias (TGVs) have attracted considerable attention in advanced packaging because they offer low dielectric loss and good electrical insulation. However, the tapered sidewalls formed during fabrication can affect the reliability of glass-based packages. These sidewalls increase the parasitic inductance at high frequencies and cause nonuniform stress under thermal loading. Existing TGV inductance models still have limited ability to describe skin-current effects in nonvertical vias. This study presents an analytical model for tapered TGVs that includes skin current and defines the frequency range in which the model is applicable. The effect of taper angle on stress distribution at <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C is also examined. The results show that the taper angle redistributes stress in the copper column and reduces stress concentration at the Cu/glass interface. By further optimizing laser power, ultrasonic power, HF concentration, etching temperature, and ammonium fluoride concentration, precise control of the TGV taper is achieved. This work provides a design reference and an optimization strategy for high-performance glass interposers.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1643-1651"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resiliency of Liquid-to-Liquid Cooling Systems in Data Centers Under Failure Scenarios","authors":"Himanshu Modi;Ali Heydari;Pardeep Shahi;Lochan Sai Reddy Chintaparthy;Anto Barigala;Mohammad Raisul Islam;Dereje Agonafer;Mohammad Tradat;Saket Karajgikar;Jeremy Rodriguez","doi":"10.1109/TCPMT.2026.3704055","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3704055","url":null,"abstract":"The growing computational demand in modern data centers has led to the adoption of liquid-to-liquid (L2L) cooling systems to efficiently manage heat dissipation from high-performance computing (HPC) infrastructure. This research investigates the resiliency of L2L cooling systems, focusing on their performance under a variety of failure scenarios that could compromise thermal management. The primary objective is to evaluate how different failure modes, including total and partial primary flow reductions, cooling distribution unit (CDU) pump malfunctions, and full CDU system failures, impact the thermal stability of critical components within data centers. An experimental setup featuring a row-based L2L cooling solution, with multiple CDUs and server racks filled with thermal test vehicles (TTVs), has been developed to simulate real-world data center conditions. The system is equipped with precise instrumentation for monitoring temperature, pressure, and flow rates, enabling detailed analysis of thermal behavior in both the primary and secondary cooling loops. The study aims to assess the response time and effectiveness of redundancy mechanisms, such as backup CDU pumps, N + 1 configurations, and failover systems, in mitigating potential risks during failure events. By identifying critical vulnerabilities and developing strategies for rapid recovery, this work seeks to enhance the robustness of L2L cooling systems, ensuring they can adapt to adverse conditions while maintaining the thermal integrity of high-density data centers. This research contributes to the broader understanding of cooling system resilience in data centers and provides valuable insights into designing more reliable thermal management solutions for future HPC environments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1526-1533"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2026.3707046","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3707046","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"C3-C3"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11609687","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Loss D-Band Power Divider Using SiC-Based SIWs","authors":"Weifeng Wu;Yunjiang Ding;Xiaopeng Wang;Lei Li;Yu-En Jeng;Pengcheng Xu;Juncheng Xiong;James C. M. Hwang;Patrick Fay","doi":"10.1109/TCPMT.2026.3682269","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3682269","url":null,"abstract":"The design, fabrication, and characterization of novel D-band power dividers in both Y- and T-junction configurations, using substrate-integrated waveguide (SIW) technology fabricated on a 100-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick 4H-silicon carbide (SiC) substrate, are reported. The three-port S-parameters of the fabricated dividers were measured and calibrated on-wafer, achieving an excess loss (EL) as low as <inline-formula> <tex-math>$0.68~pm ~0.10$ </tex-math></inline-formula> dB and an average return loss (RL) of up to 25 dB across the full D-band. This is, to the best of our knowledge, the first demonstration of a SiC-based SIW power divider at D-band, offering excellent performance and compatibility with GaN-on-SiC monolithic microwave integrated circuit (MMIC) fabrication processes.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1611-1618"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Evaluation of the Zigzag-Fin Multiparallel Serpentine Heat Sink for IGCTs","authors":"Xiaoguang Wei;Wei Hao;Jiamin Gao;Zhongkang Lin;Xinling Tang;Jingfei Wang;Rui Liu","doi":"10.1109/TCPMT.2026.3662797","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3662797","url":null,"abstract":"Press-pack high-power devices, such as integrated gate-commutated thyristors (IGCTs), are widely used in high-voltage direct current (HVDC) transmission systems. A key engineering challenge is managing their high heat flux density (<inline-formula> <tex-math>$ge$ </tex-math></inline-formula>40 W/cm<inline-formula> <tex-math>${}^{2}$ </tex-math></inline-formula>). To address the cooling bottleneck for 5-kA IGCTs, this article proposes a novel water-cooled heat sink featuring an integrated zigzag-fin multiparallel serpentine (ZMPS) flow channel. By synergistically combining the merits of serpentine (enhanced heat transfer), parallel (reduced pressure drop), and spiral (improved temperature uniformity) channel designs, the ZMPS architecture effectively balances the inherent tradeoffs among thermal resistance, pressure drop, and temperature uniformity. Numerical simulations and experimental results demonstrate that, at a flow rate of 27 L/min, the ZMPS heat sink achieves a thermal resistance of 2.44 K/kW. Compared to a conventional straight-channel baseline, it reduces thermal resistance by 34.9%, improves temperature uniformity by 80%, and increases the performance evaluation criterion (PEC) by 2.2 times, all while maintaining an acceptable system pressure drop. The study validates the ZMPS design as an effective and practical thermal management solution for high-power electronic devices.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1543-1555"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of a Compact Manifold Heatsink in External Airflow for Power Devices Using a Multiobjective Genetic Algorithm","authors":"Wenguang Zhao;Gearóid Farrell;Rajesh Nimmagadda;Shailesh N. Joshi;Ercan. M. Dede;Tim Persoons","doi":"10.1109/TCPMT.2026.3653162","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3653162","url":null,"abstract":"This article presents a robust multiobjective genetic algorithm (MOGA) optimization of the novel converging–diverging (CONDIV) manifold heatsink for external airflow environments. The CONDIV manifold is designed to protect internal heatsinks from debris-laden flows while maintaining high thermal performance. Previous studies relied on simple parametric sweeps for only a limited exploration of the design space of external manifolds, limiting the discovery of optimal designs. Here, a comprehensive MOGA framework is implemented, combining 3-D computational fluid dynamics (CFD) simulations validated against experiments. Seven geometric parameters are optimized to simultaneously minimize thermal resistance and pumping power, maximizing the coefficient of performance (COP). The design of experiments (DOE) is generated via Latin hypercube sampling (LHS), and a response surface model is constructed to approximate heatsink performance. The MOGA efficiently explores the design space, yielding a Pareto front of optimal solutions. Best compromise solutions (BCSs) are selected and verified through CFD. Results show that MOGA-optimized designs consistently outperform previous CONDIV and baseline plate-fin heatsinks, achieving up to 33% higher COP and 4.3% greater heat flux than previous CONDIV-H design and 42.4% higher mean COP than the baseline plate-fin heatsink. Detailed flow analyzes reveal that optimized BCSs improve airflow into internal channels and improve flow uniformity, resulting in superior thermal management. This demonstrates the strong potential of MOGA-driven optimization for advanced manifold heatsink applications in electrified transport.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1487-1498"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11346515","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Machine-Learning-Based Prediction Method for Manufacturing Tolerances in Multilayer Circuit","authors":"Weihong Liu;Shuai Zhang;Zhiyuan Qu;Miao Zhao","doi":"10.1109/TCPMT.2026.3702535","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3702535","url":null,"abstract":"Manufacturing tolerances (MTs) have a significant impact on the transmission characteristics of millimeter-wave circuits. Therefore, it is urgently necessary to obtain a cost-effective strategy for predicting MTs. This letter proposes a method that combines the vector network analyzer (VNA) with machine learning (ML) to estimate the MTs in multilayer liquid crystal polymer (LCP) circuits. First, an artificial neural network (ANN) surrogate model is trained to map geometric parameters to electromagnetic (EM) responses using a sampled dataset. Subsequently, the S-parameters measured by the VNA are used as the target function of the genetic algorithm (GA) to inversely determine the MTs of the fabricated circuit while ensuring its structural integrity. Experimental validation demonstrates that the prediction percentage error of key geometric parameters is below 10%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1689-1692"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermomechanical Stress Optimization of Tapered Through-Glass Vias Using Stress-Relief Structures","authors":"Jinxu Liu;Jihua Zhang;Zhen Fang;Zihan Wang;Borui Li;Shuqi Li;Wenlei Li;Wanli Zhang","doi":"10.1109/TCPMT.2026.3694441","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3694441","url":null,"abstract":"Through-glass vias (TGVs) are increasingly used in advanced packaging, offering superior performance compared to through-silicon vias (TSVs). However, the thermal expansion mismatch between copper and glass causes significant thermomechanical stresses, which may lead to packaging reliability issues. In this study, we analyzed stress-mitigation strategies for hyperbolic TGVs using finite element modeling. A series of models incorporating various stress-buffer layers and trench isolation structures (annular and shallow trench) was developed to analyze their impact on thermal stress distribution. Simulation results reveal that these strategies effectively reduce interfacial stress concentrations, particularly under elevated temperature conditions. The proposed design modifications offer promising solutions for enhancing the thermomechanical reliability of glass-based packaging platforms.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1693-1696"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Recovery Characteristics and Parameter Dependence Under Dishing in Cu/SiO2 Interconnect Bonding Structures","authors":"Seung Hwan Oh;Sarah Eunkyung Kim;Jong Kyung Park;Seul Ki Hong","doi":"10.1109/TCPMT.2026.3701074","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3701074","url":null,"abstract":"As semiconductor device integration continues to scale, ensuring the reliability of Cu–Cu direct bonding has emerged as a critical requirement for next-generation 3-D integrated circuits (3-D-ICs) and wafer-level packaging (WLP) technologies. However, dishing defects induced by chemical mechanical polishing (CMP) lead to nonuniform interfacial contact, thereby causing void formation, debonding, and overall degradation of bonding quality. In this work, we combine finite-element simulations, extreme gradient boosting (XGBoost)–SHapley Additive exPlanations (SHAP)-based machine-learning analysis, and experimental validation to quantitatively evaluate the influence of dishing gap size, bonding temperature, and applied pressure on interfacial recovery. The results revealed that smaller gaps exhibited higher recovery ratios, with temperature identified as the most dominant factor, followed by gap size and pressure as secondary contributors. Experimental validation was carried out using photolithography-based step-height patterns (1000 and <inline-formula> <tex-math>$2000~mu $ </tex-math></inline-formula>m). 3-D profiler measurements indicated increased step heights with larger patterns, while scanning acoustic tomography (SAT) demonstrated that bonding yields above 99% could be achieved under high-temperature and high-pressure conditions, whereas significantly reduced bonding ratios were observed under lower conditions. The experimental results were in strong agreement with the simulations, and further analysis confirmed that when the dishing gap was <inline-formula> <tex-math>$le 0.15~mu $ </tex-math></inline-formula>m, stable bonding ratios above 80% could be consistently obtained at <inline-formula> <tex-math>$sim 330~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$360~^{circ }$ </tex-math></inline-formula>C and 6–6.5 MPa. These results indicate that reliable Cu–Cu bonding does not necessarily require the complete elimination of dishing; rather, maintaining the effective dishing gap at or below <inline-formula> <tex-math>$0.15~mu $ </tex-math></inline-formula>m and prioritizing temperature-driven recovery enables stable bonding above 80% under approximately <inline-formula> <tex-math>$330~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$360~^{circ }$ </tex-math></inline-formula>C and 6–6.5 MPa for the investigated structure.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1682-1688"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermofluidic Visualization of the Capillary-Driven Boiling for Design Optimization of Silicon-Embedded Evaporators","authors":"Yujui Lin;Heungdong Kwon;Kewei Xiao;Man Prakash Gupta;Michael Degner;Mehdi Asheghi;H. Alan Mantooth;Kenneth E. Goodson","doi":"10.1109/TCPMT.2025.3636077","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3636077","url":null,"abstract":"Two-phase embedded microcoolers emerge as a promising solution to high-performance and highly efficient cooling for microprocessors and power electronics. We characterized capillary-driven embedded microcoolers with silicon microchannels (width = 120 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, height = 200 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and spacing = 480 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m) coated with 20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick, porous hydrophilic copper dendritic microstructure and a heated area of <inline-formula> <tex-math>$5^{2}$ </tex-math></inline-formula> mm². We implemented a two-way (1-D) and four-way (2-D) liquid delivery scheme to the evaporator, achieving improved critical heat flux (CHF) levels of 370 versus 450 W/cm² and superheat level of ~10 °C, leading to a heat transfer coefficient (HTC) of 300 000 versus 450 000 W/m<inline-formula> <tex-math>${}^{2} {cdot}^{circ }$ </tex-math></inline-formula>C (or R<inline-formula> <tex-math>${}^{prime prime } sim ~0.027$ </tex-math></inline-formula> versus 0.022 cm<inline-formula> <tex-math>${}^{2} {cdot}^{circ }$ </tex-math></inline-formula>C/W). To provide additional insight into the physics of capillary-driven boiling, bubble dynamics, and dry-out formation, we conducted infrared (IR) thermal and high-speed flow visualization imaging. An important finding is related to the delayed dry-out of ~300 ms in capillary-based microcoolers compared to a much shorter timescale of 210 ms for the two-phase pumped flow boiling in smooth silicon microchannels. The result demonstrates the potential of the capillary-based two-phase microcooler for transient thermal management. For future work, we will consider optimizing the microchannel dimensions, in particular, width and spacing, and introducing hydrophilic copper dendritic microstructure at the walls of the microchannels.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 7","pages":"1499-1512"},"PeriodicalIF":3.3,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}