Junming Li;Huaguo Liang;Hao Lv;Yuqi Pan;Zhengfeng Huang;Tian Chen;Yingchun Lu
{"title":"Machine Learning-Based Diagnosis of Defects in 2.5-D and 3-D Interconnects","authors":"Junming Li;Huaguo Liang;Hao Lv;Yuqi Pan;Zhengfeng Huang;Tian Chen;Yingchun Lu","doi":"10.1109/TCPMT.2025.3550201","DOIUrl":null,"url":null,"abstract":"Diagnosing interconnect line defects becomes increasingly challenging in advanced chiplet integration due to the immaturity of fabrication processes, reduced interconnect spacing, and increased density. In this article, a nondestructive interconnect defect diagnosis method is proposed. First, redistribution layers (RDLs) on the 2.5-D silicon interposer and 3-D through silicon via-RDL (TSV-RDL) interconnect channels are simulated by ANSYS HFSS, with open and short defects injected at various positions to analyze signal integrity; utilizing <italic>S</i> parameters and group delay time (GDT) as feature vectors, machine learning algorithms are employed specifically for the classification and identification of defects. For defect localization, a novel high-precision scheme driven by adaptive regression and clustering is proposed, achieving highly accurate and reliable localization of defects. The results show that the algorithm can accurately identify open and short defects. In defect localization, the mean relative error (MRE) of the proposed method is less than 8%, and the maximum relative error (MaxRE) does not exceed 13%. Compared with the related algorithms, the localization accuracy is significantly improved, providing a novel perspective for the identification and localization of defects within package interconnect lines.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1104-1116"},"PeriodicalIF":3.0000,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10922176/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Diagnosing interconnect line defects becomes increasingly challenging in advanced chiplet integration due to the immaturity of fabrication processes, reduced interconnect spacing, and increased density. In this article, a nondestructive interconnect defect diagnosis method is proposed. First, redistribution layers (RDLs) on the 2.5-D silicon interposer and 3-D through silicon via-RDL (TSV-RDL) interconnect channels are simulated by ANSYS HFSS, with open and short defects injected at various positions to analyze signal integrity; utilizing S parameters and group delay time (GDT) as feature vectors, machine learning algorithms are employed specifically for the classification and identification of defects. For defect localization, a novel high-precision scheme driven by adaptive regression and clustering is proposed, achieving highly accurate and reliable localization of defects. The results show that the algorithm can accurately identify open and short defects. In defect localization, the mean relative error (MRE) of the proposed method is less than 8%, and the maximum relative error (MaxRE) does not exceed 13%. Compared with the related algorithms, the localization accuracy is significantly improved, providing a novel perspective for the identification and localization of defects within package interconnect lines.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.