IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

Failure Mechanism and Reliability Research of Solder Layer Tilt in Double-Sided Cooling Power Modules 双面冷却电源模块焊层倾斜的失效机理与可靠性研究

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3447124

Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang

{"title":"Failure Mechanism and Reliability Research of Solder Layer Tilt in Double-Sided Cooling Power Modules","authors":"Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang","doi":"10.1109/TCPMT.2024.3447124","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3447124","url":null,"abstract":"The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE 《部件、封装和制造技术》期刊为作者提供的信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3471053

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information 电气和电子工程师学会《部件、封装和制造技术》期刊出版信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3471051

引用次数: 0

Blank Page 空白页

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484209

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information 电气和电子工程师学会《元件、封装和制造技术》学会信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484225

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information 电气和电子工程师学会《元件、封装和制造技术》学会信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3471055

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information 电气和电子工程师学会《部件、封装和制造技术》期刊出版信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484219

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE 《部件、封装和制造技术》期刊为作者提供的信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-10-30 DOI: 10.1109/TCPMT.2024.3484223

引用次数: 0

The Analytical Model of Hotspot Temperature and the Effects of Different Factors in 3-D Integration 三维集成中热点温度的分析模型及不同因素的影响

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-09-18 DOI: 10.1109/TCPMT.2024.3462944

Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao

{"title":"The Analytical Model of Hotspot Temperature and the Effects of Different Factors in 3-D Integration","authors":"Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao","doi":"10.1109/TCPMT.2024.3462944","DOIUrl":"10.1109/TCPMT.2024.3462944","url":null,"abstract":"The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within \u0000<inline-formula> <tex-math>$2~^{circ }$ </tex-math></inline-formula>\u0000C. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. For cases with large-sized hot spot, to decrease the hotspot temperature, smaller microbump and greater chip thickness are advised in packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142248860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Robustness of Large-Size Vacuum Sealed Packages for Microbolometer Array 用于微测辐射热计阵列的大型真空密封封装的稳健性

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2024-09-17 DOI: 10.1109/TCPMT.2024.3462818

Hexin Xia;Hoang-Vu Nguyen;Avisek Roy;Per Ohlckers;Knut Eilif Aasmundtveit

{"title":"Robustness of Large-Size Vacuum Sealed Packages for Microbolometer Array","authors":"Hexin Xia;Hoang-Vu Nguyen;Avisek Roy;Per Ohlckers;Knut Eilif Aasmundtveit","doi":"10.1109/TCPMT.2024.3462818","DOIUrl":"10.1109/TCPMT.2024.3462818","url":null,"abstract":"Microbolometers are the core detectors of uncooled thermal sensors. These detectors require a high vacuum environment (<1> <tex-math>$sim 12times 12$ </tex-math></inline-formula>\u0000 mm) wafer-level Cu-Sn SLID packages using a time-dependent cap deflection study and exposing them to humidity and thermal shock test environments. Cap deflection measurements at the wafer level indicate that the dies maintained a stable vacuum for more than 13 months after bonding before they were exposed to harsh environments. The Cu-Sn SLID packages display resilience to corrosion effects, with 93% of the dies passing the humidity test. In contrast, all dies failed the thermal shock test due to vertical cracks in the Cu/Cu3Sn/Cu bondline. These vertical cracks are primarily found to propagate through voids in the Cu3Sn, where the stresses are assumed to be the largest. To mitigate vertical crack formation and enhance long-term sealing frame integrity, void formation must be minimized. Strict requirements are thus put on the electroplating process to avoid contamination, demanding careful monitoring of the bath conditions and optimization of the electroplating parameters.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142248861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0