IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

Predictive Modeling of TCV-Cu Protrusion Under Thermal Cycling 热循环作用下TCV-Cu突出的预测建模

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-01-15 DOI: 10.1109/TCPMT.2026.3654515

Heran Zhao;Tao He;Dan Li;Lihua Cao;Shizhao Wang;Mingxiang Chen

{"title":"Predictive Modeling of TCV-Cu Protrusion Under Thermal Cycling","authors":"Heran Zhao;Tao He;Dan Li;Lihua Cao;Shizhao Wang;Mingxiang Chen","doi":"10.1109/TCPMT.2026.3654515","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3654515","url":null,"abstract":"Through-ceramic-via copper (TCV-Cu) in direct-plated-copper (DPC) substrates can protrude during thermal cycling, threatening package planarity and interconnect reliability. This work develops a coupled thermo-mechanical framework that links transient temperature histories to out-of-plane deformation via a calibrated creep law for electroplated Cu. A 3-D finite-element model resolves the via shoulder and Cu/ceramic corner while enforcing realistic interface constraints and elastic heterogeneity. Creep parameters are identified by inverse optimization against 32 ramp-dwell thermal profiles using weighted least squares reflecting profilometer repeatability and registration uncertainty. The residual plots show no systematic bias, and leave-one-profile-out cross-validation confirms predictive robustness. Mechanistic analysis reveals stress-creep synergy during heating produces CEEQ pulses and peak protrusion, whereas high-temperature dwells and slow cooling govern residual buildup. A persistent ring-like stress hotspot forms at the via shoulder and Cu/ceramic interface corner. Sensitivity studies indicate faster ramps increase peak but reduce residual protrusion, while longer dwells amplify residuals; array pitch and modulus contrast modulate hotspot intensity. The results yield actionable process-window guidance for ramp rate, dwell duration, and layout, providing a compact, data-validated predictor for TCV-Cu protrusion in advanced packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2068-2075"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Lossy Decoupling Network for Anti-Resonance Suppression and Capacitor Reduction in CoWoP 一种用于coop抗谐振抑制和电容缩减的有损去耦网络

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-06-11 DOI: 10.1109/TCPMT.2026.3702815

Yuying Li;Mu-Shui Zhang;Zi-Xin Wang

{"title":"A Lossy Decoupling Network for Anti-Resonance Suppression and Capacitor Reduction in CoWoP","authors":"Yuying Li;Mu-Shui Zhang;Zi-Xin Wang","doi":"10.1109/TCPMT.2026.3702815","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3702815","url":null,"abstract":"Chip-on-wafer-on-platform (CoWoP) technology has recently been reported as a potential shift in the packaging technology for NVIDIA’s next-generation artificial intelligence (AI) GPUs for higher performance. CoWoP excludes package inductance and reduces the parasitic inductance of the voltage regulator module (VRM), which results in a fast and smaller printed circuit board (PCB) decoupling network. Small and fast decoupling networks are also accompanied by severe anti-resonance, causing unwanted sharp peaks in the frequency-domain impedance profile and voltage oscillations in the time-domain. The traditional target impedance design method leads to a larger number of decoupling capacitors for anti-resonance suppression. In this article, the anti-resonance-induced power noise of a multiple-capacitor decoupling network is studied first. It is recursively simplified to <inline-formula> <tex-math>$n$ </tex-math></inline-formula> second-order systems, and then the resonant parameters of each loop are derived. The transient response exhibits two types of voltage droops: inductive/resistive voltage drops and anti-resonance-induced oscillations. According to the analysis, a new decoupling network design method is proposed, in which lossy components are introduced for anti-resonance suppression and capacitor reduction. Anti-resonance-induced power noise is analyzed under transient conditions first. Through simulation and experimental validation, the lossy decoupling strategy can not only improve the robustness and efficiency of decoupling networks but also reduce nearly two-thirds of component usage compared to conventional methods. Some practical design guidelines are developed to balance the voltage drop and the loop loss, ensuring reliable decoupling network performance in CoWoPs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2114-2126"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Dynamic Capillary Limits of a Heat Pipe: Mapping the Operating Power Ranges Using a Transient Dryout and Rewetting Model 热管的动态毛细极限：用瞬态干燥和再润湿模型映射工作功率范围

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-04-30 DOI: 10.1109/TCPMT.2026.3689442

Shrutika Singh;Justin A. Weibel

{"title":"The Dynamic Capillary Limits of a Heat Pipe: Mapping the Operating Power Ranges Using a Transient Dryout and Rewetting Model","authors":"Shrutika Singh;Justin A. Weibel","doi":"10.1109/TCPMT.2026.3689442","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3689442","url":null,"abstract":"This work demonstrates the use of a transient model to map the operational limits of a heat pipe based on the time-to-dryout (<italic>TTD), evaporator temperature, and time-to-rewet (<italic>TTR) in response to dynamic high-power pulses and subsequent throttling. The model considers dynamic coupling between the local liquid saturation and capillary pressure, as well as incorporates wetting hysteresis to predict pulse-load-induced dryout and power-throttling-assisted recovery. Traditional heat pipe design and performance metrics consider the “steady capillary limit” (maximum power at which a steady heat load can be maintained without dryout), but this steady-state framework does not capture the transient power excursions common in modern electronic systems. This work, therefore, puts forth a framework for mapping the “dynamic capillary limits” of a heat pipe as a function of the transient workload of interest. Specifically, the framework produces design-ready operational maps that quantify the <italic>TTD, peak evaporator temperature during a pulse (<inline-formula> <tex-math>$T_{evap}$ </tex-math></inline-formula>), and <italic>TTR during throttling—thereby defining dynamic capillary limits beyond the conventional steady capillary limit. These operational maps are effective as tools for assessing the transient limits of performance and can be generated for different heat pipe designs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2036-2045"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Physics-Guided FE Surrogate CDNN With Grouped Attention and Monotonicity Constraints for Solder Joint Thermal Fatigue Life Prediction 基于分组关注和单调性约束的物理引导FE替代CDNN焊点热疲劳寿命预测

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-08-10 DOI: 10.1109/TCPMT.2026.3721074

Yaxian Huang;Yang Xi;Renxiang Wang;Wenwang Zhang;Yutong Dai;Dan Li;Heran Zhao;Shizhao Wang;Bin Wang

{"title":"Physics-Guided FE Surrogate CDNN With Grouped Attention and Monotonicity Constraints for Solder Joint Thermal Fatigue Life Prediction","authors":"Yaxian Huang;Yang Xi;Renxiang Wang;Wenwang Zhang;Yutong Dai;Dan Li;Heran Zhao;Shizhao Wang;Bin Wang","doi":"10.1109/TCPMT.2026.3721074","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3721074","url":null,"abstract":"The prediction of thermal fatigue life for solder joints is a key aspect of reliability design in electronic packaging. Existing methods face challenges such as high barriers to traditional finite element (FE) simulation, low efficiency, and poor reusability, while purely data-driven models suffer from issues like the “limited transparency” nature, overfitting in small-sample conditions, and limited physical interpretability. This article proposes a physics-guided FE surrogate convolutional deep neural network (CDNN) model that integrates a physical grouped attention mechanism with dynamic monotonicity constraints, specifically designed for high-accuracy and interpretable life prediction under small-sample conditions. Through fivefold stratified cross-validation, the results show that the model achieves an <inline-formula> <tex-math>$R^{2}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$0.8604~pm ~0.0181$ </tex-math></inline-formula> and a root mean square error (RMSE) of <inline-formula> <tex-math>$0.0825~pm ~0.0039$ </tex-math></inline-formula>, demonstrating prediction accuracy comparable to random forest (RF) and higher than extreme gradient boosting (XGBoost) and multilayer perceptron (MLP), while providing improved physical interpretability. Additionally, the parameters learned by the model align closely with classical thermal fatigue failure theories, providing clear physical interpretability. These findings indicate that the proposed method offers a novel technical approach to the thermal fatigue life prediction of solder joints in electronic packaging, with significant engineering potential.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2015-2024"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advancement in Hermetic Packaging for MEMS: An Al–Si–Ge Ternary Eutectic Bonding Approach With Interring Groove Structure MEMS密封封装的进展：一种Al-Si-Ge三元共晶键合方法

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-08-12 DOI: 10.1109/TCPMT.2026.3723173

Bangda Xue;Wenhua Shi;Wenkui Lin;Weiming Lv;Lei Yang;Zhongming Zeng;Hao Zhai

{"title":"Advancement in Hermetic Packaging for MEMS: An Al–Si–Ge Ternary Eutectic Bonding Approach With Interring Groove Structure","authors":"Bangda Xue;Wenhua Shi;Wenkui Lin;Weiming Lv;Lei Yang;Zhongming Zeng;Hao Zhai","doi":"10.1109/TCPMT.2026.3723173","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3723173","url":null,"abstract":"The enhancement of hermetic packaging is of pivotal significance for the advancement of inertial sensor devices, including MEMS gyroscopes. The aluminum–germanium (Al–Ge)-based eutectic bonding technology, renowned for its superior sealing and mechanical strength, has the capacity to significantly enhance the reliability and efficiency of these devices. This study introduces a hermetic packaging technology based on an Al–silicon–Ge (Al–Si–Ge) ternary eutectic bonding system that employs a dual-seal-ring and interring groove (IRG) structure. A series of studies were conducted on the morphology of the sealing rings, the helium leakage rates of the packaging units, and the shear strength. These were then compared with the traditional Al–Ge binary system bonding. The results indicate that, under the same bonding parameters, the cross sections of sealing rings in the Al–Si–Ge ternary system exhibit distinct eutectic phases, and the packaging performance in terms of helium leak hermeticity and shear strength surpasses that of the traditional binary system. The performance of the getter-free system is found to meet the MIL-STD-883 with a leak rate of (3.42 ± 0.10) <inline-formula> <tex-math>$times 10^{-9}$ </tex-math></inline-formula> atm <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> cc/s and a shear force of (<inline-formula> <tex-math>$52.62~pm ~1.61$ </tex-math></inline-formula>) kilogram force (kgf). Furthermore, the IRG packaging structure proposed in this article has been shown to enhance the sealing and mechanical strength of the packaging cavity. The research findings emphasize the positive impact of the Al–Si–Ge ternary eutectic bonding process and the innovative packaging structure design on the hermetic performance of MEMS devices, offering a new technological approach to improving the performance and lifespan of MEMS.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2173-2181"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing 高性能计算中垂直功率传输的综合设计框架

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-08-18 DOI: 10.1109/TCPMT.2026.3724907

Sriharini Krishnakumar;Yaroslav Popryho;Mingeun Choi;Ramin Rahimzadeh Khorasani;Madhavan Swaminathan;Satish Kumar;Inna Partin-Vaisband

{"title":"A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing","authors":"Sriharini Krishnakumar;Yaroslav Popryho;Mingeun Choi;Ramin Rahimzadeh Khorasani;Madhavan Swaminathan;Satish Kumar;Inna Partin-Vaisband","doi":"10.1109/TCPMT.2026.3724907","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3724907","url":null,"abstract":"Power delivery—including high-to-low voltage conversion, complex power distribution across heterogeneously integrated chiplets, and efficient interconnect allocation—remains a critical bottleneck in high-performance computing (HPC) systems. Existing vertical power-delivery (VPD) solutions are estimated to achieve less than 70% system-wide end-to-end power-delivery efficiency, defined from platform input power to delivered on-chip load power, with substantial energy lost as heat before reaching on-chip point-of-loads (POLs). In the absence of systematic design methodologies, evaluating power quality, exploring architectural alternatives, and optimizing performance rely on computationally prohibitive simulations, resulting in suboptimal designs. This article introduces an end-to-end scalable power-delivery framework for HPC systems, including distributed VPD (DVPD) architecture, DVPD design optimization methodology, and analytical models. The framework leverages substrate-embedded GaN power switches together with arrays of unit inductors and capacitors tailored for HPC applications. Multistage power conversion schemes (48-to-1 V, 48-to-24-to-1 V, and 48-to-12-to-1 V) are explored, with system-wide voltage drops and power losses evaluated under steady-state conditions. Design specifications for passive and active devices are formulated to meet next-generation efficiency targets. For the 48-to-1 V case, the proposed DVPD approach achieves 84% system-wide efficiency while occupying 54% of the area beneath the load system, with efficiency increasing to 87.6% at 75% area utilization across a 1–50 kW load range. Furthermore, steady-state voltage drops peak at 2.7% and transient drops at 9% (without decoupling capacitors), demonstrating the viability of DVPD for future wafer-scale HPC platforms.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2089-2102"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11658737","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-09-22 DOI: 10.1109/TCPMT.2026.3728933

引用次数: 0

Self-Aligned Low-Temperature Cu--Cu Direct Bonding in Air 自对准低温Cu- Cu在空气中的直接键合

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-08-24 DOI: 10.1109/TCPMT.2026.3720603

Kexuan Zhang;Fangcheng Cao;Xingyan Zhao;Yang Qiu;Shaonan Zheng;Yuan Dong;Qize Zhong;Ting Hu

{"title":"Self-Aligned Low-Temperature Cu--Cu Direct Bonding in Air","authors":"Kexuan Zhang;Fangcheng Cao;Xingyan Zhao;Yang Qiu;Shaonan Zheng;Yuan Dong;Qize Zhong;Ting Hu","doi":"10.1109/TCPMT.2026.3720603","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3720603","url":null,"abstract":"This study presents a self-aligned, low-temperature Cu–Cu direct bonding process that integrates a nonplanar Cu pair design based on photosensitive polyimide (PSPI) with straightforward ethylene glycol-enabled surface activation. High-quality bonding with shear strength of 27.18 MPa is achieved at <inline-formula> <tex-math>$160~^{circ }$ </tex-math></inline-formula>C under ambient atmospheric conditions. Comparative analysis of the Cu surface before and after treatment indicates ethylene glycol not only reduces Cu2O to Cu but also minimizes surface roughness effectively. Cross-sectional observations confirm that the sloped sidewall profile remains intact without noticeable cracks or delamination after bonding, although the sloped angle decreases to 39.2° from 45° due to compressive load. Comprehensive daisy-chain measurements demonstrate an obvious linear relationship between the measured resistance and the number of serially connected Cu pairs, implying favorable fabrication and bonding uniformity. Electrical performance of the bonded stack is proven to be reliable across an extended temperature range from <inline-formula> <tex-math>$- 50~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2200-2203"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Capillary-Assisted Automated Silver Direct Bond of Chip-on-Chip Through a Novel Sponge-Dipping Approach 一种新型海绵浸渍方法的毛细管辅助银片直接键合

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-08-11 DOI: 10.1109/TCPMT.2026.3721915

Jonas Weber;Hubert Rauh;Jürgen Leib;Martin März

{"title":"Capillary-Assisted Automated Silver Direct Bond of Chip-on-Chip Through a Novel Sponge-Dipping Approach","authors":"Jonas Weber;Hubert Rauh;Jürgen Leib;Martin März","doi":"10.1109/TCPMT.2026.3721915","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3721915","url":null,"abstract":"Silver direct bonding is an organic-free joining technique for chip-on-chip power electronic assemblies that eliminates the need for sinter paste, but also removes the temporary chip-tacking function that the paste normally provides. This article presents a simple and cost-effective sponge-dipping approach, in which a water-soaked sponge module is integrated into a conventional pick-and-place process. The resulting capillary forces retain the chips in position during multichip stacking without requiring a dedicated dispensing unit or hydrophobic surface patterning. Experiments on five-chip stack assemblies with three chip footprints (<inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula>, <inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$10times 10$ </tex-math></inline-formula> mm<inline-formula> <tex-math>${}^{2}$ </tex-math></inline-formula>) show that capillary assistance increases the yield to 100% for the two larger footprints, eliminates complete placement failures across all chip sizes, and reduces misalignment. Scanning acoustic microscopy (SAM) and cross-sectional scanning electron microscope (SEM)/energy-dispersive X-ray (EDX) analyses reveal no significant mineral contamination at the Ag–Ag bonding interface, indicating that the applied deionized (DI) water does not measurably affect bond quality under the tested conditions.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2182-2191"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11646847","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Scalable Stress Recovery Technique for Hybrid Bonding in Chiplet-Based Systems 基于芯片的混合键合系统的可扩展应力恢复技术

IF 3.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2026-09-01 Epub Date: 2026-08-14 DOI: 10.1109/TCPMT.2026.3723892

Yin-Da Wang;Qiwei Zhan;Hao-Xuan Zhang;Yu Zhu;Wen-Yan Yin

{"title":"A Scalable Stress Recovery Technique for Hybrid Bonding in Chiplet-Based Systems","authors":"Yin-Da Wang;Qiwei Zhan;Hao-Xuan Zhang;Yu Zhu;Wen-Yan Yin","doi":"10.1109/TCPMT.2026.3723892","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3723892","url":null,"abstract":"The post-Moore era has ushered in the development of multichip and multistack chiplet-based systems, with hybrid bonding (HB) serving as a method to achieve ultrafine pitch interconnections. This article presents a scalable stress recovery technique designed for thermal–mechanics analysis of HB. Our method enhances the accuracy of <inline-formula> <tex-math>$C^{-1}$ </tex-math></inline-formula> continuous stress on element boundaries within finite elements by employing postprocessing on the displacement-based finite-element method (FEM). This recovery technique focuses solely on solving local problems near the finite element, making it well-suited for deployment in multicore parallel application scenarios. We illustrate the effectiveness of this approach through numerical examples involving chip-to-wafer (C2W) and die-to-wafer (D2W) HB cases, analyzing its accuracy, efficiency, and scalability. Overall, our method demonstrates advantages over traditional approaches, achieving a 90.9% reduction in computational scale, a 95.4% decrease in running time, and a 44.5% reduction in memory usage, all while maintaining the same accuracy requirements. Furthermore, we evaluate the thousand-core parallel capability of this technique on a high-performance computing (HPC) platform, underscoring its application in simulating ultrahigh-density chiplet interconnections and evaluating the potential risk of bonding voids from simulation.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2148-2156"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0