IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Advanced Photonic Debonding Using Solution-Processed Ag Nanoparticle/Cu-Precursor Hybrid Light-Absorbing Layers for Wafer-Level Packaging","authors":"Soomin Song","doi":"10.1109/TCPMT.2026.3718409","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3718409","url":null,"abstract":"This study presents an advanced photonic debonding (APDB) process for wafer-level packaging using millisecond-intense pulsed light (IPL) irradiation and a solution-processed Ag nanoparticle (NP)/Cu-precursor hybridIPL-absorbing layer (IAL, MyCin–C). The notation 7:3 denotes the feed mass ratio of Ag NPs to Cu(<inline-formula> <tex-math>$mathrm{NO}_{textrm {3}})_{2}~{cdot }~3$ </tex-math></inline-formula>H₂O precursor and does not represent the final elemental Ag:Cu ratio. A 2-butoxyethanol-based formulation provided improved wettability and coating uniformity compared with a DI water-based formulation, resulting in a more homogeneous photothermal response and improved carrier-glass reuse. Among the investigated formulations, the 7:3 hybridIAL exhibited broadband optical absorption of approximately 95% and the highest transient photothermal response. Wafer-level debonding was demonstrated on a 150-mm silicon wafer thinned to approximately <inline-formula> <tex-math>$30~mu $ </tex-math></inline-formula>m using a single IPL pulse at 4 J/cm2 with a pulse duration of 1 ms. In contrast, an Ag-only NPIAL fabricated under comparable coating, bonding, and wafer-processing conditions did not achieve debonding at 4, 5, or 6 J/cm², and carrier-glass cracking occurred at 6 J/cm2. These results establish a direct relationship among absorber formulation, coating morphology, optical absorption, transient photothermal response, and interfacial separation behavior. Post-debonding optical microscopy (OM), scanning electron microscopy (SEM), FIB-SEM, and semiquantitative EDS analyses showed no pronounced cracking, interfacial delamination, structural deformation, or major redistribution of the detected elements within the analyzed regions. The total device multilayer-stack thickness remained comparable before and after debonding, and neither Ag nor Cu was detected on the analyzed wafer regions under the applied EDS conditions. In addition, the 2-butoxyethanol-based carrier glass retained high optical transmittance over repeated debonding–cleaning–reuse cycles. These results demonstrate the feasibility of localized, single-pulse IPL debonding for thin-wafer handling and advanced semiconductor packaging under the tested process conditions.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2157-2172"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wideband Intelligent Reflecting Surface for 6G Indoor Communication: Design Considerations and Performance Analysis","authors":"V. Renuga Kanni;Esther Florence Sundarsingh;R. Vimal Samsingh","doi":"10.1109/TCPMT.2026.3720464","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3720464","url":null,"abstract":"This article presents the development of intelligent reflecting surfaces (IRSs) aimed at enhancing 6G indoor communication. The unit-cell design incorporates a circular reflecting element, enhanced with circular rings and a clover-diamond slot. Constructive interference is achieved with a phase tolerance of ±20° within the 11.8–14.37-GHz band, ensuring optimal signal reflection under normal incidence. Directivity is recorded as 19.72 dB, which proves that the proposed IRS has a wide bandwidth. Maximum sidelobe level is found to be −27.28 dB. Specific absorption rate (SAR), recorded for the first time, is found to be 0.139 W/kg for 1-g tissue, which complies with the IEEE standard and makes it suitable for use in indoor applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2103-2109"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental Optimization of Liquid--Vapor Phase Separation in High Heat Flux Capillary-Driven μ-Coolers","authors":"Kaiying Jiang;Heungdong Kwon;Mehdi Asheghi;Kenneth Goodson","doi":"10.1109/TCPMT.2026.3697351","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3697351","url":null,"abstract":"Capillary-driven two-phase cooling offers an effective and energy-efficient solution for high-heat-flux thermal management in compact electronic systems. To enhance boiling performance, it is critical to separate the liquid supply and vapor escape pathways. Prior work has demonstrated liquid–vapor phase separation in copper inverse opals (CuIOs), a 160–500-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-wide bridge <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>-cooler. To area scale such a <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>-cooler, a silicon-based 3-D manifold is a promising option due to fine microchannel features that enable capillary wicking over longer distances. This study presents design optimization, performance data, and modeling results for capillary-based <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>-coolers with a silicon 3-D manifold. By varying the vapor extraction pathways spacing (80, 200, 400, 600, 800 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m) between liquid delivery microchannels, we show the impact of effective wicking length on thermal performance. The 3-D manifold with 400-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m vapor spacing achieves the best overall performance: critical heat flux (CHF) of up to 580 Wcm^–2 with a low superheat of <inline-formula> <tex-math>$5.4~^{circ }$ </tex-math></inline-formula>C, yielding a thermal resistance less than 0.01 cm²KW⁻¹ with a very small flow rate of 3.37 gmin⁻¹. This optimized geometry maximizes active boiling area while maintaining sufficient capillary-driven liquid replenishment. Too-small spacing leads to flooding and a reduction in effective area available for two-phase boiling, while too-large spacing limits lateral liquid transport and causes dry out. The experimental results validate the area-scaling model and confirm its effectiveness as a design tool for a large-area cooler.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2046-2053"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Effect of Particle Pollution on the Temperature Rise of Assembled Printed Circuit Boards","authors":"Shengjie Liu;Hansheng Zhang;Fan Zhang;Yin Luo;Zhengyang Cui;Yilin Zhou","doi":"10.1109/TCPMT.2026.3666180","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3666180","url":null,"abstract":"During the long-term operation of electronic devices, airborne dust particles are carried by airflow into the interior of the equipment, where they deposit on the surfaces of printed circuit boards (PCBs) and their assembled electronic components. This deposition obstructs normal heat dissipation, thereby increasing the risk of component failure. To investigate the effect of dust accumulation on the temperature rise of PCBs with integrated electronic components, this study proposes an innovative thermal modeling approach by treating deposited dust as an equivalent porous medium film. Gradient-density quartz particle deposition experiments combined with image recognition techniques were employed to determine the porosity of the dust layer. Based on thermal resistance theory analysis, the equivalent thermal conductivity of the film was derived. A finite element method (FEM)-based thermal simulation model was developed to systematically study the influence of dust coverage density on the surface temperature of PCBs assembled with various power levels of electronic components. The simulation results were experimentally validated through quartz particle deposition and temperature rise measurements. Experimental results indicate that the surface temperature of the circuit board increases significantly with higher particle coverage density. As the dust coverage density increases from dust-free condition to 1200 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>g/cm², the predicted temperature rise of PCB-mounted chips is an average temperature rise of <inline-formula> <tex-math>$3.6~^{circ }$ </tex-math></inline-formula>C, showing excellent agreement with experimental measurements, with an overall deviation within −3%<inline-formula> <tex-math>$sim!+4$ </tex-math></inline-formula>%. Under the same coverage density, the temperature rise is nearly identical across electronic components with different power ratings. Finally, a theoretical temperature rise model for dust-covered components was established by fitting experimental data. This study demonstrates that modeling deposited particles as a porous medium film provides an efficient and accurate method for predicting the permissible dust coverage threshold of electronic products based on allowable temperature rise limits.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2076-2088"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2026.3728929","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3728929","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"C2-C2"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703949","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2026.3728931","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3728931","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2208-2208"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703882","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of the Interface Reliability of Multilevel Stacked Copper Microvias: Modeling and Simulation","authors":"Syed Mujahid Abbas;Qiang Yu;Michael Pecht","doi":"10.1109/TCPMT.2026.3704315","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3704315","url":null,"abstract":"Microvias serve as electrical interconnections between conducting layers of laminates in high-density interconnect printed circuit boards (PCBs). However, stacked microvias can interfacially separate or crack due to fatigue if not properly designed and manufactured. In this article, seven different types of commercially used microvia configurations, e.g., stacked, staggered, semi-stacked, stacked-on buried via (BV), and stacked offset to BVs, are modeled using finite element analysis to investigate the mechanisms of failure. The simulation results strongly correlate with experimental data, and a novel Coffin–Manson factor was developed to predict the fatigue life of the microvia interface. Insights into the interfacial separation and target pad cracking are then presented.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2054-2067"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact IPD Bandpass Filter With Wide Upper Stopband in GaAs Technology","authors":"Gang Zhang;Yuanming Yan;Yichuan Jiang;Zehua Liu;Na Li;Kam-Weng Tam;Shichang Chen","doi":"10.1109/TCPMT.2026.3716634","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3716634","url":null,"abstract":"A compact bandpass filter (BPF) featuring high selectivity and a wide stopband has been proposed and realized using gallium arsenide (GaAs) integrated passive device (IPD) technology. A developed topology consisting of a T-shape topology and a paralleled capacitor is introduced in this BPF. The T-shape topology can achieve a triple-mode filter response and generate two transmission zeros (TZs) at both sides of the passband, significantly improving the frequency selectivity. This paralleled capacitor can introduce an additional TZ to widen the stopband. For validation, the proposed BPF centered at 3.65 GHz with a 3-dB fractional bandwidth (FBW) of 64% has been fabricated and measured. The measured results show a wide stopband rejection of −20 dB up to 36.7 GHz (about <inline-formula> <tex-math>$10f_{0}$ </tex-math></inline-formula>) and a compact size of <inline-formula> <tex-math>$0.068lambda _{0} times 0.052lambda _{0}$ </tex-math></inline-formula>.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2110-2113"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip-Chip Bonding of 3-D Copper Compressible Microinterconnects for Cryogenic Electronic Packaging","authors":"Euichul Chung;Michael A. Nieves Calderon;Zhonghao Zhang;M. Mert Torunbalci;Martin Damyanov;Georg Aigeldinger;Michael C. Hamilton;Muhannad S. Bakir","doi":"10.1109/TCPMT.2026.3720606","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3720606","url":null,"abstract":"A free-standing copper compressible microinterconnect (CMI) for cryogenic applications was fabricated, flip-chip bonded, and its electrical and mechanical characteristics were analyzed in this letter. To address the increasing demand for reliable off-chip interconnects in cryogenic electronic packaging, we present a pressure-contact-based 3-D copper CMI that exhibits linear elastic behavior, requires a relatively low bonding force, and offers reworkability. Ex-situ resistance measurements at room temperature and in-situ measurements from 300 K down to 14 mK were performed on a flip-chip bonded CMI array, revealing up to a 39.6% reduction in resistance upon cool down. Furthermore, a mechanistic investigation of the flip-chip bonding process was conducted, including force–displacement measurements, along with force–stress analysis using finite element analysis (FEA), to verify robustness.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2204-2207"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-Packaged All-Port CM Reflectionless Balanced Filtering Power Divider Based on SISPSL Structure With Broadband CM Absorption","authors":"Du Chen;Han-Peng Zheng;Xu Jiang;Feng Wei;Hong-Yu Liu","doi":"10.1109/TCPMT.2026.3685442","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3685442","url":null,"abstract":"In this article, a self-packaged all-port common-mode (CM) reflectionless balanced filtering power divider (FPD) with high CM suppression and broadband CM absorption is proposed based on substrate-integrated suspended parallel stripline (SISPSL) for the first time. A ring resonator is utilized to provide differential-mode (DM) filtering and power division response based on the Wilkinson power-divider structure. Two transmission zeros (TZs) are generated by employing a ring resonator, significantly improving DM frequency selectivity. Based on the anti-phase-fed double-sided parallel-stripline (DSPSL) structure, a high CM suppression without affecting the DM performance is achieved in the proposed balanced FPD. Furthermore, the CM energy is absorbed by the resistors loaded between the transmission lines, thereby achieving broadband CM reflectionless characteristics. To validate the design, a prototype of the CM reflectionless balanced FPD was designed and fabricated. The measured results show good consistency with simulated data, confirming the feasibility and effectiveness of the proposed approach.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2127-2134"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}