IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献_第2页

Broadband Characterization of Interconnects in Die-Embedded Glass Interposer

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-05 DOI: 10.1109/TCPMT.2025.3548082

Serhat Erdogan;Xiaofan Jia;Xingchen Li;Mohanalingam Kathaperumal;Ravi Agarwal;Madhavan Swaminathan

{"title":"Broadband Characterization of Interconnects in Die-Embedded Glass Interposer","authors":"Serhat Erdogan;Xiaofan Jia;Xingchen Li;Mohanalingam Kathaperumal;Ravi Agarwal;Madhavan Swaminathan","doi":"10.1109/TCPMT.2025.3548082","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3548082","url":null,"abstract":"This article presents a broadband <italic>S</i>-parameter characterization of embedded and vertical transitions between chips embedded in a glass interposer. We discuss the opportunities that die-embedded glass interposer presents for heterogeneous integration by enabling vertical and lateral die-to-die interconnects with increased bandwidth and reduced length, as well as low-loss chip-to-interposer interconnects between RF chips and passives. Multiple back-to-back (B2B) chain structures with different lengths are designed on a high-resistivity silicon test die, which is embedded in the glass interposer with two redistribution layers (RDLs) with stacked microvias. The electrical characterization includes obtaining two-port <italic>S</i>-parameters (dc–170 GHz) of the stacked microvia interconnect by applying a two-step TRL de-embedding procedure to remove the chip-level and interposer-level transmission lines. Crosstalk measurements are also presented up to 50 GHz. Crosstalk for all chain structures is better than −30 dB at the near end and −25 dB at the far end. The measured <italic>S</i>-parameters of the interconnect show 0.2-dB insertion loss at 170 GHz. This represents the first broadband characterization results for chips embedded in the glass interposer.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"766-773"},"PeriodicalIF":2.3,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Efficiency Extraction Method for Thermal Network Model of Advanced Electronic Packages

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-03 DOI: 10.1109/TCPMT.2025.3547229

Ian Hu;Yu-Chih Kuo;Tian-Shiang Yang

{"title":"High-Efficiency Extraction Method for Thermal Network Model of Advanced Electronic Packages","authors":"Ian Hu;Yu-Chih Kuo;Tian-Shiang Yang","doi":"10.1109/TCPMT.2025.3547229","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3547229","url":null,"abstract":"To reduce the number of grids in numerical computations that involve multiple length scales, a compact thermal model of an electronic package is widely used for electronic system thermal design. This study was conducted according to development of libraries of physical models for an integrated design environment (DELPHI) procedure and extended to dual-chip application. A flip-chip chip-scale package (FCCSP) containing a single or dual chip was chosen as the test vehicle. A domain-knowledge-assisted sequential least-squares programming (SLSQP) technique is used to minimize the objective function; meanwhile, the genetic algorithm (GA) technique is used for comparison. This study examines how to use domain knowledge on initial condition settings when using SLSQP and how to increase spatial resolution to improve the network models effectively. It is found that using calculated 1-D thermal resistances as the initial estimates of the critical thermal resistance parameters can increase the accuracy of the network model training by SLSQP, which has accuracy similar to GA and much better computational efficiency. This study also demonstrates that the network model can be improved by systematically increasing its spatial resolution of the main heat dissipation path based on the errors observed in primary attempts, which has more benefits than increasing the spatial resolution of the surface having a larger temperature difference.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"716-724"},"PeriodicalIF":2.3,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Sensitive Data Labeling Strategy for Optimizing a Broadband Vertical Transition in W Band

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-03-03 DOI: 10.1109/TCPMT.2025.3547053

Weihong Liu;Shuai Zhang;Yanbo Zhao;Zhiyuan Qu;Miao Zhao

引用次数: 0

Multilayer Uniform Photoresist Coating on Silicon Wafers via Spin-Coupled Inkjet Printing

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-27 DOI: 10.1109/TCPMT.2025.3546272

Lei Zhang;Xiukun Wang;Tao Miao;Shenghua Guo;Yubo Tong

引用次数: 0

A High-Voltage Low-Dropout Regulator With Wide Ranges of Output Capacitance and Au80Sn20 Alloy Solder for Packaging 一种具有宽范围输出电容和 Au80Sn20 合金焊料的高压低压差稳压器，适用于封装

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-26 DOI: 10.1109/TCPMT.2025.3546032

Hua Fan;Xiaopeng Diao;Qi Wei;Quanyuan Feng

{"title":"A High-Voltage Low-Dropout Regulator With Wide Ranges of Output Capacitance and Au80Sn20 Alloy Solder for Packaging","authors":"Hua Fan;Xiaopeng Diao;Qi Wei;Quanyuan Feng","doi":"10.1109/TCPMT.2025.3546032","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3546032","url":null,"abstract":"This article presents the circuit design and the implementation of a low-dropout (LDO) regulator with high-voltage operation across a broad temperature range from <inline-formula> <tex-math>$- 55~^{circ } {mathrm {C}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$125~^{circ } {mathrm {C}}$ </tex-math></inline-formula>. The proposed LDO operates stably over wide ranges of output capacitance <inline-formula> <tex-math>$Crm _{OUT}$ </tex-math></inline-formula> (from 1 to <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>F) and effective series resistance (ESR; from tens of milliohms ceramic capacitor to several ohms aluminum electrolytic capacitor). This LDO consumes not more than 200-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A quiescent current. This low quiescent current is obtained by replacing the traditional high-voltage p-n-p bipolar power transistor with a p-type laterally diffused MOS (LDMOS) counterpart, reducing the quiescent current from tens of milliamperes to hundreds of microamperes. At the same time, the degradation of the transient response caused by the large gate capacitor of the p-type LDMOS power transistor is mitigated by an operational amplifier with a specially designed feedback path, class-AB bipolar driver, and dynamic bias. The measurement results show that when the load current jumps from 5 to 750 mA within <inline-formula> <tex-math>$3~mu text {s}$ </tex-math></inline-formula>, the output voltage overshoot remains as low as 50 mV with a <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>F of output capacitance <inline-formula> <tex-math>$Crm _{OUT}$ </tex-math></inline-formula>.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"774-781"},"PeriodicalIF":2.3,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bandpass Power Combined Amplifier Based on All-Ports Reflectionless Filtering Power Divider

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-25 DOI: 10.1109/TCPMT.2025.3545059

Guo-Qing Zhou;Jin Xu;Jia-Hao Su;Zi-Hao Zhou;Hui-Kun Yang;Shi-Xin Meng

{"title":"A Bandpass Power Combined Amplifier Based on All-Ports Reflectionless Filtering Power Divider","authors":"Guo-Qing Zhou;Jin Xu;Jia-Hao Su;Zi-Hao Zhou;Hui-Kun Yang;Shi-Xin Meng","doi":"10.1109/TCPMT.2025.3545059","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3545059","url":null,"abstract":"This article proposed a bandpass power combined amplifier (BPCA) based on an all-ports reflectionless filtering power divider (ARFPD). The ARFPD integrates the functions of filtering, power division/combination, and stopband signal absorption. In addition, to verify the proposed BPCA, a low-voltage 3–4GHz continuous Class-F power amplifier (PA) using a gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) was designed. The proposed BPCA has the characteristics of good filtering, harmonic suppression, and out-of-band absorption. To validate the proposed structure, the ARFPD, continuous Class-F PA, and BPCA in the 3–4GHz frequency range were fabricated and tested. The test results show that the ARFPD has an insertion loss of 3.8 dB, an input return loss of better than 11.6 dB across all frequency band (0–7 GHz),and an isolation and output return loss (ORL) of better than 18 dB within the band. The BPCA has achieved input and ORL better than 10 dB up to 8GHz, a maximum DE of 55.7%, a maximum <inline-formula> <tex-math>${P} _{text {out}}$ </tex-math></inline-formula> of 28.2 dBm, as well as a harmonic suppression level of 33dBc up to the tenth-harmonic frequency.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"792-799"},"PeriodicalIF":2.3,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Packaged Quasi-Circulators With Low NF and High Isolation Considering the Fabrication Tolerance

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-25 DOI: 10.1109/TCPMT.2025.3545060

Zhan Chen;Chun-Xia Zhou;Wen Wu

{"title":"Packaged Quasi-Circulators With Low NF and High Isolation Considering the Fabrication Tolerance","authors":"Zhan Chen;Chun-Xia Zhou;Wen Wu","doi":"10.1109/TCPMT.2025.3545060","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3545060","url":null,"abstract":"A packaged quasi-circulator (QC) with low noise, low insertion loss (IL), high isolation, and ease of manufacturing is proposed in this letter. The proposed QC is constructed by two couplers, three connecting transmission lines (TLs), and a common-emitter amplifier. High isolation between transmitter (TX) and receiver (RX) ports can be obtained using two-way signal cancellation by designing the amplitude and phase of the amplifier, while the noise from the amplifier is suppressed by the isolation of the coupler. The negative group delay (NGD) technique is introduced to change the slope of the loop phase to improve the TX-ANT transmission bandwidth. Furthermore, a reconfigurable load is employed to ensure high isolation within a wide frequency range since the isolation performance is sensitive to the fabrication tolerance. For design validation, a QC is designed and fabricated, which achieves the in-band TX-ANT IL of 2.1 dB, ANT-RX IL of 1.7 dB, and noise figure (NF) of 2.3 dB. By tuning two controlling voltage of varactors, the proposed circulator can obtain >40 dB isolation in the frequency range of 1.925–2.09 GHz.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"874-876"},"PeriodicalIF":2.3,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of Au Substrate Crystal Structure on Ag–Au Interdiffusion for WBG Packaging

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-25 DOI: 10.1109/TCPMT.2025.3545544

Bowen Zhang;Zhiheng Gao;Zhiyuan Zhao;Yi Liu;Daohang Li;Yun-Hui Mei

{"title":"Influence of Au Substrate Crystal Structure on Ag–Au Interdiffusion for WBG Packaging","authors":"Bowen Zhang;Zhiheng Gao;Zhiyuan Zhao;Yi Liu;Daohang Li;Yun-Hui Mei","doi":"10.1109/TCPMT.2025.3545544","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3545544","url":null,"abstract":"The rapid diffusion of Ag–Au usually results in weak interface joints, which significantly impacts the stability of wide bandgap (WBG) devices. Therefore, the interdiffusion mechanism at the atomic scale is essential to effectively inhibit excessive interdiffusion and ultimately achieve robust joints. Herein, die-attach samples were prepared by Au substrate with different crystal structures, in which the shear strength reached 43.5 and 34.4 MPa for Sample I and Sample II, respectively. The following crystal structures analysis confirms the sintered Sample I exhibited a higher interface connection rate (ICR) of 47% and lower Ag–Au interdiffusion thickness of <inline-formula> <tex-math>$0.2~mu $ </tex-math></inline-formula>m, both of which benefit the high-quality bonding. Compared to Sample II (~82.3%), the relatively low proportion of high-angle grain boundaries in Sample I (~81%) may inhibit interdiffusion and favor higher shear strength. Finally, molecular dynamics simulations (MDSs) were employed to better understand the performance difference between Sample I and Sample II. The simulation results reveal that the interdiffusion process tends to occur on Au substrates with small grain size, high-angle grain boundaries, high proportion of Au (111) plane, and elevated sintering temperatures. The proposed interdiffusion mechanism facilitates the development of die-attach through sintered Ag paste and Au metallization substrate, enhancing the reliable packaging of WBG devices.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"858-867"},"PeriodicalIF":2.3,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Gold-Silicon Eutectic Bonding to Realize the Symmetric Sensing Element of MEMS Piezoresistive Accelerometer 研究金-硅共晶键合以实现 MEMS 压阻式加速度计的对称传感元件

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-24 DOI: 10.1109/TCPMT.2025.3545281

Satyapal Singh;Vijay Kumar;Satinder Pal Singh;Navin Kumar

{"title":"Investigation of Gold-Silicon Eutectic Bonding to Realize the Symmetric Sensing Element of MEMS Piezoresistive Accelerometer","authors":"Satyapal Singh;Vijay Kumar;Satinder Pal Singh;Navin Kumar","doi":"10.1109/TCPMT.2025.3545281","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3545281","url":null,"abstract":"In this article, we investigate the intermixing of gold-silicon (Au-Si) across the Chromium (Cr) adhesion layer for Au-Si eutectic wafer bonding process development. In the first experiment, a stack of Cr and Au film was deposited on a silicon wafer, annealed in nitrogen gas ambient followed by the etching of unreacted Au, and investigated using optical microscopy, scanning electron microscopy (SEM), and energy-dispersive X-ray (EDX) analysis. The study confirms the intermixing and formation of Au-Si alloy. With that understanding, the Au-Si eutectic wafer bonding process was developed to realize a new symmetric sensing element for a micro electro mechanical systems (MEMS) piezoresistive accelerometer. This structure is realized by bonding two silicon wafers containing complementary halves of the structure and Au-Au facing bond interface. Each half was formed by deep reactive ion etching (DRIE) in silicon-on-insulator (SOI) wafers. The DRIE-based method results in a smaller die size and eliminates the need for corner compensation, unlike potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH)-based wet etching of silicon, and it enables the fabrication of even a cylindrical seismic mass. Post bonding, the interface was investigated using SEM, high-resolution X-ray imaging, and MIL-STD-883-based die shear test. The structure was successfully realized, achieving a 100% dicing yield of bonded wafers. For the 12 tested samples, the minimum, maximum, average, and standard deviation of die shear strength are 18.3, 40.1, 28.9, and 6.9 kgf, respectively. The average shear strength per unit of bond area is 27 MPa.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"697-705"},"PeriodicalIF":2.3,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

PIDDN: Pair-Image-Based Defect Detection Network With Template for PCB Inspection

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-21 DOI: 10.1109/TCPMT.2025.3543396

Qixing Jiang;Xiaojun Wu;Jinghui Zhou;Jun Cheng

{"title":"PIDDN: Pair-Image-Based Defect Detection Network With Template for PCB Inspection","authors":"Qixing Jiang;Xiaojun Wu;Jinghui Zhou;Jun Cheng","doi":"10.1109/TCPMT.2025.3543396","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3543396","url":null,"abstract":"The detection of defects has consistently posed a significant obstacle in the domain of machine vision, particularly in the context of the production of printed circuit board (PCB) components. To advance this technology, we present pair-image-based defect detection network (PIDDN), a novel framework that enables precise detection of object bounding boxes by utilizing a pair of images, with one designated as a template. The PIDDN approach involves the utilization of a Siamese neural network to simultaneously encode the features of the pair image, followed by the implementation of a template feature fusion network (TFFN) for integration. In addition, we introduce a template feature rectification module (TFRM) that aligns the feature maps of the pair-images attentively. We evaluate PIDDN on the DeepPCB dataset, and it achieves an impressive mean average precision (mAP) score of 99.6%. Furthermore, we present PairPCB, a complex and realistic dataset collected from real-world PCB production scenarios, to validate the effectiveness of template images. Extensive experiments demonstrate that PIDDN outperforms mainstream object detection algorithms with a 4.1% improvement in mAP. Code will be available at: <uri>https://github.com/QixingJiang/PIDDN</uri>.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"830-841"},"PeriodicalIF":2.3,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0