IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献_第3页

IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information

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IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-19 DOI: 10.1109/TCPMT.2025.3533109

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IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE 《部件、封装和制造技术》期刊为作者提供的信息

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IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-19 DOI: 10.1109/TCPMT.2025.3533107

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Automatic Test and Array Crosstalk Suppression Scheme for 3D-ICs With Inductively Coupled Interconnections

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-19 DOI: 10.1109/TCPMT.2025.3543763

Yang Cui;Zhuo Yang;Jie Xiong;Pan Zheng;Hao Gao;Wenwen Cai;Wei Zou;Xuecheng Zou;Li Zhang

{"title":"Automatic Test and Array Crosstalk Suppression Scheme for 3D-ICs With Inductively Coupled Interconnections","authors":"Yang Cui;Zhuo Yang;Jie Xiong;Pan Zheng;Hao Gao;Wenwen Cai;Wei Zou;Xuecheng Zou;Li Zhang","doi":"10.1109/TCPMT.2025.3543763","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3543763","url":null,"abstract":"Inductively coupled interconnection (ICI) is a wireless interchip interconnect technology for 3D-ICs, which offers cost savings and enhanced flexibility compared to through-silicon via (TSV). However, ICI presents unique key challenges, including high power consumption, reliability issues, and the complexity of wire bonding during the stacking process. To overcome these challenges, we propose a new packaging process, chip edge connection (CEC), and self-sorting and power-tuning circuits. We also propose an array crosstalk suppression (ACS) strategy. We showed the designed chip in a 180-nm CMOS process. The results show that the CEC process can establish a conductive channel at the chip edge. The self-sorting circuit can provide chip IDs without wire bonding. For four-layer stacked chips with a 50% single-layer misalignment, the power-tuning circuit reduces power consumption by 20.98%. Furthermore, the ACS scheme reduces the bit error rate (BER) to between <inline-formula> <tex-math>$1times 10^{-10}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$1times 10^{-12}$ </tex-math></inline-formula> at average misalignment levels of 10%–50% in the ICI channel.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"850-857"},"PeriodicalIF":2.3,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-19 DOI: 10.1109/TCPMT.2025.3533105

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Design and Implementation of High-Performance Tantalum Thin-Film Capacitors for Embedded Technologies

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-18 DOI: 10.1109/TCPMT.2025.3543402

Jiping Zhao;Shiheng Liu;Ruida Zhao;Jingyi An;Youlong Xu

{"title":"Design and Implementation of High-Performance Tantalum Thin-Film Capacitors for Embedded Technologies","authors":"Jiping Zhao;Shiheng Liu;Ruida Zhao;Jingyi An;Youlong Xu","doi":"10.1109/TCPMT.2025.3543402","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3543402","url":null,"abstract":"Embedding surface-mounted discrete capacitors into package substrates will result in more compact, efficient, and less-expensive electronic systems. Despite widespread awareness, embedded capacitor technology has not been widely used in electronic systems for the past two decades. The main reason is that embedded capacitors are still constrained by capacitance density, component size, and simplicity of integration into the package substrate. Tantalum (Ta) capacitors have the potential to provide the highest volumetric density among current capacitor technologies, but their bulky size and low-frequency stability limit their use in embedded technologies. In this article, a process for an ultrathin, high-density, thin-film capacitor (TFC) with excellent electrical properties using etched Ta foil as the anode is demonstrated. The equivalent series resistance (ESR) (7.5 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>) and leakage current (0.266 nA/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>F) of the Ta thin-film capacitor (TTFC) have been drastically reduced by modulating the chemical state of the Ta foil surface, optimizing the formation process and in situ treatment of the polymer cathode film. The capacitor (<inline-formula> <tex-math>$45~mu $ </tex-math></inline-formula>F, 10 V) has a volumetric density of <inline-formula> <tex-math>$9~mu $ </tex-math></inline-formula>F/mm3 with a thickness of only <inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>m and has a capacitance retention of approximately 33% higher than that of the commercial polymer Ta capacitors (CPTCs) up to 100 kHz. Apart from these excellent attributes, TTFCs prepared by electrochemical etching have good compatibility with the package substrate, which makes the TTFCs a promising candidate for embedded capacitors.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"868-873"},"PeriodicalIF":2.3,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Thermoelectric Generator With Boost Converter as a Portable Power Source for Battery Charging

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-18 DOI: 10.1109/TCPMT.2025.3543258

Soumyabrata Patra;Ajay Singh

{"title":"Thermoelectric Generator With Boost Converter as a Portable Power Source for Battery Charging","authors":"Soumyabrata Patra;Ajay Singh","doi":"10.1109/TCPMT.2025.3543258","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3543258","url":null,"abstract":"This research describes a portable power source that harvests energy from waste heat using a thermoelectric generator (TEG). The output voltage and power of TEG depend on the temperature gradient across it. This article describes an experimental investigation to keep the TEG’s cold end temperature low by using phase-changing material (PCM) in the heatsink. Using this setup for a 102 °C heat source results in a temperature gradient of 35 °C, allowing the energy harvesting device to generate 502 mW of power with a voltage of 410 mV. The output voltage of the energy harvesting device is made suitable for any electronics load or for battery charging by dc-dc boost converter. The proposed oscillator-driven self-start-up maximum power point tracking (MPPT) controlled dc-dc converter operates over a wide input voltage and power range of 210 mV (47 mW)–1.5 V (1.48 W). The circuit uses a unique technique for resampling of open circuit voltage which is determined by the change of duty cycle value from steady state. It eliminates the need for periodic sampling. The maximum efficiency of 76.5% at an input voltage of 300 mV and an input power of 242 mW demonstrates that the present work has the potential to become a future portable power bank.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"725-732"},"PeriodicalIF":2.3,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Impact on Reliability of Microvoids and β-Sn Anisotropy in Flip-Chip Bumps

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-14 DOI: 10.1109/TCPMT.2025.3542245

Kei Murayama;Kor Oon Lee;Haruo Shimamoto;Toshiaki Ono;Kiyoshi Oi;Sze Pei Lim;Yvonne Yeo;Keith Sweatman;Steven R. Martell;Masahiro Tsuriya

{"title":"Impact on Reliability of Microvoids and β-Sn Anisotropy in Flip-Chip Bumps","authors":"Kei Murayama;Kor Oon Lee;Haruo Shimamoto;Toshiaki Ono;Kiyoshi Oi;Sze Pei Lim;Yvonne Yeo;Keith Sweatman;Steven R. Martell;Masahiro Tsuriya","doi":"10.1109/TCPMT.2025.3542245","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3542245","url":null,"abstract":"The formation of small voids can occur in solder-based flip chip joints during the assembly process and a concern for certain applications that involve high electrical and thermal flux across the flip chip and also impact on electromigration (EM) in the joint. In this study, the impact of microvoids within flip-chip interconnections using Cu pillar bumps on EM resistivity was investigated. These microvoids can significantly affect the reliability of interconnections. To explore this, we intentionally created large voids in the solder bumps and measured the resulting differences in EM resistivity. The EM tests were conducted under specific conditions: at 150 °C and with a current density of 40 kA/cm2. Electron flow occurred in two directions—either from the Cu pad on the substrate side to the Cu pillar side (forward direction) or from the Cu pillar side to the substrate side (reverse direction). Surprisingly, the EM lifetime of interconnects with large voids was approximately 0.4 times shorter than that of interconnects with few or no voids, regardless of the electron flow direction. Further analysis by the simulation of current density distribution revealed that the presence of a 10-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-diameter void near the cathode interface led to a 1.5-fold increase in current density. Interestingly, this increase aligned well with Black’s empirical formula, which describes the relationship between EM lifetime and current density. In addition, the combination of c-axis of beta-Sn grain aligned with current direction around void at cathode interface, significantly accelerated EM test results.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"733-739"},"PeriodicalIF":2.3,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Study on Effect of Microstructure Evolution on Wafer Warpage for High-Temperature Annealed and Self-Annealed Copper Thin Films

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-10 DOI: 10.1109/TCPMT.2025.3540216

Prashant Kumar Singh;Maik Mueller;Holm Geisler;Michael Hecker;Meiqi Yu;Dirk Breuer;Kashi Vishwanath Machani;Karsten Meier;Frank Kuechenmeister;Karlheinz Bock

{"title":"Study on Effect of Microstructure Evolution on Wafer Warpage for High-Temperature Annealed and Self-Annealed Copper Thin Films","authors":"Prashant Kumar Singh;Maik Mueller;Holm Geisler;Michael Hecker;Meiqi Yu;Dirk Breuer;Kashi Vishwanath Machani;Karsten Meier;Frank Kuechenmeister;Karlheinz Bock","doi":"10.1109/TCPMT.2025.3540216","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3540216","url":null,"abstract":"Copper is widely used as an interconnect material in the back-end-of-line (BEoL) because it has high electrical conductivity and good electromigration failure resistance. Different applications, however, require a large number of ultrathick copper metal interconnects with varied line widths. A high wafer warpage is induced in the wafer due to the coefficient of thermal expansion (CTE) mismatch between the copper and the silicon during the BEoL process steps. High-temperature annealing and self-annealing of copper after deposition also result in high wafer warpage during fabrication. In this work, blanket copper thin films, and high-temperature annealed copper damascene interconnects with varied cross sections were investigated for their textural and microstructural evolution. The investigations show the directional changes of texture and grain size of copper cross sections at different annealing conditions. In addition, measurements also show variation in roughness and hardness magnitude for copper cross sections at different annealing conditions. In the case of blanket copper films, measurements confirmed the self-annealing behavior of copper within 48 h after deposition. In order to analyze a relationship between the stress state of the wafer and the microstructural evolution, the wafer warpage was measured after each BEoL process step. Through this investigation, it was found that the nonhomogenous stress concentrations with different cross sections are an important parameter for understanding the warpage change after high-temperature annealing processes. This study, moreover, gives insights into the structural change of the material during different annealing processes.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"576-590"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Facilitating Small-Pitch Interconnects With Low-Temperature Solid-Liquid Interdiffusion Bonding

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-10 DOI: 10.1109/TCPMT.2025.3540665

O. Golim;V. Vuorinen;M. Paulasto-Kröckel

{"title":"Facilitating Small-Pitch Interconnects With Low-Temperature Solid-Liquid Interdiffusion Bonding","authors":"O. Golim;V. Vuorinen;M. Paulasto-Kröckel","doi":"10.1109/TCPMT.2025.3540665","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3540665","url":null,"abstract":"The trend for 3-D heterogeneous integration drives the need for a low-temperature bonding process for high-density interconnects (HDIs). The Cu-Sn–In-based solid-liquid interdiffusion (SLID) is a promising option as a low-temperature bonding technique that offers better processing flexibility and relatively lower costs for chip-sized substrates when compared with hybrid bonding. In this letter, the low-temperature process was applied in a chip-to-chip bonding process. The test structures contain microbumps with 5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m width and 15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m pitch, mimicking state-of-the-art small-pitch interconnects. At the bonding temperature of 170°C, the process was completed within 5 min, while at 150°C extended bonding time was required to completely transform low-melting materials into intermetallic phases. Electrical characterization, performed using three test structures, estimated a single interconnect resistivity as low as 1.3e<inline-formula> <tex-math>$^{-7}~Omega $ </tex-math></inline-formula>m. This letter showcases the potential of the low-temperature SLID bond process for HDI applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"627-630"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10879407","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Transferring Fine-Pitch Cu Nanoparticle Bumps for Low-Temperature Cu-Cu Bonding in Chip-Scale Integration 在芯片级集成中转移细间距铜纳米粒子凸块以实现低温铜铜键合

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-02-07 DOI: 10.1109/TCPMT.2025.3540019

Shuaiqi Wang;Guisheng Zou;Rongbao Du;Lei Liu

{"title":"Transferring Fine-Pitch Cu Nanoparticle Bumps for Low-Temperature Cu-Cu Bonding in Chip-Scale Integration","authors":"Shuaiqi Wang;Guisheng Zou;Rongbao Du;Lei Liu","doi":"10.1109/TCPMT.2025.3540019","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3540019","url":null,"abstract":"Cu-Cu bonding using nanomaterials as an intermediate has attracted increasing attention for its eased requirements for bonding temperature and surface roughness. In this work, we developed a novel low-temperature Cu-Cu bonding technique using transferable Cu nanoparticle bumps. These nanoparticle bumps were first fabricated on donor substrate through pulsed laser deposition (PLD) and then transferred to the target chip by low-temperature pre-sintering (<inline-formula> <tex-math>$160~^{circ }$ </tex-math></inline-formula>C). The conventional dry transfer method using Si donor substrate was proved less feasible since the Cu-O–Si bond formed between Cu nanoparticles and SiO2 natural oxide layer on Si surface could cause transfer failure. An alternative wet transfer approach using Al as a sacrificial layer was proposed, wherein Al was dissolved by KOH solution and nanoparticle bumps were subsequently transferred. The self-release characteristic of wet transfer ensured a higher transfer yield. Transferred nanoparticle bumps on target chip maintained sintering activity and could realize reliable die shear strength (37.4 MPa) with target substrate at <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C, 15 MPa, and 5 min. The electrical resistance of sintered Cu joints showed negligible change before and after transfer. Joint strength decreased to 27.3 MPa due to oxidation after a thermal shock test (TST) (−65 to <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C) for 500 cycles. The transfer strategy could enable a more flexible application of nanomaterials for all-Cu interconnection in chip-scale integration.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"444-453"},"PeriodicalIF":2.3,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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