IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献_第3页

Two-Phase Liquid Cooling of Vertically Stacked High-Power Chips With Backside-Embedded Micro-Pin Fins 后置微针鳍垂直堆叠高功率芯片的两相液冷

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-11-12 DOI: 10.1109/TCPMT.2025.3631836

Huicheng Feng;Gongyue Tang;Xiaowu Zhang;Boon Long Lau;Ming Chinq Jong

{"title":"Two-Phase Liquid Cooling of Vertically Stacked High-Power Chips With Backside-Embedded Micro-Pin Fins","authors":"Huicheng Feng;Gongyue Tang;Xiaowu Zhang;Boon Long Lau;Ming Chinq Jong","doi":"10.1109/TCPMT.2025.3631836","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3631836","url":null,"abstract":"Three-dimensional integrated circuits (3-D ICs) enable a higher level of device integration for high-performance computing but also introduce significant thermal challenges due to increased power density. This letter demonstrates a two-phase liquid cooling approach for stacked high-power chips featuring backside-embedded micro-pin fins. Deionized water is circulated directly through the chips, providing internal cooling. The results show effective thermal management, with maximum power levels of 126–140 W achieved for Chips 1 and 2. Temperature fluctuations in the two-phase regime remain minimal, confirming the approach’s practicality. Chip 2 benefits from lower temperatures and higher heat transfer coefficients due to double-side cooling by water flowing through both itself and Chip 1. Increasing the flowrate reduces the chip temperatures and improves heat transfer coefficients but incurs higher pressure drops. The coefficient of performance (COP) decreases with flowrate but improves with heat power. These findings validate the feasibility of the proposed cooling method and establish a proof of concept for further integration in 3-D IC designs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 1","pages":"244-247"},"PeriodicalIF":3.0,"publicationDate":"2025-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146001880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE元件、封装与制造技术资讯汇刊

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-28 DOI: 10.1109/TCPMT.2025.3620696

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IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-28 DOI: 10.1109/TCPMT.2025.3620698

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EM-Induced Voiding Mechanism in Trapped Sn Phase Inside Massive Cu–Sn Compound 块状Cu-Sn化合物中被困Sn相的电磁致空化机制

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-23 DOI: 10.1109/TCPMT.2025.3624273

Po-Yu Chen;Chieh-Pu Tsai;Liu-Hsin-Chen Yang;Kai-Chi Lin;Chih-Wen Chiu;Chih-En Hsu;Chung-Yu Chiu;Jui-Shen Chang;Chen-Nan Chiu;David T. Chu;Yao-Chun Chuang;Cheng-Yi Liu

{"title":"EM-Induced Voiding Mechanism in Trapped Sn Phase Inside Massive Cu–Sn Compound","authors":"Po-Yu Chen;Chieh-Pu Tsai;Liu-Hsin-Chen Yang;Kai-Chi Lin;Chih-Wen Chiu;Chih-En Hsu;Chung-Yu Chiu;Jui-Shen Chang;Chen-Nan Chiu;David T. Chu;Yao-Chun Chuang;Cheng-Yi Liu","doi":"10.1109/TCPMT.2025.3624273","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3624273","url":null,"abstract":"This letter proposes a detailed analysis of the electromigration (EM)-induced voiding process in current-stressed Cu pillar/solder/Cu pad bumps, focusing on the amount and locations of void formation. Severe voiding primarily occurs within the Sn phase, which becomes trapped due to the uneven growth of a massive Cu<inline-formula> <tex-math>${}_{mathbf {6}}$ </tex-math></inline-formula> Sn<inline-formula> <tex-math>${}_{mathbf {5}}$ </tex-math></inline-formula> intermetallic compound. This phenomenon is identified as a crucial factor leading to EM failure and a reduced bump lifetime. The voiding in the trapped Sn phase is attributed to two main mechanisms: 1) the formation of Sn vacancies due to backfilling Sn flux as Cu pads are consumed and 2) the nonconservative volume change associated with the transformation of Sn phase into Cu<inline-formula> <tex-math>${}_{mathbf {6}}$ </tex-math></inline-formula>Sn<inline-formula> <tex-math>${}_{mathbf {5}}$ </tex-math></inline-formula> phase. The uneven growth of the massive Cu<inline-formula> <tex-math>${}_{mathbf {6}}$ </tex-math></inline-formula>Sn<inline-formula> <tex-math>${}_{mathbf {5}}$ </tex-math></inline-formula> compound is linked to the preferential dissolution of Cu fluxes, which are driven by the anisotropic diffusivity of Sn within its lattice and the divergence of atomic fluxes at Sn grain boundaries.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 12","pages":"2797-2800"},"PeriodicalIF":3.0,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Integrated Metal-Lidded Microfluidic Cooling on a High-Power AI Chip Using Confined Two-Phase Liquid Jet With Dielectric Fluid R1233zd(E) 基于介电流体R1233zd(E)的高功率AI芯片金属盖集成微流控冷却

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-20 DOI: 10.1109/TCPMT.2025.3623470

Gopinath Sahu;Sidharth Rajeev;Duc Hoang;Harish Kumar Lattupalli;Srikanth Rangarajan;Bahgat G. Sammakia;Scott Schiffres;Tiwei Wei

{"title":"Integrated Metal-Lidded Microfluidic Cooling on a High-Power AI Chip Using Confined Two-Phase Liquid Jet With Dielectric Fluid R1233zd(E)","authors":"Gopinath Sahu;Sidharth Rajeev;Duc Hoang;Harish Kumar Lattupalli;Srikanth Rangarajan;Bahgat G. Sammakia;Scott Schiffres;Tiwei Wei","doi":"10.1109/TCPMT.2025.3623470","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3623470","url":null,"abstract":"Innovative thermal management solutions are required to maintain a lower operating temperature of current lidless packages of AI chips. This study systematically investigates direct-on-chip multiliquid jets cooling over a 2.5-D interposer package using dielectric fluid. A compact metallic and lid-compatible manifold is proposed using 3-D printing technology with alternating impinging and draining nozzles, matching the dimensions of NVIDIA V100 chip. The fabricated manifold is mounted over the stiffener and mechanically pressurized with top cover plate and screw arrangement to ensure mechanical robustness and leak proof operation. A dielectric fluid R1233zd(E) is used as a working fluid at a saturation temperature of <inline-formula> <tex-math>$37.5~^{circ }$ </tex-math></inline-formula>C. Operating GPU temperature is experimentally measured for various flow rates, and power load up to thermal design power of 300 W using embedded sensor within the device. The finding under two-phase operation reveals a significantly lower temperature, measuring lowest thermal resistance of ~0.05 K/W with excellent response for step variation in power maps. This enhanced thermal dissipation at the chip level facilitates the compact lidded manifold package and next-generation AI chip.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 12","pages":"2789-2792"},"PeriodicalIF":3.0,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Dual-Wideband Bandpass Filter in Single SIW Cavity for 5G mmWave Systems 5G毫米波系统单SIW腔双宽带带通滤波器

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-17 DOI: 10.1109/TCPMT.2025.3622728

Guangwei Fan;Xiaohuai He;Dawei Ding

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A Broadband Dual-Component Magnetic Probe With a New Structural Design for EMI Diagnostics 一种新型电磁干扰诊断结构的宽带双分量磁探头

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-09 DOI: 10.1109/TCPMT.2025.3619541

Enming Luo;Xinyu Lu;Xiyou Sun;Lei Wang

{"title":"A Broadband Dual-Component Magnetic Probe With a New Structural Design for EMI Diagnostics","authors":"Enming Luo;Xinyu Lu;Xiyou Sun;Lei Wang","doi":"10.1109/TCPMT.2025.3619541","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3619541","url":null,"abstract":"This work develops a broadband dual-component magnetic probe with a new structural design, tailored for electromagnetic interference (EMI) diagnostic applications. Unlike the conventional dual-component magnetic probes that measure the <inline-formula> <tex-math>${H} _{x}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${H} _{y}$ </tex-math></inline-formula> field components, the proposed probe employs a new detection architecture capable of simultaneously measuring two orthogonal <inline-formula> <tex-math>${H} _{y}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${H} _{z}$ </tex-math></inline-formula> field components. The probe structure comprises a new detection architecture, a pair of striplines, two ground planes, and a pair of SubMiniature version A (SMA) connectors. This configuration enables concurrent measurement of the <inline-formula> <tex-math>${H} _{y}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${H} _{z}$ </tex-math></inline-formula> field components. To validate the design, the proposed probe was fabricated on a four-layer printed circuit board (PCB), evaluated through simulations using high-frequency electromagnetic simulation software, as well as measurements via a self-developed near-field measurement system with two distinct calibration kits (microstrip line and slot-line). Both simulated and experimental results demonstrate that the probe can not only have a wider operational bandwidth (<inline-formula> <tex-math>$4sim 15$ </tex-math></inline-formula> GHz) but also realize simultaneous measurement of two orthogonal <inline-formula> <tex-math>${H} _{y}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${H} _{z}$ </tex-math></inline-formula> field components.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 11","pages":"2542-2545"},"PeriodicalIF":3.0,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145584595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Slow Wave Power Divider Based on the HISL Platform 基于HISL平台的慢波功率分配器

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-07 DOI: 10.1109/TCPMT.2025.3618951

Huajiao Shen;Fanyi Meng;Yongqiang Wang;Kaixue Ma

{"title":"A Slow Wave Power Divider Based on the HISL Platform","authors":"Huajiao Shen;Fanyi Meng;Yongqiang Wang;Kaixue Ma","doi":"10.1109/TCPMT.2025.3618951","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3618951","url":null,"abstract":"This letter proposes a slow wave structure based on inductive-loading and applies it to the design of a miniaturized power divider. By adopting the capacitance and inductive-loading technology, the slow wave transmission line has a large slow wave coefficient. The proposed slow wave transmission line is based on the hybrid integrated suspended line (HISL) platform. The overall structure is a multilayer structure. The core layer slow wave structure is based on double-sided printed circuit board (PCB) circuit processing, and the remaining four layers are metal boards. The overall structure has good mechanical strength and the advantage of self-packaging based on multilayer. The designed slow wave power divider has a central operating frequency of 0.7 GHz and a circuit area of <inline-formula> <tex-math>$13.49times 12.06$ </tex-math></inline-formula> mm, i.e., <inline-formula> <tex-math>$0.036lambda $ </tex-math></inline-formula>g <inline-formula> <tex-math>$times 0.033lambda $ </tex-math></inline-formula>g, where <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>g is the guided wavelength at the center frequency.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 11","pages":"2539-2541"},"PeriodicalIF":3.0,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145584600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Ultralow-Temperature Deposition and Enhanced Bonding of SiCN Films for Advanced 3-D Integration 用于先进三维集成的SiCN薄膜的超低温沉积和增强键合

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-03 DOI: 10.1109/TCPMT.2025.3617495

Yeonju Kim;Kyungmin Shin;Donghyeok Choi;Jongshin Hyun;Byungjoo Jin;Jong Kyung Park

{"title":"Ultralow-Temperature Deposition and Enhanced Bonding of SiCN Films for Advanced 3-D Integration","authors":"Yeonju Kim;Kyungmin Shin;Donghyeok Choi;Jongshin Hyun;Byungjoo Jin;Jong Kyung Park","doi":"10.1109/TCPMT.2025.3617495","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3617495","url":null,"abstract":"This study explores the potential of SiCN films as a low-temperature alternative to SiO<sub>2</sub> insulators for hybrid bonding in 3-D integration. SiCN films were deposited at <inline-formula> <tex-math>$180~^{circ }$ </tex-math></inline-formula>C and <inline-formula> <tex-math>$350~^{circ }$ </tex-math></inline-formula>C to investigate the effects of deposition temperature and composition on bonding performance. By optimizing precursor flow rates, we tailored the film properties, enhancing Si dangling bonds crucial for bonding. To achieve ultralow-temperature bonding below <inline-formula> <tex-math>$100~^{circ }$ </tex-math></inline-formula>C, O<sub>2</sub> plasma and potassium hydroxide (KOH) surface treatments were employed, significantly improving bonding interfaces by increasing Si-OH groups on the surface. Our results demonstrate that SiCN films deposited at low temperatures can achieve bonding characteristics comparable to those of high-temperature films. The enhanced bonding performance is attributed to surface treatments that mitigate hydrogen content and promote Si-OH formation. The low-temperature bonding capabilities of SiCN contribute to reducing thermal budgets, preventing device degradation, and advancing 3-D integration and hybrid bonding technologies for next-generation semiconductor applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 11","pages":"2501-2512"},"PeriodicalIF":3.0,"publicationDate":"2025-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145584668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Hybrid Bonding of Nonphotosensitive Dry Films and Cu/SnAg Microbumps for Multilayer Glass Packaging 非光敏干膜与Cu/SnAg微凸点复合键合用于多层玻璃封装

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-10-01 DOI: 10.1109/TCPMT.2025.3616264

Qing Zhou;Ying Tian;Yaqing Zhou;Yi Zhong;Tian Yu;Miao Zhang;Daquan Yu

{"title":"Hybrid Bonding of Nonphotosensitive Dry Films and Cu/SnAg Microbumps for Multilayer Glass Packaging","authors":"Qing Zhou;Ying Tian;Yaqing Zhou;Yi Zhong;Tian Yu;Miao Zhang;Daquan Yu","doi":"10.1109/TCPMT.2025.3616264","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3616264","url":null,"abstract":"A novel low-temperature wafer-level hybrid bonding technique using metal microbumps (Cu/SnAg) and nonphotosensitive dry films has been developed and investigated. The bonding process is conducted at low temperatures: <inline-formula> <tex-math>$160~^{circ }$ </tex-math></inline-formula>C for the dry film and within the range of <inline-formula> <tex-math>$260~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$280~^{circ }$ </tex-math></inline-formula>C for the microbumps. The microbumps are fabricated using conventional electroplating, while patterning of the nonphotosensitive dry film is achieved through laser ablation, bypassing the need for traditional lithography. Furthermore, optimizing the thickness of the microbumps, the opening dimensions of the dry film, the maximum bonding pressure, and the bonding temperature has enabled the development of a stepped control profile, which allows a seam-free bonding interface between the microbumps and the dry films. For demonstration, superior interconnect performance with an average tensile strength of approximately 8.11 MPa is achieved. The nonphotosensitive dry film exhibits low transmission loss when applied to glass packaging due to its low dielectric constant and dissipation factor. Consequently, the proposed hybrid bonding technique provides a highly cost-effective and promising approach for future multilayer glass/polyimide (PI) radio frequency (RF) 3-D integration.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 11","pages":"2513-2520"},"PeriodicalIF":3.0,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145584622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0