IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献_第3页

Gate Oxide and Package Reliability of TO-263 SiC MOSFETs TO-263 SiC mosfet的栅极氧化物和封装可靠性

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-15 DOI: 10.1109/TCPMT.2025.3589429

Rahman Sajadi;C. N. Muhammed Ajmal;Bilal Akin

{"title":"Gate Oxide and Package Reliability of TO-263 SiC MOSFETs","authors":"Rahman Sajadi;C. N. Muhammed Ajmal;Bilal Akin","doi":"10.1109/TCPMT.2025.3589429","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3589429","url":null,"abstract":"This article presents a comprehensive reliability analysis of TO-263 silicon carbide MOSFETs (SiC MOSFETs) from four different vendors, focusing on gate oxide and package degradation. A range of accelerated aging tests (AATs), including positive high-temperature gate bias (PHTGB), negative high-temperature gate bias (NHTGB), high-temperature reverse bias (HTRB), and dc power cycling (DCPC), are conducted to investigate both gate oxide and package reliability. The findings from HTGB and HTRB tests emphasize that even a 10 nm reduction in gate oxide thickness can significantly impact gate oxide reliability compared to similar designs. Furthermore, the results from NHTGB show that the devices are more prone to failure compared to PHTGB, disproving the idea that the device lifetime is longer in the off-state compared to the on-state. The conclusions are drawn from measurements using focused ion beam (FIB) and transmission electron microscopy (TEM), which provide detailed cross-sectional images of the devices. Additionally, the reliability of the TO-263 package is assessed, highlighting solder fatigue failure between the device and the printed circuit board (PCB) as a significant issue. This failure mechanism can lead to the detachment of the device from the PCB, resulting in a loss of connection. The study underscores the importance of optimizing gate oxide thickness and addressing thermal–mechanical stresses to enhance the overall reliability of SiC MOSFETs with TO-263 packages in high-power applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1732-1740"},"PeriodicalIF":3.0,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Cost Functional Testing Based on Data Imputation Integrating Fault Tree Analysis and XGBoost 集成故障树分析和XGBoost的数据插补低成本功能测试

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-15 DOI: 10.1109/TCPMT.2025.3589029

Yiyang Xu;Kangcheng Wang;Yun-Bo Zhao;Yu Kang;Peng Bai

{"title":"Low-Cost Functional Testing Based on Data Imputation Integrating Fault Tree Analysis and XGBoost","authors":"Yiyang Xu;Kangcheng Wang;Yun-Bo Zhao;Yu Kang;Peng Bai","doi":"10.1109/TCPMT.2025.3589029","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3589029","url":null,"abstract":"Functional testing is essential for ensuring the quality of electronic products. As system complexity increases, the cost of functional testing—particularly during the motherboard testing stage—has risen significantly. Designing an efficient testing strategy is therefore key to reducing overall testing costs. Although data imputation methods can enhance the effectiveness of strategies by addressing missing data, current approaches do not adequately account for the impact of correlation information between system modules on the input information of the data imputation model. This oversight results in suboptimal imputation performance, making it challenging to further reduce testing costs. To overcome this limitation, we propose a data imputation method that integrates fault tree analysis (FTA) with eXtreme gradient boosting (XGBoost), effectively combining system fault mode analysis with data-driven modeling. First, faults in nonbus data transmission are additionally considered, and an enhanced fault tree for motherboard testing is constructed. Next, correlations among system modules are quantitatively represented as system event associations within the fault tree, based on which the attributes requiring imputation are determined. Then, a top–down quantitative analysis method driven by both mechanisms and data is introduced to infer the states of basic events from intermediate event states. This mapping from intermediate events to basic events reduces the proportion of missing data. Based on this, missing values are imputed using the tree-based XGBoost model. Experiments conducted on transformed real-world manufacturing data demonstrate that effective testing strategies can be dynamically developed under varying conditions using the proposed method. Testing costs are reduced by up to 5.64% in high-yield scenarios, 6.66% in low-yield scenarios, and 7.07% during long-term yield fluctuations. Furthermore, the defect level is reduced by as much as 51.02%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1764-1777"},"PeriodicalIF":3.0,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144892378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Miniaturized Metasurface-Inspired Tunable Power Divider and Phase Shifter 小型化超表面可调谐功率分压器和移相器

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-10 DOI: 10.1109/TCPMT.2025.3588044

Nophadon Wiwatcharagoses;Sambit Kumar Ghosh;Premjeet Chahal

引用次数: 0

Direct Die-to-Die Bridging for Heterogeneous mm-Wave Circuits Enabled by Fused-Silica Stitch-Chip Technology 采用熔融硅缝片技术实现非均匀毫米波电路的直接模对模桥接

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-10 DOI: 10.1109/TCPMT.2025.3587609

Zhonghao Zhang;Paul K. Jo;Shane Oh;Muhannad S. Bakir

{"title":"Direct Die-to-Die Bridging for Heterogeneous mm-Wave Circuits Enabled by Fused-Silica Stitch-Chip Technology","authors":"Zhonghao Zhang;Paul K. Jo;Shane Oh;Muhannad S. Bakir","doi":"10.1109/TCPMT.2025.3587609","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3587609","url":null,"abstract":"This work presents a novel direct die-to-die (D2D) interconnect approach utilizing fused-silica stitch-chip technology to integrate heterogeneous commercial off-the-shelf (COTS) chiplets without the need for die embedding. This study evaluates RF performance through simulations and experimental measurements, comparing the stitch-chip interconnect against both wire-bond and other interconnect technologies. In addition, this study analyzes the impact of die embedding within a cavity on its performance. A heterogeneous integration of a low-noise amplifier (LNA) die (GaAs) and a switch die (AlGaAs), both designed for K-/Ka-band applications, is demonstrated using stitch-chip technology. RF characterization results verify that the bare LNA die maintains strong performance, achieving greater than 12-dB return loss (RL). The integrated LNA-switch module achieves a 20-dB linear gain up to 38 GHz, with the D2D stitch-chip interconnect showing a 4-dB improvement in gain compared to the die-to-package-to-die (D2P2D) approach and an 8.5-dB increase in gain compared to wire-bond connections. The results demonstrate that the proposed stitch-chip technology effectively minimizes insertion loss (IL), improves impedance matching, and enhances RF signal integrity, positioning it as an up-and-coming solution for future heterogeneous RF/mm-wave multichip integration applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1652-1660"},"PeriodicalIF":3.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Liquid Paste Interconnects on a Silicon Power Diode 液体膏状互连在硅功率二极管上

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-10 DOI: 10.1109/TCPMT.2025.3582563

Nick Baker;Francesco Iannuzzo;Szymon Bęczkowski

引用次数: 0

The Pressure Balance Effect of the Polytetrafluoroethylene Buffer Film in Pressure-Assisted Sintering Bonding 聚四氟乙烯缓冲膜在压力辅助烧结键合中的压力平衡效应

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-10 DOI: 10.1109/TCPMT.2025.3587762

Chenxiao Huang;Guisheng Zou;Shuaiqi Wang;Zehua Li;Guoqiang Qi;Lei Liu

{"title":"The Pressure Balance Effect of the Polytetrafluoroethylene Buffer Film in Pressure-Assisted Sintering Bonding","authors":"Chenxiao Huang;Guisheng Zou;Shuaiqi Wang;Zehua Li;Guoqiang Qi;Lei Liu","doi":"10.1109/TCPMT.2025.3587762","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3587762","url":null,"abstract":"Bonding pressure is one of the most important process parameters in pressure-assisted sintering bonding of the SiC power chips. The buffer film, placed between the pressure indenter and the chips, is essential to balance the pressure during the simultaneous bonding of multiple chips. However, the pressure balance mechanism, optimization, and enhancement of the buffer film have been rarely studied. In this study, a simulation model for the pressure balance effect of the polytetrafluoroethylene (PTFE) buffer film was established and verified by experimental results. The mean relative error (MRE) between the simulation and experimental results was merely 1.06% and 1.98%, regarding to the compression ratio and porosity of the joint. It was found that the pressure balance ability peaked at an optimal pressure for the first time. The optimal pressure value was negatively correlated with the sintering temperature regardless of the film thickness. To improve the pressure balance effect at lower pressure, drilled buffer films were proposed to enhance the pressure balance ability of the PTFE film. With a drilled film, the joint porosity difference between two chips with a 60-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-height difference was reduced by 44%. The combination of films with different removal rates could further eliminate the influence of a specific height difference. This work is promising to deepen the understanding of the pressure balance mechanisms of the buffer film and pave the way for low-cost and low-pressure sintering bonding.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1778-1787"},"PeriodicalIF":3.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144892376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE元件、封装与制造技术资讯汇刊

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-08 DOI: 10.1109/TCPMT.2025.3583863

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-08 DOI: 10.1109/TCPMT.2025.3583865

引用次数: 0

IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information IEEE元件、包装与制造技术汇刊信息

IF 2.3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-07-08 DOI: 10.1109/TCPMT.2025.3583861

引用次数: 0

IC Modeling via Machine Learning Regressions: A Data-Driven Approach to SPICE Integration 通过机器学习回归的IC建模：SPICE集成的数据驱动方法

IF 3 3区工程技术

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-06-30 DOI: 10.1109/TCPMT.2025.3584470

Marco Atlante;Riccardo Trinchero;Igor S. Stievano;Mihai Telescu;Noël Tanguy

引用次数: 0