IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Research on Low-Temperature Thermocompression Bonding of Glass Substrates Assisted by Nano Titanium Passivation Layer","authors":"Zihan Wang;Jihua Zhang;Zhen Fang;Jinxu Liu;Hongwei Chen;Shuqi Li;Borui Li;Wenlei Li;Mingcheng Chen;Wanli Zhang","doi":"10.1109/TCPMT.2026.3724823","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3724823","url":null,"abstract":"Low-temperature Cu–Cu bonding is critical for glass-based 3-D advanced packaging, as conventional high-temperature processes induce severe thermal stress via CTE mismatch. This work investigates Ti-passivation-assisted low-temperature Cu–Cu bonding through molecular dynamics (MDs) simulations and experimental characterization. The results reveal that the Ti layer spontaneously undergoes solid-state amorphization (SSAR) under coupled thermodynamic and kinetic effects: negative Cu–Ti mixing enthalpy drives intermixing, while rapid asymmetric interstitial diffusion of small Cu atoms induces lattice distortion and structural collapse. The resulting amorphous layer acts as an ultrafast diffusion channel with reduced activation energy, enabling dense bonding at <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C with >90% wafer-level effective area and 16 MPa tensile strength. Failure occurs at the glass/Ti film–substrate interface rather than the bonded Cu–Cu interface. These findings provide mechanistic insights and a viable pathway for reliable multilayer glass stacking in high-performance 3-D packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2196-2199"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spatiotemporal Learning in Power Modules: Wavelet-Enhanced Forecasting of Thermomechanical Degradation","authors":"Sanghyeon Chang;Paul Paret;Sreekant Narumanchi;Yoonjin Won","doi":"10.1109/TCPMT.2026.3656473","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3656473","url":null,"abstract":"Detecting internal defects in power electronics packages is critical for their performance and reliability, especially under extreme operating conditions, as these defects can lead to catastrophic failure if not properly addressed. Confocal scanning acoustic microscopy (C-SAM) plays a key role in the nondestructive evaluation of bond layer degradation within a power electronics package by detecting defects such as delamination, voids, and cracks. However, accurately quantifying and predicting these defects from C-SAM images remain significant challenges due to the low noise-to-signal ratio, which typically arises from both the imaging process and the bond patterns themselves. In this article, we explore machine learning strategies for processing C-SAM images and providing predictive models of defect growth. We use C-SAM images of sintered copper and sintered silver samples, which are obtained under accelerated thermal experiments, as the representative dataset for our study. We investigate the effect of Fourier transforms and wavelet transforms on these datasets to remove high-frequency noise and address noise across multiple scales with histogram equalization to enhance the contrast and improve the visibility of defects. As a result, defect boundaries can be clearly distinguished, enabling more accurate tracking of their growth over time. We then employ different time-series forecasting algorithms on the denoised images to formulate an image-based lifetime prediction model. Statistical models and deep learning techniques are trained on images obtained in the early stages of thermal shock, and defect growth in the later stages is predicted. Our work serves as a preliminary attempt to improve the accuracy of lifetime prediction models of power electronics packages, which is critical under extreme operating environments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2025-2035"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Substrate Attachment Voids and Their Impact on VSWR/Insertion Loss Performance for Low-Power Passive Circuits","authors":"Shivendra Tripathi;Anuj Sarode;Satendra Kumar;Deepak Kumar Sharma;Harimohan Singh;Santanu Sinha;Ishwarlal Prajapati","doi":"10.1109/TCPMT.2026.3724946","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3724946","url":null,"abstract":"Substrate-attachment voids are critical defects in high-reliability RF assemblies, yet their quantitative impact on passive circuit performance is underreported. This study correlates Au₈₀Sn₂₀ solder voiding with the simulated voltage standing wave ratio (VSWR) and measured insertion loss (IL) of miniature hybrid semi-monolithic microstrip lines and bandpass filters (BPF) across C through Ka band. Full-wave 3-D FEM (Ansys HFSS) and MoM planar EM (Keysight ADS Momentum) simulations were validated experimentally on microstrip-line and BPF test vehicles (TVs), respectively. Across void fractions from 4.3% to 44.9%, insertion loss showed no correlation with void content; the largest post-bake deviation observed was –0.33 dB, bounding any void-related effect below that level. A 144-h bake at <inline-formula> <tex-math>$125~^{circ } $ </tex-math></inline-formula>C confirmed electrical stability, with minor fluctuations tied to stress relaxation. The results support distinguishing active-device thermal paths from passive ground paths, avoiding unnecessary rework and reducing manufacturing costs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2140-2147"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cross-Alloy Transfer Learning With Transferability Assessment for Mechanical Property Prediction of Lead-Free Solders","authors":"Qais Qasaimeh;Waad Tarman;Daniel F. Silva;Saad Hamasha;Jia Liu","doi":"10.1109/TCPMT.2026.3716524","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3716524","url":null,"abstract":"The mechanical properties of lead-free solder alloys, including yield strength (YS), ultimate tensile strength (UTS), and elastic modulus, are critical indicators of reliability. These properties are typically obtained through experimental testing; however, generating comprehensive datasets through such experiments is costly and time-consuming, particularly for newly developed alloy systems. To address this limitation, this study proposes a transferability-guided transfer-learning (TL) framework that leverages data-rich conventional alloys (e.g., SAC305) to predict the UTS of newly developed, data-scarce alloys (e.g., Innolot). The proposed framework is benchmarked against conventional machine learning (ML) models, including artificial neural networks, random forests (RFs), Gaussian process regression (GPR), support vector regression (SVR), and extreme gradient boosting, demonstrating superior accuracy and robustness in low-data regimes. For example, for SACQ, TL reduces the mean absolute error (MAE) by more than 50% relative to the best conventional ML model. Transferability analysis is employed to evaluate the effectiveness of knowledge transfer from data-rich source alloys to data-scarce target alloys, indicating stronger transfer to SACQ than to Innolot. In addition, interpretability analysis confirms that the TL model captures physically consistent trends, including strength degradation with increasing temperature and aging, and strengthening with higher strain rates. Overall, this work demonstrates that transferability-guided TL enables accurate prediction of mechanical properties for newly developed alloys using minimal experimental data, reducing cost and accelerating the design of high-reliability lead-free solder materials.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2002-2014"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultracompact 2.5-D Integration of RF Interfaces and Opto-Electronic Devices via Silicon Interposer","authors":"Yueqi Zhao;Jinsheng Xu;Jia Li;Qian Zhang;Chen Hu;Qingwei Mo;Gang Luo;Chenhui Li","doi":"10.1109/TCPMT.2026.3698859","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3698859","url":null,"abstract":"This study presents a compact 2.5-D opto-electronic system-in-package solution based on a silicon interposer. This single package integrates opto-electronic chips, electrical chips, and directly soldered radio frequency (RF) interfaces (GPPO connector). This novel approach eliminates RF bond wires and enables direct connection between RF cables and optical chips, leading to a smaller form factor and improved signal integrity. Both single-ended and differential signal transmission lines are co-designed with the RF connector and patterned through wafer-level fabrication. The chips and connectors are connected via flip-chip bonding and solder reflow. Optical fiber is aligned through optical vias on the silicon interposer. In the demonstration, clear eye diagrams are achieved for both a vertical-cavity surface-emitting laser (VCSEL)-based optical transmitter and optical receiver. The directly modulated VCSEL exhibits a 106.25-Gb/s PAM4 eye diagram under a PRBS13Q pattern, while the receiver achieves a 25.78125-Gb/s NRZ.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2135-2139"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Equivalent Circuit Modeling of RF Degradation in TSVs for Millimeter-Wave Applications","authors":"Yong Wang;Minglong Wu;Kun He;Yue Tang;Jun Xing;Fengyi Huang;Yuehang Xu;Xusheng Tang;Huanpeng Wang","doi":"10.1109/TCPMT.2026.3717167","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3717167","url":null,"abstract":"Compared with numerical methods, the equivalent circuit method offers advantages in simulation speed and ease of implementation in commercial radio frequency (RF) electronic design automation (EDA) tools. This letter presents, for the first time, an RF degradation equivalent circuit model (ECM) for through-silicon vias (TSVs) that quantitatively characterizes their performance degradation. The proposed approach is validated through thermal shock stress testing. By integrating the Coffin–Manson reliability model into a degradation-sensitive TSV ECM, the model accurately predicts the evolution of RF performance under thermal loading. The experimental results based on thermal shock tests from <inline-formula> <tex-math>$- 70~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C show excellent agreement between the simulated and measured S-parameters from 0.1 to 40 GHz, with accuracy exceeding 92%. The proposed model is suitable for millimeter-wave reliability assessment, particularly in advanced packaging applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2192-2195"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine Learning-Based Co-Design of Advanced Flip-Chip Packages: Co-Optimization of Package Warpage, Die Stress, Solder-Joint Reliability, Thermal Management, and Signal Integrity","authors":"Mohammad Rafiee;Maryam Hasheminasab;Farough Agin;Farah El Siss","doi":"10.1109/TCPMT.2026.3674462","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3674462","url":null,"abstract":"Advanced flip-chip packages must satisfy thermal limits, chip–package interaction (CPI) constraints, solder-joint reliability, and increasingly tight signal-integrity (SI) margins. These requirements are strongly coupled. A design change that improves one metric can degrade another. Prior studies often optimize the thermal or thermomechanical metrics in isolation, or treat SI separately from package reliability. A unified workflow for concurrent thermal–mechanical–electrical screening at the package-architecture stage is still limited. This article presents an ML-assisted co-design workflow for advanced flip-chip packages. The framework combines thermomechanical FEA, a steady-state thermal model, and full-wave EM analysis. Six objectives are considered jointly: junction-to-ambient thermal resistance (<inline-formula> <tex-math>$boldsymbol {Theta }_{JA}$ </tex-math></inline-formula>), package warpage (<inline-formula> <tex-math>$w_{pkg}$ </tex-math></inline-formula>), maximum principal stress in the ELK/BEOL region (<inline-formula> <tex-math>$boldsymbol {sigma }_{ELK}$ </tex-math></inline-formula>), viscoplastic work-based fatigue indicators for first-level bumps and second-level ball grid array (BGA) (<inline-formula> <tex-math>$boldsymbol {Delta }W_{bump}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {Delta }W_{BGA}$ </tex-math></inline-formula>), and a differential insertion-loss metric (<inline-formula> <tex-math>$text {IL}_{DD21}$ </tex-math></inline-formula>, derived from <inline-formula> <tex-math>$S_{DD21}$ </tex-math></inline-formula>). A Latin hypercube sampling (LHS) spans key material, geometry, and thermal-stack parameters. SI is evaluated using discrete, manufacturable substrate-core options anchored by EM simulations. Random forest (RF) and XGBoost surrogates are trained (fivefold cross validation) for the thermomechanical and thermal objectives and embedded in NSGA-II to generate Pareto-optimal tradeoffs. The net flow method (NFM) is then used to rank Pareto candidates and identify a transparent “champion” design, which is resimulated as a physics-based check. The workflow enables rapid and explainable exploration of coupled tradeoffs. It also provides a practical screening method for early stage flip-chip package-architecture selection under mixed thermal, reliability, and SI constraints.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1823-1831"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of High-Conductive and Reliable Embedded Circuits in Glass Substrates via Pressure-Assisted Cu Nanoparticle Sintering","authors":"Guannan Yang;Dongchang Ma;Junyi Lu;Weiqiang Li;Chao Tang;Wenzhe Wang;Qiyuan Zhang;Yu Zhang;Guanghan Huang;Chengqiang Cui","doi":"10.1109/TCPMT.2026.3706784","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3706784","url":null,"abstract":"This study presents a fabrication method of high-conductive and reliable embedded circuits in glass substrates through pressure-assisted sintering of copper nanoparticle paste. First, inverted trapezoidal grooves were created on glass substrates by picosecond laser modification and hydrofluoric (HF) acid etching. Then, Cu particle paste with a 250-nm size and 75% solid content was filled in the grooves through a two-step filling process. Finally, the samples were hot-press sintered to form conductive circuits. Using the method, embedded circuits with a linewidth of <inline-formula> <tex-math>$30sim 100~mu $ </tex-math></inline-formula>m were fabricated on glass substrates, with a porosity of only 7.6% and a resistivity as low as <inline-formula> <tex-math>$8.53~mu Omega ~cdot $ </tex-math></inline-formula> cm. The embedded circuit structure enabled precise linewidth control and also enhanced the mechanical interlocking of the circuit with superior adhesion, demonstrated by <5% resistance change and no detachment after tape peel tests. Compared to the conventional electroplating method for circuit fabrication on glass substrates, this method eliminates the chemical residues and improves the reliability, offering a scalable solution for circuit fabrication on advanced glass substrates for 5G/6G RF components and optical modules.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1982-1992"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Handling Capability Evaluation and Uncertainty Quantification of Self-Packaged Substrate Integrated Suspended Line RF Balun Through Electromagnetic–Thermal Cosimulation","authors":"Yanning Chen;Hao-Xuan Zhang;Shi-Wei Guo;Jingwei Zhang;Kaiyuan Jin;Yi-Yao Wang;Enze Zhu;Yingzong Liang;Fang Liu;Hao Xie;Wen-Yan Yin","doi":"10.1109/TCPMT.2026.3673271","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3673271","url":null,"abstract":"This article presents a comprehensive investigation of electromagnetic–thermal coupling effect and average power handling capability (APHC) of a self-packaged substrate integrated suspended line (SISL) RF balun for high power applications. A fully coupled electromagnetic–thermal cosimulation is performed based on an in-house finite element method (FEM) solver, incorporating temperature-dependent material properties such as electrical conductivity, thermal conductivity, specific heat, permittivity, and loss tangent. The developed solver shows good agreement with COMSOL Multiphysics and high frequency structure simulator (HFSS) while achieving superior runtime performance. In particular, the thermal effects induced by both conductive and dielectric losses are accurately captured under the continuous-wave excitation. Through detailed parametric studies on key passive elements of spiral inductors and interdigital capacitors, the effects of metal layer thickness and operating frequency on thermal behavior and APHC are characterized and examined. In addition, a surrogate-based uncertainty quantification (UQ) framework is incorporated to assess the robustness of the S-parameter responses and peak temperature against dielectric-property variations. Numerical results reveal that increasing metal line thickness can enhance the APHC by suppressing Joule heating greatly, while dielectric losses contribute minimally to the rise in temperature. Confidence bands and Sobol sensitivity indices are reported to identify the dominant uncertainty contributors across frequency. The findings of this study can provide new insights into the design of high-power RF components with improved thermal reliability.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1901-1911"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frequency-Selective Transition From Substrate-Integrated-Waveguide to Rectangular Waveguides for 77/130-GHz Automotive Radar Using Metal-Only Additive Manufacturing","authors":"Kevin A. P. van Hastenberg;Marianna V. Ivashina;A. Bart Smolders;Artem R. Vilenskiy","doi":"10.1109/TCPMT.2026.3697854","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3697854","url":null,"abstract":"This article presents a compact dual-band substrate integrated waveguide (SIW)-to-rectangular waveguide (RWG) frequency-selective transition (FST). This FST is a key enabler of future dual-band systems, such as automotive radar operating at 77 and 130 GHz. The proposed structure enables efficient signal routing from a single beamforming integrated circuit (BFIC) to two separate antenna arrays, leveraging waveguide (WG)-based filtering for high-frequency integration. A vertical transition topology is adopted to enhance mechanical robustness and to simplify assembly. This robustness is validated by performing a sensitivity analysis on the assembly. The structure is fabricated using aluminum-based laser powder-bed fusion (LPBF), enabling monolithic integration of complex millimeter-wave (mmWave) features. Experimental results demonstrate insertion loss (IL) around 2.5 dB for the low and high bands of the FST, with measured isolation exceeding 30 dB in the high band. The results validate the feasibility of the proposed FST and highlight the impact of manufacturing tolerances on mmWave performance. This work contributes a scalable, low-loss packaging solution for dual-band radar front ends in next-generation automotive and 6G sensing applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 8","pages":"1881-1893"},"PeriodicalIF":3.3,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11538124","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}