The Pressure Balance Effect of the Polytetrafluoroethylene Buffer Film in Pressure-Assisted Sintering Bonding

IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Chenxiao Huang;Guisheng Zou;Shuaiqi Wang;Zehua Li;Guoqiang Qi;Lei Liu
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Abstract

Bonding pressure is one of the most important process parameters in pressure-assisted sintering bonding of the SiC power chips. The buffer film, placed between the pressure indenter and the chips, is essential to balance the pressure during the simultaneous bonding of multiple chips. However, the pressure balance mechanism, optimization, and enhancement of the buffer film have been rarely studied. In this study, a simulation model for the pressure balance effect of the polytetrafluoroethylene (PTFE) buffer film was established and verified by experimental results. The mean relative error (MRE) between the simulation and experimental results was merely 1.06% and 1.98%, regarding to the compression ratio and porosity of the joint. It was found that the pressure balance ability peaked at an optimal pressure for the first time. The optimal pressure value was negatively correlated with the sintering temperature regardless of the film thickness. To improve the pressure balance effect at lower pressure, drilled buffer films were proposed to enhance the pressure balance ability of the PTFE film. With a drilled film, the joint porosity difference between two chips with a 60- $\mu $ m-height difference was reduced by 44%. The combination of films with different removal rates could further eliminate the influence of a specific height difference. This work is promising to deepen the understanding of the pressure balance mechanisms of the buffer film and pave the way for low-cost and low-pressure sintering bonding.
聚四氟乙烯缓冲膜在压力辅助烧结键合中的压力平衡效应
在SiC功率芯片的压力辅助烧结键合中,键合压力是最重要的工艺参数之一。缓冲膜放置在压力压头和芯片之间,在多个芯片同时粘合时平衡压力是必不可少的。然而,对缓冲膜的压力平衡机理、优化和增强等方面的研究却很少。本文建立了聚四氟乙烯(PTFE)缓冲膜压力平衡效应的仿真模型,并通过实验结果进行了验证。节理压缩比和孔隙率的平均相对误差(MRE)仅为1.06%和1.98%。结果表明,压力平衡能力首次在最佳压力下达到峰值。与膜厚无关,最佳压力值与烧结温度呈负相关。为了提高PTFE薄膜在较低压力下的压力平衡效果,提出了钻孔缓冲膜来提高PTFE薄膜的压力平衡能力。使用钻孔膜后,高度差为60 μ m的两个芯片之间的接头孔隙度差异降低了44%。不同去除率的膜组合可以进一步消除比高差的影响。这项工作有望加深对缓冲膜压力平衡机制的理解,为低成本、低压烧结键合铺平道路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Components, Packaging and Manufacturing Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
4.70
自引率
13.60%
发文量
203
审稿时长
3 months
期刊介绍: IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.
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