{"title":"高密度玻璃中间体中小直径、高纵横比玻璃通孔的双面铜填充","authors":"Ye Yang;Kelly E. Lahaie;Tiwei Wei","doi":"10.1109/TCPMT.2025.3557232","DOIUrl":null,"url":null,"abstract":"Glass substrates offer significant advantages over current organic substrate, particularly in high-density, high-performance chip packaging for data-intensive applications such as artificial intelligence (AI). Glass with ultralow flatness enhances the depth of focus in lithography, which helps pattern precisely at advanced metal interconnects. In addition, their superior thermal stability minimizes pattern distortion, and their outstanding mechanical stability supports ultralarge package sizes. These exceptional dimensional stability properties facilitate precise layer-to-layer interconnect alignment, ultimately enabling glass substrates to achieve ten times higher interconnect density compared to organic substrates. However, fabricating high-density, small-diameter, high-aspect ratio (AR) through-glass vias (TGVs) remains a significant challenge. The current state-of-the-art technology for vertical TGVs achieves an AR of 12, with a via diameter of <inline-formula> <tex-math>$30~\\mu $ </tex-math></inline-formula>m. In this work, we present the first demonstration of straight TGVs with 20-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m diameters on 300-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m thick borosilicate glass, achieving a record-high AR of 15. Thanks to the low large-area packaging cost, low thermal expansion coefficient, excellent thermal stability, and low electrical dissipation in high-frequency operation, borosilicate is chosen as the glass substrate in our research. For straight, high AR TGVs, this study explores a double-sided seed layer enhancement (SLE) approach using electroless deposition to reinforce the seed layer, combined with an electroplating strategy to produce void-free, fully filled straight TGVs metal interconnects. The parameter study of the SLE process provides valuable insights and guidelines for fabricating high AR TGVs for future high interconnect density 3-D integration systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1529-1537"},"PeriodicalIF":3.0000,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Double-Sided Copper Filling of Small Diameter, High-Aspect Ratio Through-Glass Vias in High-Density Glass Interposers\",\"authors\":\"Ye Yang;Kelly E. Lahaie;Tiwei Wei\",\"doi\":\"10.1109/TCPMT.2025.3557232\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Glass substrates offer significant advantages over current organic substrate, particularly in high-density, high-performance chip packaging for data-intensive applications such as artificial intelligence (AI). Glass with ultralow flatness enhances the depth of focus in lithography, which helps pattern precisely at advanced metal interconnects. In addition, their superior thermal stability minimizes pattern distortion, and their outstanding mechanical stability supports ultralarge package sizes. These exceptional dimensional stability properties facilitate precise layer-to-layer interconnect alignment, ultimately enabling glass substrates to achieve ten times higher interconnect density compared to organic substrates. However, fabricating high-density, small-diameter, high-aspect ratio (AR) through-glass vias (TGVs) remains a significant challenge. The current state-of-the-art technology for vertical TGVs achieves an AR of 12, with a via diameter of <inline-formula> <tex-math>$30~\\\\mu $ </tex-math></inline-formula>m. In this work, we present the first demonstration of straight TGVs with 20-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m diameters on 300-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m thick borosilicate glass, achieving a record-high AR of 15. Thanks to the low large-area packaging cost, low thermal expansion coefficient, excellent thermal stability, and low electrical dissipation in high-frequency operation, borosilicate is chosen as the glass substrate in our research. For straight, high AR TGVs, this study explores a double-sided seed layer enhancement (SLE) approach using electroless deposition to reinforce the seed layer, combined with an electroplating strategy to produce void-free, fully filled straight TGVs metal interconnects. The parameter study of the SLE process provides valuable insights and guidelines for fabricating high AR TGVs for future high interconnect density 3-D integration systems.\",\"PeriodicalId\":13085,\"journal\":{\"name\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"volume\":\"15 7\",\"pages\":\"1529-1537\"},\"PeriodicalIF\":3.0000,\"publicationDate\":\"2025-04-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10947587/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10947587/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Double-Sided Copper Filling of Small Diameter, High-Aspect Ratio Through-Glass Vias in High-Density Glass Interposers
Glass substrates offer significant advantages over current organic substrate, particularly in high-density, high-performance chip packaging for data-intensive applications such as artificial intelligence (AI). Glass with ultralow flatness enhances the depth of focus in lithography, which helps pattern precisely at advanced metal interconnects. In addition, their superior thermal stability minimizes pattern distortion, and their outstanding mechanical stability supports ultralarge package sizes. These exceptional dimensional stability properties facilitate precise layer-to-layer interconnect alignment, ultimately enabling glass substrates to achieve ten times higher interconnect density compared to organic substrates. However, fabricating high-density, small-diameter, high-aspect ratio (AR) through-glass vias (TGVs) remains a significant challenge. The current state-of-the-art technology for vertical TGVs achieves an AR of 12, with a via diameter of $30~\mu $ m. In this work, we present the first demonstration of straight TGVs with 20-$\mu $ m diameters on 300-$\mu $ m thick borosilicate glass, achieving a record-high AR of 15. Thanks to the low large-area packaging cost, low thermal expansion coefficient, excellent thermal stability, and low electrical dissipation in high-frequency operation, borosilicate is chosen as the glass substrate in our research. For straight, high AR TGVs, this study explores a double-sided seed layer enhancement (SLE) approach using electroless deposition to reinforce the seed layer, combined with an electroplating strategy to produce void-free, fully filled straight TGVs metal interconnects. The parameter study of the SLE process provides valuable insights and guidelines for fabricating high AR TGVs for future high interconnect density 3-D integration systems.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.