Shi-Chung Chang, L. Lee, Lee-Sing Pang, Tien-Ying Chen, Yi-Chen Weng, Huei-Der Chiang, Dennis W. T. Dai
{"title":"Iterative capacity allocation and production flow estimation for scheduling semiconductor fabrication","authors":"Shi-Chung Chang, L. Lee, Lee-Sing Pang, Tien-Ying Chen, Yi-Chen Weng, Huei-Der Chiang, Dennis W. T. Dai","doi":"10.1109/IEMT.1995.526212","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526212","url":null,"abstract":"This paper presents an effective algorithm of determining daily production targets and the corresponding machine capacity allocation for semiconductor wafer fabrication. The algorithm adopts an iterative scheme and each iteration consists of two modules: the proportional Target Generation and Machine Allocation (TG&MA) and the Stage of Penetration Estimation Algorithm (SOPEA). In TG&MA, machine capacities are allocated to processing different types of products at various stages in proportion to their respective available workloads. With the capacity allocated to each product type, SOPEA then applies a recursive, deterministic queuing analysis to estimate the expected flow-in workload of a stage within a day. The flow-ins are fed into TG&MA for another iteration of capacity allocation. Field implementation of this algorithm has demonstrated significant effects on production move increase, cycle time reduction and line balancing.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126530533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Correlation between yield and waiting time: a quantitative study","authors":"K. Srinivasan, R. Sandell, S. Brown","doi":"10.1109/IEMT.1995.526094","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526094","url":null,"abstract":"Using SEMATECH yield modeling techniques, the effect of reductions in cycle time and of improvements in environmental cleanliness is projected to die-per-wafer yield gains in semiconductor wafer fabrication. This study provides a methodology to determine the impact upon the total process yield of the factory as a result of shortening queue times. Modeling a fabrication facility that uses a 0.25 micron high-performance logic (1poly, 4metal) process flow, the methodology is used to determine variations in yield at different concentrations of airborne particles. In turn, the methodology provides guidelines for implementing operational strategies intended to achieve increases in total process yield.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124279290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Flux activity evaluation using the wetting balance","authors":"C. Huang, K. Srihari, A. McLenaghan, G. Westby","doi":"10.1109/IEMT.1995.526185","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526185","url":null,"abstract":"The selection of soldering flux plays a critical role in determining the manufacturing yield and product reliability of printed circuit board assemblies. Fluxes are used to remove oxides and other contaminants on the component leads and the pads on the printed circuit board. They also assist in the transfer of heat. The selection of flux should depend on properties such as its ability to remove the (oxides) tarnish film, activation temperature, corrosiveness, and the resistivity of post process residues. The activity level of a flux influences its ability to clean the oxides on the specimen's surface and to promote wetting. It (the flux activity level) may be altered by changing the contents of the activators that make-up the flux chemistry. This research provides an approach to evaluate the influence of the flux activity in promoting wetting through the use of wetting balance analysis. Standardized specimens were used along with a set of specified test variables. The experimental procedure was determined based on the information obtained through initial experiments. The results obtained can serve as a bench mark for evaluating candidate fluxes for future use in the manufacturing process.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Plasma process control with optical emission spectroscopy","authors":"P. P. Ward","doi":"10.1109/IEMT.1995.526109","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526109","url":null,"abstract":"Plasma processes for etching and desmear of electronic components and printed wiring boards (PWB) are difficult to predict and control. Non-uniformity of most plasma processes and sensitivity to environmental changes make it difficult to maintain process stability from day to day. To assure plasma process performance, weight loss coupons or post-plasma destructive testing must be used. The problem with these techniques is that they are not real-time methods and do not allow for immediate diagnosis and process correction. These tests often require scrapping some fraction of a batch to insure the integrity of the rest. Since these tests verify a successful cycle with post-plasma diagnostics, poor test results often determine that a batch is substandard and the resulting parts unusable. These tests are a costly part of the overall fabrication cost. A more efficient method of testing would allow for constant monitoring of plasma conditions and process control. Process anomalies should be detected and corrected before the parts being treated are damaged. Real time monitoring would allow for instantaneous corrections. Multiple site monitoring would allow for process mapping within one system or simultaneous monitoring of multiple systems. Optical emission spectroscopy conducted external to the plasma apparatus would allow for this sort of multifunctional analysis without perturbing the glow discharge. In this paper, optical emission spectroscopy for non-intrusive, in situ process control is explored along with applications of this technique towards process control, failure analysis and endpoint determination.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of minienvironments on facilities cost","authors":"W. Barnett, R. K. Schneider","doi":"10.1109/IEMT.1995.526128","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526128","url":null,"abstract":"The Strategic Future Fab Study considered minienvironments as an alternative to more traditional \"ballroom\" full filter ceiling design configurations. The study determined that there were real cost savings associated with implementing minienvironment use. Tangible savings in the area of HVAC equipment first cost, ongoing energy cost reduction, and clean room garment cost saving, were identified and dollar values for the specific facilities under consideration assigned. Additional factors such as facility modification flexibility due to tool isolation, process isolation permitting varied temperature/humidity conditions to be maintained, simplified process tool electrical/piping design and routing, and increased operator safety were identified without assigning dollar values for savings.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132173502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Laser micromachining of through via interconnects in active die for 3D multichip module","authors":"D. Chu, W. D. Miller","doi":"10.1109/IEMT.1995.526103","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526103","url":null,"abstract":"One method to increase density in integrated circuits (IC) is to stack die to create a 3D multichip module (MCM). In the past, special post wafer processing was done to bring interconnects out to the edge of the die. The die were sawed, glued, and stacked. Special processing was done to create interconnects on the edge to provide for interconnects to each of the die. These processes require an IC type fabrication facility (fab) and special processing equipment. In contrast we have developed packaging assembly methods to created vertical through vias in bond pads of active silicon die, isolate these vias, and metal fill these vias without the use of a special IC fab. These die with through vias can then be joined and stacked to create a 3D MCM. Vertical through vias in active die are created by laser micromachining using a Nd:YAG laser. Besides the fundamental 1064 nm (infra-red) laser wavelength of a Nd:YAG laser, modifications to our Nd:YAG laser allowed us to generate the second harmonic 532 nm (green) laser wavelength and fourth harmonic 266 nm (ultra violet) laser wavelength in laser micromachining for these vias. Experiments were conducted to determine the best laser wavelengths to use for laser micromachining of vertical through vias in order to minimize damage to the active die. Via isolation experiments were done in order determine the best method in isolating the bond pads of the die. Die thinning techniques were developed to allow for die thickness us thin as 50 /spl mu/m. This would allow for high 3D density when the die are stacked. A method was developed to metal fill the vias with solder using a wire bonder with solder wire.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"COB and COC for low cost and high density package","authors":"G. Rochat","doi":"10.1109/IEMT.1995.526101","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526101","url":null,"abstract":"Today, portable electronic devices have many more functions than the same type of nonportable products had a few years ago. As the similitude rules are no longer valid when designers are faced with miniaturization, it is necessary to find and develop new approaches for the packaging and the interconnections of the integrated circuits. By using a well mastered Chip-On-Board (COB) technology in association with a very accurate die attach process, it is possible to offer an inexpensive Chip-On-Chip (COC) solution to the engineers who need a 3D assembly for a higher level of miniaturization.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128580260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Total contamination control: the minienvironment era","authors":"S. Abuzeid","doi":"10.1109/IEMT.1995.526125","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526125","url":null,"abstract":"Semiconductor manufacturers clearly recognize that shrinking geometries in semiconductor devices require more stringent process and contamination control. The application of isolation technology for the reduction and control of particulate contamination levels has moved from the development and evaluation stage to its current status as a preferred alternative for new semiconductor manufacturing facilities. A system based on Standard Mechanical Interfaces (SMIF), which uses clean isolation technology to protect the integrity of the wafers during processing, storage and transportation within the facility, is described. An extension of the same principle of isolation, based on the SMIF-technology, enables a selected inert environment to be furnished in the process tool area as well as in the transport and storage containers. The technology enables control of particles, oxygen and water vapor levels (to the 10 PPM range), organic vapor and gas phase contaminant. The capabilities of the minienvironment technology and its benefits are analyzed.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134524420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Issues in low-cost manufacture of reliable optoelectronic systems","authors":"S. Leclerc, G. Subbarayan","doi":"10.1109/IEMT.1995.526204","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526204","url":null,"abstract":"A product with high assembly efficiency will, in general, have a low defect count. So, it may be expected that the application of DFA would improve the reliability of optoelectronic systems. Nevertheless, detailed reliability assessment of the product is necessary during the product design and development phase either to compare alternate designs or to assess potential reliability problems in a candidate design. The procedures for such a reliability assessment are discussed. The reliability of the \"electronics\" in an optoelectronic system is typically a function of component, interconnection, board, and subassembly reliabilities.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133023204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How TOC & TPM work together to build the quality toolbox of SDWTs","authors":"E. Rose, R. Odom, R. Dunbar, J. Hinchman","doi":"10.1109/IEMT.1995.526092","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526092","url":null,"abstract":"This paper details activities targeted at improving task behaviors within self-directed work teams (SDWTs), which subsequently improve productivity and quality within the factory. Like many companies, Harris Semiconductor manages its resources to improve productivity and lower manufacturing costs. One major initiative employed at Harris, Theory of Constraints (TOC), focuses on increased throughput, decreased inventory, and reduced operating expense. TOC is the central focus for individual, team, and equipment improvements. Employees are involved in continuous improvement activities, Total Productive Maintenance (TPM) and system improvement project teams to achieve TOC objectives. We focus on the methods used at Harris Semiconductor to deploy and train employees in TOC and TPM, a subset of the total employee \"tool box\" needed to be successful in today's very competitive environment.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133315505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}