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Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'最新文献

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A robust metric for measuring within-wafer uniformity 用于测量晶圆内均匀性的可靠度量
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526193
J.C. Davis, R. S. Gyurcsik, Jye-Chi Lu, J. Hughes-Oliver, D. Nychka
{"title":"A robust metric for measuring within-wafer uniformity","authors":"J.C. Davis, R. S. Gyurcsik, Jye-Chi Lu, J. Hughes-Oliver, D. Nychka","doi":"10.1109/IEMT.1995.526193","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526193","url":null,"abstract":"A robust metric for measuring within-wafer uniformity has been developed and compared to the traditional SNR metric. The new statistic, referred to as the integration statistic, is based on the integration of the volumetric error between the target and the actual surfaces. Comparison with the traditional SNR uniformity metric indicates that the integration statistic provides a more consistent estimate of the uniformity for different numbers of measurements and different orientations of those measurements to the uniformity pattern.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134219069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The impact of single-wafer processing on fab cycle time 单晶圆制程对晶圆厂周期的影响
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526209
S. Wood
{"title":"The impact of single-wafer processing on fab cycle time","authors":"S. Wood","doi":"10.1109/IEMT.1995.526209","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526209","url":null,"abstract":"Rapid thermal processing is already the convention for processes such as silicide annealing, and is being studied as an alternative for virtually every other thermal process in modern CMOS process flows. Single-wafer cleaning is also a broad area of research and development, both in industry and academia, although single-wafer cleaning is not as mature a technology as rapid thermal processing. This paper's objective is to show how single-wafer processing can improve a fab's throughput time. Throughput time (also called cycle time) is the length of time that passes from when a wafer enters a fab to begin processing until all wafer processing is completed and the wafer is ready for final probe. This paper only considers front-end processing.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130334813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Single-wafer processing: opportunities and challenges 单晶圆加工:机遇与挑战
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526206
R. Doering
{"title":"Single-wafer processing: opportunities and challenges","authors":"R. Doering","doi":"10.1109/IEMT.1995.526206","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526206","url":null,"abstract":"As we approach the 0.25-/spl mu/m technology node and 300-mm wafer manufacturing, the industry is challenged to develop new thermal processing tools to replace traditional large-batch furnaces. The most technically challenging process for practical single-wafer implementation is thick oxidation (e.g., for device isolation). In general, the tradeoff between process uniformity, yield and throughput, for each thermal process, will be reflected in the single-wafer vs. minibatch configuration of these tools. The last bastion of large batch processing will probably be wet immersion cleanups, which are less sensitive to the \"device- and wafer-scaling pressures\". However, the migration of thermal processing away from large batches will exert \"logistical pressure\" on the associated cleanups to follow suit. Additional motivations for single-wafer processing are discussed.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"147 Pt 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126310601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New methodology of dynamic lot dispatching: required turn rate 动态批调度的新方法:所需周转率
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526113
Wen-Cheng Chin, Jiann-Kwang Wang, Kuo-Cheng Lin, Seng-Rong Huang
{"title":"New methodology of dynamic lot dispatching: required turn rate","authors":"Wen-Cheng Chin, Jiann-Kwang Wang, Kuo-Cheng Lin, Seng-Rong Huang","doi":"10.1109/IEMT.1995.526113","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526113","url":null,"abstract":"In a semiconductor manufacturing fab with production-to-order type operation, hundreds of devices and various processes are managed. To provide short cycle time and precise delivery to satisfy customers' expectation is always the major task. The difficulties encountered are complex process and product mix, unscheduled machines down time and equipment arrangement. How to dispatch lots effectively has become a very important topic in handling manufacturing. A dispatching algorithm named \"Required Turn Rate (RTR)\" is developed. According to the level of current wafers in process (WIP), RTR algorithm revises the due date for every lot to satisfy the demand from Master Production Scheduling (MPS). Further to calculate the required turn rate of each lot based on process flow to fulfill the delivery requirement. RTR algorithm determines not only due date and production priority of each lot, but also provides required turn rate for local dispatching. Therefore, local dispatching systems of each working area will dispatch the lots by using required turn rate to maximize output and machines utilization.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124987275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reusable modeling capabilities for simulating high volume electronics manufacturing systems 用于模拟大批量电子制造系统的可重用建模功能
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526112
P. Farrington, J. J. Swain, M. Ayokanmbi, J. Evans, J. Rogers
{"title":"Reusable modeling capabilities for simulating high volume electronics manufacturing systems","authors":"P. Farrington, J. J. Swain, M. Ayokanmbi, J. Evans, J. Rogers","doi":"10.1109/IEMT.1995.526112","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526112","url":null,"abstract":"This paper introduces modeling tools, developed in conjunction with personnel at Chrysler's Huntsville Electronics Division (HED), for the rapid modeling and analysis of high volume electronics production lines. The tools that are discussed include a Windows-based line definition program and static capacity evaluator with proposed links to a custom simulation package as well as the increasingly popular WITNESS and ARENA simulation products. In addition, we review a set of submodels/templates developed in WITNESS and ARENA which give the user the capability to rapidly model a line while still providing them with access to a more general simulation environment for model customization and enhancement. These tools require less familiarity with simulation constructs allowing them to be effectively used by the industrial and tooling engineers typically involved in production line design and modification.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128669711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reducing cycle time through programmable multichip modules 通过可编程多芯片模块减少周期时间
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526096
J. Banker, R. Miller
{"title":"Reducing cycle time through programmable multichip modules","authors":"J. Banker, R. Miller","doi":"10.1109/IEMT.1995.526096","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526096","url":null,"abstract":"This paper reports on programs in which the programmable nature of Pico's MCM substrates was key, focusing on the time parameters of these efforts. Data is provided on the rapid development cycle including discussion of the layout, programming, and assembly efforts involved in creating an MCM using a programmable substrate. Finally, plans for future cycle time improvements are presented.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121642794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A framework for supply chain management in semiconductor manufacturing industry 半导体制造业供应链管理框架
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526089
I.M. Ovacik, W. Weng
{"title":"A framework for supply chain management in semiconductor manufacturing industry","authors":"I.M. Ovacik, W. Weng","doi":"10.1109/IEMT.1995.526089","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526089","url":null,"abstract":"In this paper, we define the planning problem in semiconductor manufacturing to be that of managing the entire supply chain and discuss the benefits of this global approach as well as the problems associated with implementing it. Finally, we discuss the requirements for a tool that would enable us to manage the entire supply chain. Our approach allows us to model the supply chain as an integrated network and gives us the ability to identify and therefore better manage the constraints in the system, and to understand and model the response and constraint buffers. The benefits of such an approach are the ability to reflect the global (company wide) impact of local decisions, advance warning of potential problems, and the speed of planning and execution.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"50 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116321359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Solderability testing of alternate component termination materials with lead free solder alloys 无铅焊料合金替代元件端接材料的可焊性试验
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526122
P. Conway
{"title":"Solderability testing of alternate component termination materials with lead free solder alloys","authors":"P. Conway","doi":"10.1109/IEMT.1995.526122","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526122","url":null,"abstract":"The impending introduction of environmental legislation aimed at reducing the quantity of heavy metals disposed of into landfill sites has caused many organisations to look at their choice of interconnect media. A response to this challenge has been the recent activity to find drop-in replacements for tin/lead solders which do not contain lead. Switching from a well characterised and mature interconnection medium, such as the tin-lead and tin-lead-silver alloys, includes a number of potential risks if the proposed alternatives are not sufficiently understood. Candidate materials will have to satisfy a number of demands, such as those relating to reliability and manufacturing compatibility. Reliability demands include fatigue resistance, predictable failure modes, toughness, understanding of the microstructure evolution over time and satisfactory in-service environmental performance (temperature, vibration and humidity). Manufacturing demands include a reasonable liquidus temperature and percentage heat above liquidus to achieve satisfactory wetting, compatibility with current production equipment and product materials and a reasonable shelf life. This paper presents some of the results of an ongoing series of manufacturability trials at Loughborough which are assessing the solderability of various component termination finishes and styles with two candidate lead free solders under a number of different test regimes, these being representative of proposed manufacturing conditions (temperature and atmosphere inert).","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126425786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Flip chip process development techniques using a modified laboratory aligner bonder 使用改良的实验室对准器粘合的倒装芯片工艺开发技术
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526086
N. Koopman, G. Adema, S. Nangalia, M. Schneider, V. Saba
{"title":"Flip chip process development techniques using a modified laboratory aligner bonder","authors":"N. Koopman, G. Adema, S. Nangalia, M. Schneider, V. Saba","doi":"10.1109/IEMT.1995.526086","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526086","url":null,"abstract":"Tool modifications are described which have been made to a laboratory aligner bonder to allow specific process development techniques to be performed and evaluated for solder bump flip chip applications. Techniques described include: optics modifications to allow flip chip alignment to both rough and smooth surfaces; use of chip placement loads to permit temporary chip tacking for subsequent fluxless chip joining; thermal chucks for the flip chip rework operations of hot chip removal, site dress, and rejoining; and flattening of chip solder bumps for solder reflow/balling evaluations. These process steps are described with examples taken from MCNC's Flip Chip Technology Center Applications Laboratory using a Research Devices-modified M8A Aligner Bonder. The key tool parameters are indicated as well as the modifications made to enable the specific flip chip process steps to be performed.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123844929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Inspection of short fault in power-plane with irregular and perforated shapes [MCMs] 不规则和穿孔动力平面短故障的检测
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526110
F. Chao, R. Wu
{"title":"Inspection of short fault in power-plane with irregular and perforated shapes [MCMs]","authors":"F. Chao, R. Wu","doi":"10.1109/IEMT.1995.526110","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526110","url":null,"abstract":"The inspection of short fault in the power plane with irregular and perforated shapes is discussed in this study. Finite element method is utilized in calculating the normalized potential distribution of an irregular and perforated plane. Current source is applied on two diagonal corners of the power plane. The desired short fault position is then determined by the intersection of two zero voltage contour lines obtained in two different test setups. The short fault can be determined by as few as four measurements. The current driving points are also utilized as voltage sensing points. Although the accuracy is not as good as internal measurements, it can provide a convenient way for quick estimation.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127636501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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