{"title":"Technology/strategy management issues for semiconductor technology","authors":"L. Keys","doi":"10.1109/IEMT.1995.526210","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526210","url":null,"abstract":"For more than forty years continuous improvements in semiconductor technology have driven major performance and value for money improvements into a broad range of industries. In particular both sold state memory and microprocessors have been major benefactors from design and process improvements and contributors to this widespread success and penetration of microelectronics into our lives. The resulting smaller device dimensions and larger semiconductor wafers have produced the performance benefits. The rate of device dimension reduction seems to be decreasing as we approach the 0.10 to 0.25 micron range, with capital investments approaching $1 billion dollars per facility for the 200 mm wafers increasingly coming into use. Some industry leaders forecast a $2 billion dollar next generation manufacturing facility cost as we approach the year 2000. These challenges threaten the continued expectation of device cost reduction and may herald the maturation (end) of the optical lithography technology based S-curve \"family\" progress, or change the size and/or scope of the wafer manufacturing facility need to achieve good economics. This summary paper highlights issues, trends, industry activities and needs.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125061449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Managing for a future [electronics manufacturing]","authors":"M. Kelly","doi":"10.1109/IEMT.1995.526087","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526087","url":null,"abstract":"The manufacturing enterprise is the integration of the functions and activities required to make a product. It bridges from concept to end of life of a product and focuses on requirements related to the interactions among functional parts and ultimately their integration. The new manufacturing enterprise continues to depend on engineering; however, it is increasingly driven by information technology and is highly dependent on effective management. The author considers the factors that managers in manufacturing must take into account: the electronic systems, technology roadmaps, information technology, and the dominant competitive advantage.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Itaya, H. Miyazawa, E. Morimoto, Y. Takahashi, Y. Uno, K. Nakakuki, Y. Igucki
{"title":"High-density build-up wiring boards using conventional printed wiring boards process","authors":"S. Itaya, H. Miyazawa, E. Morimoto, Y. Takahashi, Y. Uno, K. Nakakuki, Y. Igucki","doi":"10.1109/IEMT.1995.526099","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526099","url":null,"abstract":"To keep pace with the downsizing of electronic communication equipment and acceleration of transmission speed, the printed wiring board (PWB) must have finer wiring and thinner plating. While various means have been developed to produce these high density boards, we have also developed a process that enables the production of upper and lower surface conductor interconnections on Build-Up substrates using metallic via-posts. The features of the via-post type boards are as follows: (a) it is possible to make them high density, because of the very small via-post developed; (b) Any type of resin can be used; (c) Stacks are possible; that is, mounting a post directly above another post; (d) wirebonding to a pad is possible by use of the via-post. We developed high density, high quality, lower costing, and easier to enable via-post type Build-Up PWBs for Card PCs using conventional PWB equipment. The following is a report on our investigation and the result of trial PWB evaluations.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design for manufacturability and design for \"X\": concepts, applications, and perspectives","authors":"T.C. Kuo, Hongchao Zhang","doi":"10.1109/IEMT.1995.526203","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526203","url":null,"abstract":"Design for Manufacturability (DFM) is a system approach that simultaneously considers all of the design goals and constraints for products that will be manufactured. Sometimes DFM is confused with Design for Assembly (DFA), which is only one aspect of design for Manufacturability. Other aspects include all the \"design for's\" or \"-abilities\"; design for Quality, design for Maintainability, etc. They are sometimes referred to as \"design for X\" (DFX). This paper presents the concepts, applications, and perspectives of DFX, thus, providing some guidelines and references for the future researches and implementations.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effective modeling of factory throughput times","authors":"N. Srivarsan, K. Kempf","doi":"10.1109/IEMT.1995.526190","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526190","url":null,"abstract":"Describes an effective approach to TPT modeling. Though this approach can be used in any factory, our focus here is limited to predicting TPT in a semiconductor wafer fabrication facility. We describe an abstract simulation that runs very quickly on standard PCs and is based on a model that focuses on the factors that have a major influence on TPT. The simple model includes machine assignments and variability of machine availability, operator assignments and variability of operator availability and transportation times and variability of transportation availability. The model can also handle a range of WIP management policies and include test wafer loading. Given the contents of the model, the simulation tool can be used to perform a variety of \"what-if\" analyses. The simulation approach as well as validation results based on implementation at actual fabrication sites are described.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116775202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Applying DFM in the semiconductor industry","authors":"K. Preston White, R. N. Athay, W. Trybula","doi":"10.1109/IEMT.1995.526201","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526201","url":null,"abstract":"In many industries, design for manufacture (DFM) has become a central concept for survival in increasingly competitive global markets. One of the important lessons of DFM is that consideration of manufacturing issues early in the design phase can reap substantial benefits. These include savings in set-up and production costs, reduction of lead times required to bring a new product to market, reduction of parts inventories and associated overhead, and improvements in overall product quality and reliability. This paper describes an effort recently initiated at the University of Virginia and SEMATECH to examine the application of DFM to the design and fabrication of integrated circuits. The DFM philosophy and related methodology, as these have evolved for numerous mechanical and electronic products, are discussed. Existing DFM concepts are considered in light of the unique features of integrated circuit design and fabrication. Some directions for further study are outlined.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117285974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermomechanical stress-strain hysteresis of Sn-Bi eutectic solder alloy","authors":"C. Raeder, L. Felton, R. Messier, L. F. Coffin","doi":"10.1109/IEMT.1995.526124","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526124","url":null,"abstract":"This study details a thermomechanical testing technique, used in an on-going program, to measure stress-strain hysteresis of solder joints. The apparatus closely approximates the mechanical conditions solder joints experience in electronics packages subjected to cyclic temperature changes. The test assembly is composed of a small load frame, an insert of differing thermal expansion coefficient, and a solder joint. Strain gages on the load frame and a calibration procedure conducted prior to testing allow shearing stress and strain in the solder joint to be obtained during testing. Some thermomechanical deformation behavior of SnBi eutectic solder is reported and discussed.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122504690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Laser ablation forward deposition of metal lines for electrical interconnect repair","authors":"K. Tatah, A. Fukumoto, C. Thompson","doi":"10.1109/IEMT.1995.526111","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526111","url":null,"abstract":"Flat-panel display interconnect repair requires an open air (vacuum-system-free), environmentally friendly, dry process with a minimum number of steps. The Laser Ablation Forward Deposition (LAFD) approach described in this paper offers such advantages with the potential for low cost. The Laser Ablation Forward Deposition technique transfers metallic film from a glass support to a nearby substrate by laser ablation. This technique can deposit a wide range of metals.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125799124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The resin molded chip size package (MCSP)","authors":"S. Tanigawa, K. Igarashi, M. Nagasawa, N. Yoshio","doi":"10.1109/IEMT.1995.526195","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526195","url":null,"abstract":"The resin molded chip size package (MCSP), consisting of a polyimide/Cu film carrier with metal bumps, has been developed. The CSP having area-array type electrodes connected with the printed circuit board has been developed by many semiconductor companies. We have developed a resin molded CSP. The encapsulant used for this application has also been developed; it is unlike the conventional liquid type or transfer mold type. The molding method is also new and has been indigenously developed. Two new molding methods were designed: 1) the resin-mold and the connection between the semiconductor-chip and the carrier tape with the metal bumps were simultaneously carried out using the newly developed thermo-adhesive polyimide coated on the carrier tape before the connection; 2) this approach involved laminating the sheet on the semiconductor-chip with the new polyimide adhesive. The encapsulation and the reliability of MCSP were investigated and found to be excellent (resistance to corrosion, heat and stress), equal or superior to that of the conventional surface-mounted devices.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nitrogen reflow ovens: the effect exit temperature has on benzotriazole coated copper boards","authors":"S. Gutierrez, D. Saxton, R. Schluter, P. Thune","doi":"10.1109/IEMT.1995.526183","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526183","url":null,"abstract":"Reports on the comparisons made of three nitrogen capable ovens. The ovens range in size and price representative of common market offerings. The ovens compared were forced convection type and oxygen concentrations (02 ppm) were set at comparable levels. All of the ovens have some exit cooling capability (nitrogen contained). Cards exiting the oven may be oxidized to different levels, dependent on the card's temperature. The level of oxidation sustained on the card's second side due to the first reflow operation and/or any intermediate process steps, e.g., misprinted paste strips, should be known. Downstream solderability and/or processability operations may be affected. Results from this work were used to provide process engineering a quantifiable way of making capital expense decisions.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115877383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}