{"title":"Technology/strategy management issues for semiconductor technology","authors":"L. Keys","doi":"10.1109/IEMT.1995.526210","DOIUrl":null,"url":null,"abstract":"For more than forty years continuous improvements in semiconductor technology have driven major performance and value for money improvements into a broad range of industries. In particular both sold state memory and microprocessors have been major benefactors from design and process improvements and contributors to this widespread success and penetration of microelectronics into our lives. The resulting smaller device dimensions and larger semiconductor wafers have produced the performance benefits. The rate of device dimension reduction seems to be decreasing as we approach the 0.10 to 0.25 micron range, with capital investments approaching $1 billion dollars per facility for the 200 mm wafers increasingly coming into use. Some industry leaders forecast a $2 billion dollar next generation manufacturing facility cost as we approach the year 2000. These challenges threaten the continued expectation of device cost reduction and may herald the maturation (end) of the optical lithography technology based S-curve \"family\" progress, or change the size and/or scope of the wafer manufacturing facility need to achieve good economics. This summary paper highlights issues, trends, industry activities and needs.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1995.526210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
For more than forty years continuous improvements in semiconductor technology have driven major performance and value for money improvements into a broad range of industries. In particular both sold state memory and microprocessors have been major benefactors from design and process improvements and contributors to this widespread success and penetration of microelectronics into our lives. The resulting smaller device dimensions and larger semiconductor wafers have produced the performance benefits. The rate of device dimension reduction seems to be decreasing as we approach the 0.10 to 0.25 micron range, with capital investments approaching $1 billion dollars per facility for the 200 mm wafers increasingly coming into use. Some industry leaders forecast a $2 billion dollar next generation manufacturing facility cost as we approach the year 2000. These challenges threaten the continued expectation of device cost reduction and may herald the maturation (end) of the optical lithography technology based S-curve "family" progress, or change the size and/or scope of the wafer manufacturing facility need to achieve good economics. This summary paper highlights issues, trends, industry activities and needs.