Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'最新文献

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Fine pitch thermosonic wire bonding 细节距热声线键合
D. Cavasin
{"title":"Fine pitch thermosonic wire bonding","authors":"D. Cavasin","doi":"10.1109/IEMT.1995.526178","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526178","url":null,"abstract":"Characterization in a manufacturing environment, under normal operating conditions using standardized material, provides further information on machine performance, capillary suitability, and potential problems to be anticipated and prepared for during manufacturing implementation. The current work has focused on establishing process capability for bonding both 85 /spl mu/m (3.4 mil) and 73 /spl mu/m (2.9 mil) minimum pad dimensions on 107 /spl mu/m (4.2 mil) and 92 /spl mu/m (3.6 mil) centers, respectively. Two state-of-the-art fully automatic thermosonic gold wire bonders, from two different equipment manufacturers, were used.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123646886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fluxless flip-chip attachment techniques using the Au/Sn metallurgy 金/锡冶金无熔剂倒装片连接技术
C. Kallmayer, D. Lin, J. Kloeser, H. Oppermann, E. Zakel, H. Reichl
{"title":"Fluxless flip-chip attachment techniques using the Au/Sn metallurgy","authors":"C. Kallmayer, D. Lin, J. Kloeser, H. Oppermann, E. Zakel, H. Reichl","doi":"10.1109/IEMT.1995.526085","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526085","url":null,"abstract":"With the use of the Au/Sn system as solder metallurgy different fluxless flip-chip processes are possible. In the studies for this paper Au/Sn bumped chips are used for soldering in an infrared oven under activated atmosphere with the self-alignment mechanism. A new approach is the successful application of the Au/Sn metallurgy for vapor phase soldering which provides the self-alignment effect as well. Flip-chip bonding on rigid and flexible substrates using a pulse heated thermode is also demonstrated. The scope of this paper is to show the development of different fluxless flip-chip processes with Au/Sn metallurgy on thin film and thick film substrates. The wetting of the pads, the fillet formation and the growth of /spl zeta/-phase are the major subjects of the studies as they determine the bonding result. Shear tests were performed in order to quantify the quality of the interconnection. The results obtained by the different methods are compared and conclusions about the investigated processes drawn.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123703323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Process integration and optimization of GaAs MESFET and MSM based opto-electronics integrated circuit (OEIC) using statistical experimental design techniques 基于统计实验设计技术的GaAs MESFET和MSM光电集成电路(OEIC)的工艺集成与优化
J. Wang, C. Teng, J. Middleton, M. Feng
{"title":"Process integration and optimization of GaAs MESFET and MSM based opto-electronics integrated circuit (OEIC) using statistical experimental design techniques","authors":"J. Wang, C. Teng, J. Middleton, M. Feng","doi":"10.1109/IEMT.1995.526205","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526205","url":null,"abstract":"Focuses on developing a manufacturable, robust, ion implanted 0.6 /spl mu/m GaAs metal-semiconductor field-effect transistor (MESFET) and metal-semiconductor-metal (MSM) based optoelectronic integrated circuit process. Our approach is to represent the OEIC process as the integration of key process modules. Each process module has well defined design parameters and statistically significant transfer characteristics. The statistically significant transfer characteristics of each process module were obtained through design of experiment (DOE) and response surface modeling (RSM), through the use of both experimental data and calibrated process simulators. These transfer characteristics are used to determine the process optimum, considering design for manufacturability (DFM). The mapping of random process variations onto device variations, are realized by these transfer characteristics and used for statistical circuit design for manufacturability. Therefore, the process yield can be enhanced at both the circuit design and the process design levels. The process capability (Cp) is assessed by these modules' transfer characteristics, as well; thus manufacturability can be incorporated into the early stage of process development. As a result, high yield OEIC transmitter and receiver chips with data transmission rates above 1 Gbit/sec have been achieved.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"460 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125807752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of future single wafer logic fabs 未来单晶圆逻辑晶圆厂的设计
Paul Castrucci
{"title":"Design of future single wafer logic fabs","authors":"Paul Castrucci","doi":"10.1109/IEMT.1995.526127","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526127","url":null,"abstract":"Describes several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, the author compares four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128262207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Advanced interconnect and low cost /spl mu/ stud BGA 先进的互连和低成本/单亩/螺柱BGA
M. Mita, G. Murakami, T. Kumakura, N. Okabe, S. Shinzawa
{"title":"Advanced interconnect and low cost /spl mu/ stud BGA","authors":"M. Mita, G. Murakami, T. Kumakura, N. Okabe, S. Shinzawa","doi":"10.1109/IEMT.1995.526199","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526199","url":null,"abstract":"The /spl mu/ stud BGA is designed to reduce the number of interconnects for higher reliability and low cost. The manufacturing processes of conventional lead-frame are applied to make a high pin count package. Numerous studs are laid out around the LSI's pad area in 0.5 mm pitch for wire bonding. The bottoms of the studs are directly connected to the substrate by micro-soldering. The /spl mu/ stud BGA has no routine in the encapsulated package body. Only bonding wires and studs are used for interconnection. Because of this, the package style is simpler and smaller than other kinds of high density package. It is a shrunken lead-frame style package. The lead-frame with numerous studs is manufactured by a conventional photochemical etching and electroplating process. The package is molded by a plastic transfer molding machine.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114876697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lead free interconnect materials for the electronics industry 电子工业用无铅互连材料
D. Napp
{"title":"Lead free interconnect materials for the electronics industry","authors":"D. Napp","doi":"10.1109/IEMT.1995.526121","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526121","url":null,"abstract":"Considerable development and research has been conducted over the last 25 years by many areas of manufacturing to reduce the use of lead and to limit human exposure to lead and products containing lead. Small levels of lead can damage the nervous system of children. Major sources of lead are ingested paint, 75%, and drinking water, 20%. The elimination of lead from all manufacturing products, whether through legislation or through tax incentives, will have a significant impact on the electronic interconnect technologies. In 1993 the National Center for Manufacturing Sciences (NCMS), a not-for-profit cooperative research consortium of more than 215 U.S. North American manufacturers, established multi-year programs. Lead Free Solder Project (LFSP) and Conductive Polymer Interconnect Project (CPIP) involving participants from industry, academia, and national laboratories. The objective of these programs is to identify lead free solder alternative replacement(s) and conductive polymeric materials for lead bearing solders in the electronics industry. The new materials must meet the interconnect performance requirements at operating environments ranging from-55 to +180 degrees centigrade. Numerous lead free alloy solders, each exhibiting unique properties, have been used by electronic manufacturers in specific applications. The major usage of conductive adhesives has been in consumer electronics and children's toys. Before any of these new lead free materials can be applied to the widely diverse electronics industry considerable research and development is required. The NCMS programs involve a study of the material properties, manufacturability, modeling and reliability predictions, economic impact, and toxicological properties.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131036146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Development of ultra-fine pitch ball bonding technology 超细间距球粘接技术的发展
K. Tatsumi, T. Uno, O. Kitamura, Y. Ohno, T. Katsumata, M. Furusawa
{"title":"Development of ultra-fine pitch ball bonding technology","authors":"K. Tatsumi, T. Uno, O. Kitamura, Y. Ohno, T. Katsumata, M. Furusawa","doi":"10.1109/IEMT.1995.526177","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526177","url":null,"abstract":"While the environment surrounding wire bonding, i.e., wire, lead frame, wire bonder, and capillary, is being developed more eagerly than ever, wire bonding technology which can better meet the more compact and higher density chips without modifying the existing assembly process is desired. This paper discusses reduction of the diameter of a ball to be formed at the tip of the wire, the required wire diameter reduction, capillary tip diameter reduction, and attainment of a higher Young's modulus for the wire which can suppress wire sweep in transfer molding, and indicates that wire bonding for a pitch of 70 /spl mu/m or less can be performed with no problem in reliability of the bonded zone.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126674660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Run by run (generalized SPC) control of semiconductor processes on the production floor 对生产车间的半导体过程进行逐行(通用SPC)控制
J. D. Boyd, M. Banan
{"title":"Run by run (generalized SPC) control of semiconductor processes on the production floor","authors":"J. D. Boyd, M. Banan","doi":"10.1109/IEMT.1995.526093","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526093","url":null,"abstract":"Multiple linear response surface methodology coupled with run by run (generalized SPC) control has been applied at Delco Electronics to a high volume production epitaxy deposition process. This resulted in nearly a 1.8/spl times/ improvement in process capability for thickness control. This was achieved by interfacing an IBM compatible 486 computer to Gemini II epi reactors, translating Sun workstation Matlab script code from the Massachusetts Institute of Technology into PC compatible Matlab script code, and combining this with the InTouch man machine interface (MMI) software package from Wonderware, Inc. This paper is a case study of our experience at implementing this on the production floor. We discuss the general nature of the process to show why this methodology is relatively easy to apply. Operator training was simplified, data acquisition capability was added, new enhanced modes of operation were implemented, and enhanced capability for more advanced processes is possible on equipment that did not originally provide these features.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130192380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Solder bumping through Super Solder 焊料通过超级焊料碰撞
Y. Kaga, T. Amano, M. Kohno, Y. Obara
{"title":"Solder bumping through Super Solder","authors":"Y. Kaga, T. Amano, M. Kohno, Y. Obara","doi":"10.1109/IEMT.1995.526082","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526082","url":null,"abstract":"Flip chip mounting technology is currently being considered for use in consumer information equipment, and industry is waiting for the establishment of solder bump forming technology as an essential constituent of flip chip (FC) mounting technology. At the present, however, no bump forming technology offers a combination of simple process and low cost. Furukawa Electric has developed a lattice substitution solder generation technique (Super Solder, or SS) to supply solder to the pads on PC boards. Taking advantage of the unique characteristics of the SS technique, the authors have developed a solder bump formation technology for FC, under the key concepts of simple process, low cost and non-bridging solder supply. The technique has proven successful in forming solder bumps with ample volume for practical application.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134439528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electrical performance trade-offs in ball grid array package designs 球栅阵列封装设计中的电气性能权衡
K.N. Wang, J. Adam, P.A. Dziekowicz
{"title":"Electrical performance trade-offs in ball grid array package designs","authors":"K.N. Wang, J. Adam, P.A. Dziekowicz","doi":"10.1109/IEMT.1995.526196","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526196","url":null,"abstract":"Summary form only given, as follows. Many new types of ball grid array packages have been introduced or proposed in the last year as alternatives to PQFPs and PGAs. These include single and multilayer configurations for both plastic and metal BGAs based on a variety of material and process technologies. A commonly claimed advantage of all these BGAs is improved electrical performance. With continued increases in clock speed and reductions in noise margins due to voltage scaling, electrical performance will become a driving force for introduction of BGAs in many products. A detailed study of the electrical performance of a selected set of single and multilayer BGA packages was completed. The different package models were generated using a field solver and analyzed for their signal integrity characteristics using SPICE. This includes an analysis of how closely the output signals and the input signals match under varying load conditions. The design and performance of the selected BGA packages were then assessed based on initial simulation results, and a set of design guidelines to optimize electrical performance were developed. These design guidelines can then be applied based on product needs. This paper will address the electrical performance and relative complexity and cost factors facing the engineer and suggest optimal choices for the varying load conditions and chip types.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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