{"title":"未来单晶圆逻辑晶圆厂的设计","authors":"Paul Castrucci","doi":"10.1109/IEMT.1995.526127","DOIUrl":null,"url":null,"abstract":"Describes several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, the author compares four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design of future single wafer logic fabs\",\"authors\":\"Paul Castrucci\",\"doi\":\"10.1109/IEMT.1995.526127\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Describes several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, the author compares four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less.\",\"PeriodicalId\":123707,\"journal\":{\"name\":\"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1995.526127\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1995.526127","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Describes several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, the author compares four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less.