Analog Integrated Circuits and Signal Processing最新文献_第9页

Parasitic RC estimation and defect prediction for embedded memory using machine learning 基于机器学习的嵌入式存储器的寄生RC估计和缺陷预测

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-12 DOI: 10.1007/s10470-025-02438-5

Venkatesham Maddela, Sanjeet Kumar Sinha, Muddapu Parvathi, Sweta Chander

{"title":"Parasitic RC estimation and defect prediction for embedded memory using machine learning","authors":"Venkatesham Maddela, Sanjeet Kumar Sinha, Muddapu Parvathi, Sweta Chander","doi":"10.1007/s10470-025-02438-5","DOIUrl":"10.1007/s10470-025-02438-5","url":null,"abstract":"<div><p>In today's rapidly scaling-down technological environment, identifying the best-fit algorithms for evaluating complicated circuits such as SRAMs is a difficult issue. Many fault models have developed, however their flexibility of use is limited by the restrictions and constraints of the provided test environment. The majority of existing fault models have been studied in terms of well-known March algorithms, which simply provide fault detection information. Scaled-down technologies have an impact on parasitic effects as well, resulting in an extra source of defective behavior and making current test algorithms vulnerable to them. Recent work that uses method of parasitic extraction for fault detection have addressed the problem of limitation due to scale down technologies. However, as the circuit complexity increases the estimation of RC would be tedious. Hence in this paper machine learning based parasitic RC extraction is proposed. Also, as an extension to that, proposed ML based fault detection using extracted parasitic RCs as dataset. The proposed machine learning based fault prediction uses extracted parasitic RCs as dataset. The parasitic RC values are extracted for each fault model using technologies of 120 nm down to deep submicron 7 nm. Regression algorithm is used for modeling the machine for extraction of RCs and observed that 88% of prediction accuracy. Decision tree modeling is used for fault detection and observed 91.7% of accuracy in prediction of fault.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145165547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low profile hybrid frequency and polarization reconfigurable bunny patch antenna for S-band applications 用于s波段应用的低轮廓混合频率和极化可重构兔子贴片天线

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-02 DOI: 10.1007/s10470-025-02430-z

Sweta Agarwal, Manoj Kumar Meshram

{"title":"Low profile hybrid frequency and polarization reconfigurable bunny patch antenna for S-band applications","authors":"Sweta Agarwal, Manoj Kumar Meshram","doi":"10.1007/s10470-025-02430-z","DOIUrl":"10.1007/s10470-025-02430-z","url":null,"abstract":"<div><p>In this Article, a unique single probe feed bunny patch antenna with hybrid frequency and polarization reconfigurability for S-Band application is presented. A bunny patch antenna is a modified circular patch antenna. The bunny-shaped patch antenna is made by joining the conducting strips to the circular patch at 60<sup>0</sup>. Two conducting strips, two notches on the patch periphery, and two RF-PIN diodes are used to reconfigure three polarization states in this antenna: left-hand circular polarization (LHCP), right-hand circular polarization (RHCP), and linear polarization (LP) with frequency reconfigurability. The dielectric material FR-4 is used, which has a thickness of 6.4 mm and a permittivity of 4.4. This antenna features a 400 MHz, -10dB impedance bandwidth from 2.46 to 2.86 GHz and a 3.38% axial ratio (AR) bandwidth from 2.54 to 2.64 GHz. This antenna, when designed optimally, can emit a gain of about 5dBic in its circular polarization states. The proposed bunny patch antenna is fabricated and measured. Results have good agreement in all states of operation. The UMT (Universal MSS Terminal) receiver system can benefit from this antenna.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145142258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A predictive quantization based compressive sensing SAR ADC for ECG signal 基于预测量化的心电信号压缩感知SAR ADC

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-30 DOI: 10.1007/s10470-025-02426-9

Chenhui Feng, Caisheng Liu, Yuanhui Wu, Hui Qian

{"title":"A predictive quantization based compressive sensing SAR ADC for ECG signal","authors":"Chenhui Feng, Caisheng Liu, Yuanhui Wu, Hui Qian","doi":"10.1007/s10470-025-02426-9","DOIUrl":"10.1007/s10470-025-02426-9","url":null,"abstract":"<div><p>Compressive sensing (CS) theory states that sparse signals can be sampled at a sub-Nyquist rate without information loss. The combination of CS and analog-to-digital converter (ADC) has demonstrated an effective reduction in the conversion rate. However, the majority of prior CS ADCs have not been successful in efficiently optimizing the quantization process. This paper proposes the predictive quantization method for the CS successive approximation register ADC. This approach not only reduces the conversion rate but also decreases the number of conversion bits. The pseudo-random sequence used in random demodulation, along with the previous value, serves as the basis for prediction to address the challenge that results from the randomness by mixing. With predictive quantization, the reduction in the number of bits per conversion contributes to improving overall power saving. The prototype circuit is designed in a 0.18-µm CMOS process. The simulation results indicate that the proposed ADC successfully reduces the average number of conversion bits to 6.97 bits for ECG signals when the resolution of ADC is 10 bits. There is approximately a 30% drop in the number of conversion bits.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145145659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance improvement in asynchronous binary search ADC using bootstrapped sample and hold circuit & 2-stage ladder network 采用自举采样保持电路和两级阶梯网络的异步二进制搜索ADC的性能改进

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-27 DOI: 10.1007/s10470-025-02419-8

Anurag Pandey, Kashi Bandla, Dipankar Pal, Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami

{"title":"Performance improvement in asynchronous binary search ADC using bootstrapped sample and hold circuit & 2-stage ladder network","authors":"Anurag Pandey, Kashi Bandla, Dipankar Pal,  Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami","doi":"10.1007/s10470-025-02419-8","DOIUrl":"10.1007/s10470-025-02419-8","url":null,"abstract":"<div><p>This paper presents a design of an 8-bit asynchronous, binary search analog-to-digital converter (ADC) using an asynchronously generated clock signal and inbuilt Bootstrapped sample and hold circuit by utilizing a 2-stage ladder for generation of reference voltages. The proposed design utilizes an anti-aliasing filter and Bootstrapped sample and hold circuit for charge cancellation with only N comparators, <span>(2^{(N-3)})</span> multiplexers, and a switching network. The ADC achieves an SNR of 47.4 dB, an ENOB of 7.7 bits, <span>(text {f}_{in})</span> of 200 KHz, <span>(text {f}_{s})</span> of 125 MSPS, and dissipates 13 mW of power when operated on 1.8 V supply rail. The proposed design had resulted in saving 10<span>(%)</span> of chip area with respect to a recent candidate SAR ADC and more than 50<span>(%)</span> of chip area with respect to flash ADC. The proposed design also showed 61.7<span>(%)</span> improvement in speed with respect to existing SAR architectures due to switching networks. Pre and post-layout simulation results showed a conversion time of approximately 5.2 ns and 6.5 ns respectively, while Monte Carlo simulation and process corner analysis showed good results with less spread. Further, the static characteristics that have been plotted for resistor mismatch showed linearity approximation in the nominal range. The design has the merit of being that choice for radio frequency identification applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02419-8.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144140163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high speed-low power compressor with novel structure for reducing the complexity of wallace multipliers 为降低华莱士乘法器的复杂度，设计了一种结构新颖的高速低功率压缩机

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-27 DOI: 10.1007/s10470-025-02435-8

J Suresh Babu, G. Saravana Kumar

{"title":"A high speed-low power compressor with novel structure for reducing the complexity of wallace multipliers","authors":"J Suresh Babu, G. Saravana Kumar","doi":"10.1007/s10470-025-02435-8","DOIUrl":"10.1007/s10470-025-02435-8","url":null,"abstract":"<div><p>Nowadays power, delay in addition to the area has to turn out to be the attribute features of any VLSI circuit. Usually, the delay of usual multipliers is high due to the number of computations, consequently; the overall speed of circuits become less, and increases power consumption. The performance of Digital Signal Processing (DSP) processors is frequently dependent on the Multiplier and Accumulator (MAC) unit, and three parameters determine it, namely power, area and speed. However, the performance of the conventional MAC is not good when the number of bits increases and also using several multiplication factors increases the power consumption. So, to reduce the compressor size for working with a higher level of bits in lower power and low area consumption, this paper proposes a new architecture for an effective MAC unit. In the proposed architecture, the Peres logic gates are applied in the third compression stage for reducing the power compression and delay. The outcomes demonstrate that the suggested design has high speed and low MAC unit area consumption. Furthermore, the increase in the compressor size is not affecting the system operations. The proposed architecture can be applied for future DSP system to get efficient performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144140165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of electrical parameters in extended source epitaxial layer DG-TFET including interface trap charges and temperatures 扩展源外延层DG-TFET的电学参数研究，包括界面陷阱电荷和温度

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-26 DOI: 10.1007/s10470-025-02428-7

Rajesh Saha, Shridev Devji, Shanidul Hoque, Brinda Bhowmick, Srimanta Baishya

{"title":"Investigation of electrical parameters in extended source epitaxial layer DG-TFET including interface trap charges and temperatures","authors":"Rajesh Saha, Shridev Devji, Shanidul Hoque, Brinda Bhowmick, Srimanta Baishya","doi":"10.1007/s10470-025-02428-7","DOIUrl":"10.1007/s10470-025-02428-7","url":null,"abstract":"<div><p>In this work, we have highlighted the electrical parameters of extended source epitaxial layer double gate TFET (ESETL-DGTFET) for the wide variation in temperatures and interface trap charge density. The DC, RF/analog, and linearity behaviour are reported for variation in positive interface trap charge (PITC)/ negative interface trap charge (NITC) along with wide temperature variations (250–400) K using TCAD simulator. It is seen that PITC improved the electrical parameters like current ratio, cut-off frequency, linearity behaviour, whereas, NITC degrades the same. The degradation in OFF state current at low gate bias with increased temperature is due SRH rate is exponentially dependent on temperature, whereas, band to band tunnelling (BTBT) rate is weak dependence of temperature leads to negligible variation in drain current at high gate bias. With increased temperature, the current ratio degrades and delay improved for both PITC and NITC. The temperature sensitivity is improved in presence of PITC compared to NITC.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144135466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A subthreshold CMOS voltage reference with low temperature coefficient, low power and high PSRR 具有低温系数、低功耗和高PSRR的亚阈值CMOS电压基准

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02421-0

Shubing Wan, Hua Wu, Jiawei Cheng, Xianguo Cao

引用次数: 0

A novel architecture for high-performance PWM class-D audio amplifier 一种新型的高性能PWM d类音频放大器结构

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02422-z

Ahmad Karimi, Abdalhossein Rezai, Mohammad Mahdi Hajhashemkhani, Javad Sadeghi Azizkhani

引用次数: 0

Majority voting for low power and low complexity preamble detection by hybrid memristor-CMOS architecture 基于记忆电阻器- cmos混合结构的低功耗低复杂度前置检测

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02413-0

Ehsan Kalanaki, Behzad Ebrahimi, Mohammad Ali Pourmina

{"title":"Majority voting for low power and low complexity preamble detection by hybrid memristor-CMOS architecture","authors":"Ehsan Kalanaki, Behzad Ebrahimi, Mohammad Ali Pourmina","doi":"10.1007/s10470-025-02413-0","DOIUrl":"10.1007/s10470-025-02413-0","url":null,"abstract":"<div><p>In modern embedded systems, efficient and low-power communication is essential, especially as these systems increasingly handle concurrent wireless protocols. Preamble detection is a critical step in synchronizing received signals after demodulation, yet traditional methods—such as correlation and Hamming distance techniques—suffer from high power consumption and computational complexity. To address these challenges, this paper proposes a novel majority voting-based pattern recognition method that enhances detection accuracy while reducing energy consumption. By leveraging majority voting, our approach mitigates noise effects and improves signal robustness, enabling more efficient preamble detection across varying signal-to-noise ratios (SNRs). The proposed method is implemented in both CMOS-based and hybrid memristor-CMOS architectures, where the hybrid design incorporates dedicated complementary circuits to further optimize power efficiency and reduce silicon area utilization. Unlike conventional CMOS-only implementations, our hybrid approach reduces redundant computations and enhances energy efficiency, making it well-suited for resource-constrained applications. Performance evaluation demonstrates significant improvements over existing techniques, highlighting the potential of memristor-CMOS hybrid technology in low-power, high-speed communication systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144108493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware efficient arithmetic reconfigurable fully homomorphic encryption (ARFHE) accelerator of low power IoT based RISC-V processor 基于低功耗物联网RISC-V处理器的硬件高效算法可重构全同态加密（ARFHE）加速器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02414-z

T. Thammi Reddy, Silpakesav Velagaleti, B. V. V. Satyanarayana, G. Prasanna Kumar

{"title":"Hardware efficient arithmetic reconfigurable fully homomorphic encryption (ARFHE) accelerator of low power IoT based RISC-V processor","authors":"T. Thammi Reddy, Silpakesav Velagaleti, B. V. V. Satyanarayana, G. Prasanna Kumar","doi":"10.1007/s10470-025-02414-z","DOIUrl":"10.1007/s10470-025-02414-z","url":null,"abstract":"<div><p>Homomorphic encryption has emerged as an essential cryptographic approach for protecting data privacy in cloud computing and IoT applications. This research describes a high-performance BGV-FHE accelerator combined with a RISC-V processor to improve efficiency, security, and flexibility over current implementations. The proposed approach uses a Reconfigurable Booth Polynomial Multiplier to improve polynomial operations and reduce computational complexity. The Artix-7 FPGA-based accelerator improves encryption and decryption times by 12.5% compared to previous designs, with times of 1.05 µs and 1.01 µs, respectively. The proposed design provides a throughput of 68.12 MB/s, exceeding traditional homomorphic encryption accelerators. Furthermore, it provides optimal FPGA resource utilization by requiring only 8915 LUTs, 4120 FFs, and 4 DSPs, making it ideal for low-power applications. Compared to previous studies, the proposed accelerator provides improved processing efficiency (229.4 MB/s per W) while maintaining a strong 128-bit security level, ensuring resistance to quantum attacks. The flexibility of the design allows for easy scalability across different FPGA architectures. These enhancements establish the proposed work as the best option for real-time, secure computations in cloud-based encryption and IoT security frameworks.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144108491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0