基于低功耗物联网RISC-V处理器的硬件高效算法可重构全同态加密(ARFHE)加速器

IF 1.4 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
T. Thammi Reddy, Silpakesav Velagaleti, B. V. V. Satyanarayana, G. Prasanna Kumar
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引用次数: 0

摘要

同态加密已成为云计算和物联网应用中保护数据隐私的基本加密方法。本研究描述了一种高性能BGV-FHE加速器与RISC-V处理器相结合,以提高当前实现的效率,安全性和灵活性。该方法采用可重构布斯多项式乘法器来改进多项式运算,降低计算复杂度。Artix-7基于fpga的加速器与之前的设计相比,加密和解密时间分别提高了1.05µs和1.01µs,提高了12.5%。提出的设计提供了68.12 MB/s的吞吐量,超过了传统的同态加密加速器。此外,它提供了最佳的FPGA资源利用率,只需要8915 lut, 4120 ff和4个dsp,使其成为低功耗应用的理想选择。与之前的研究相比,该加速器提供了更高的处理效率(229.4 MB/s / W),同时保持了强大的128位安全级别,确保了对量子攻击的抵抗力。该设计的灵活性允许在不同的FPGA架构之间轻松扩展。这些增强使提议的工作成为基于云的加密和物联网安全框架中实时、安全计算的最佳选择。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Hardware efficient arithmetic reconfigurable fully homomorphic encryption (ARFHE) accelerator of low power IoT based RISC-V processor

Hardware efficient arithmetic reconfigurable fully homomorphic encryption (ARFHE) accelerator of low power IoT based RISC-V processor

Homomorphic encryption has emerged as an essential cryptographic approach for protecting data privacy in cloud computing and IoT applications. This research describes a high-performance BGV-FHE accelerator combined with a RISC-V processor to improve efficiency, security, and flexibility over current implementations. The proposed approach uses a Reconfigurable Booth Polynomial Multiplier to improve polynomial operations and reduce computational complexity. The Artix-7 FPGA-based accelerator improves encryption and decryption times by 12.5% compared to previous designs, with times of 1.05 µs and 1.01 µs, respectively. The proposed design provides a throughput of 68.12 MB/s, exceeding traditional homomorphic encryption accelerators. Furthermore, it provides optimal FPGA resource utilization by requiring only 8915 LUTs, 4120 FFs, and 4 DSPs, making it ideal for low-power applications. Compared to previous studies, the proposed accelerator provides improved processing efficiency (229.4 MB/s per W) while maintaining a strong 128-bit security level, ensuring resistance to quantum attacks. The flexibility of the design allows for easy scalability across different FPGA architectures. These enhancements establish the proposed work as the best option for real-time, secure computations in cloud-based encryption and IoT security frameworks.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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