Analog Integrated Circuits and Signal Processing最新文献

A compact frequency reconfigurable MIMO antenna with high isolation for Wi-Fi and fixed satellite applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-06 DOI: 10.1007/s10470-025-02358-4

B. Ramamohan, M. Siva Ganga Prasad

引用次数: 0

Voltage mode quadrature sinusoidal oscillators employing inverting current feedback operational amplifier 采用反相电流反馈运算放大器的电压模式正弦波振荡器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-06 DOI: 10.1007/s10470-025-02356-6

Tajinder Singh Arora

引用次数: 0

A novel chaotic system with 2-D grid multi-scroll chaotic attractors through quasi-sine function

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-05 DOI: 10.1007/s10470-025-02345-9

Pengfei Ding, Zixuan Wang, Ke Li, Le Yang

{"title":"A novel chaotic system with 2-D grid multi-scroll chaotic attractors through quasi-sine function","authors":"Pengfei Ding, Zixuan Wang, Ke Li, Le Yang","doi":"10.1007/s10470-025-02345-9","DOIUrl":"10.1007/s10470-025-02345-9","url":null,"abstract":"<div><p>With regard to chaotic system with multi-scroll chaotic attractors in multiple directions, the circuit complexity and the size of electronic components of its circuit implementation raise with the increase of the direction and quantity of scrolls. For reducing the complexity of circuit implementation of multi-scroll chaotic attractors, we came up a novel chaotic system with two-directional (2-D) grid multi-scroll chaotic attractors, and its nonlinear term is a quasi-sine function (QSF), which is multiplication of a gate function and a sine function. The circuit implementation of QSF is much simpler compared to other nonlinear functions used in existing chaotic systems. The dynamical properties of Lyapunov exponents, equilibrium points, phase portraits and bifurcation diagrams were discussed. Based on the analyses of dynamical characteristics, the electronic circuits of the novel chaotic system through Multisim software, and the circuit simulation results have good consistency with the numerical ones. Especially, the effectiveness and feasibility of the chaotic system are confirmed through hardware circuits, and its circuit complexity is not affected by the quantity of scrolls, which is easily regulated through changing the width of the gate function used in the QSF.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A compact MIMO antenna design using Yagi-uda antenna inspired elements for 5G sub 6 GHz balanced band applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02353-9

Gopi Chand Naguboina, Anusudha Krishnamurthi

{"title":"A compact MIMO antenna design using Yagi-uda antenna inspired elements for 5G sub 6 GHz balanced band applications","authors":"Gopi Chand Naguboina, Anusudha Krishnamurthi","doi":"10.1007/s10470-025-02353-9","DOIUrl":"10.1007/s10470-025-02353-9","url":null,"abstract":"<div><p>This work describes a unique design for a compact multiple-input multiple-output (MIMO) antenna based on Yagi-uda components and optimized for 5G sub-6 GHz band applications. The antenna, which operates in the frequency range of 3.1–8.9 GHz, is designed to reduce mutual coupling between elements in order to improve performance. This is critical for enabling reliable communication in MIMO systems. The antenna design includes the arrangement of two radiating elements in close proximity edge to edge at different distances. This arrangement allows the antenna to attain high gain while maintaining a compact structure, making it suitable for integration into small form factor devices. The use of FR-4 substrate material further contributes to the antenna’s compactness and cost-effectiveness. The proposed design effectively minimizes interference and maximizes diversity gain, as evidenced by low mutual coupling of − 23 dB at 3.5 GHz, envelope correlation coefficient below 0.001, and diversity gain exceeding 10 dB. These metrics are crucial for robust MIMO communication. Comprehensive evaluations that include S-parameters, diversity gain, radiation pattern, and total effective reflection coefficient evaluate the proposed design’s performance across a variety of parameters. Overall, the proposed MIMO antenna design is a potential solution for 5G sub-6 GHz band applications, as it combines compactness, high performance, and compatibility with emerging wireless communication standards.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analytical minimization of cross cumulant for stationary and non-stationary sources recovery

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02359-3

El Mouataz Billah Smatti, Djemai Arar

引用次数: 0

Design, development and performance of video processor electronics for ocean imaging payload in EOS-06 satellite

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02348-6

Ashok Kumar, Ravi Kumar, Pradeep Soni, Vishnu D. Patel, Ashish Mishra

{"title":"Design, development and performance of video processor electronics for ocean imaging payload in EOS-06 satellite","authors":"Ashok Kumar, Ravi Kumar, Pradeep Soni, Vishnu D. Patel, Ashish Mishra","doi":"10.1007/s10470-025-02348-6","DOIUrl":"10.1007/s10470-025-02348-6","url":null,"abstract":"<div><p>Knowledge of ocean colour information is vital for locating of Potential fishing zone (PFZ). For oceanographic studies, Indian space research organization (ISRO) has launched one Ocean color monitor (OCM-3) payload onboard EOS-08 satellite. OCM-3 has 13 fine spectral bands for better delineation of ocean features with SNR requirements of ≈ 1000 (@ sea reference radiance). Video processor (VP) electronics is the critical circuit for precisely digitizing the multi-port analog signal received from the detectors while maintaining low noise. The design, development and performance of video processor electronics for OCM-3 payload is compiled in this paper. Thirteen separate electronic chains are developed catering to each spectral band. Detector video is processed with 12-bit digitization by 8-port video processor. To obtain higher SNR and lesser electrical coupling, circuit and layout are optimized. The electrical performance is showcased with an SNR of around 4000 and coupling (both intra-and inter-port) confined to less than 0.1%. The developed video processor PCB has a power dissipation of less than 1W and measures only 150 × 110 mm. Acquired onboard images illustrates SNR performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact inverted E-shaped open-circuited impedance matching stub bandpass filter for wireless applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02357-5

A. Kayalvizhi, G. Sankara Malliga, R. Seetharaman

{"title":"Compact inverted E-shaped open-circuited impedance matching stub bandpass filter for wireless applications","authors":"A. Kayalvizhi, G. Sankara Malliga, R. Seetharaman","doi":"10.1007/s10470-025-02357-5","DOIUrl":"10.1007/s10470-025-02357-5","url":null,"abstract":"<div><p>The front and back ends of antennas in wireless communication systems primarily depend on filter design. This experimental study designed a compact inverted E-shaped open-circuited impedance matching stub with a uniform stepped impedance resonator (SIR) bandpass filter for the ultra-wideband (UWB) range of frequencies used in 4G and mid-band 5G wireless applications. The main challenge is to reject the spurious response of upper and lower stopbands with the help of uniform SIR BPF. The proposed filter design generates excellent selectivity and effective stopband rejection at both passbands ends using the symmetrical structure of SIR and inter-digital coupled feed lines. By modifying and positioning two open-circuited stubs on every side of the stub resonators for impedance matching, a bandpass filter (BPF) was made to attain a broad bandwidth and a high degree of selectivity. This study also investigated on various dielectric constant FR-4, Rogers RO-3003, Rogers RO-4003C, and RT/Duriod-6010 for the achievement of filter performances (4.6–7.3), (5.34–8.68), (5–8), (3–5) GHz respectively with the same design structure. Among these dielectric constants, the filter on RT/Duroid-6010 has good FBW (51.6%) and return loss (50 dB). For cost-effectiveness, the filter on the FR-4 substrate was fabricated and measured using a network analyzer, and the simulation results were as expected. Electromagnetic (EM) and Tubular schematic Circuit models were simulated using an Advanced Design System (ADS) tool. This filter exhibits a compact, efficient, wide passband with high selectivity and stopband rejection at both passband ends.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Lightweight implementation of AES for resource constrained environment

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02343-x

R. Parthasarathy, P. Saravanan, S. Rajesh Srivatsav, C. M. Manisha

{"title":"Lightweight implementation of AES for resource constrained environment","authors":"R. Parthasarathy, P. Saravanan, S. Rajesh Srivatsav, C. M. Manisha","doi":"10.1007/s10470-025-02343-x","DOIUrl":"10.1007/s10470-025-02343-x","url":null,"abstract":"<div><p>In order to enhance the data confidentiality and integrity in resource-constrained environments, an optimized hardware implementation of the Advanced Encryption Standard is proposed. An iterative architecture common for both AES-128 encryption and decryption, involving minimum hardware resources, is developed. The sub bytes and inverse sub bytes operations are realized using composite field arithmetic S-box and its inverse, respectively. The matrix constants of the inverse mixcolumns operation of decryption are expressed involving matrix constants of the mixcolumns operation of encryption. Hence, a common equation for both encryption and decryption is derived. Depending upon the requirement, encryption or decryption will be implemented with the minimum resources with appropriate control signals. The proposed work is implemented in both FPGA devices and ASIC platforms. The area occupied by the proposed architecture is 205 slices in the Virtex-5 FPGA device. The area estimate of the proposed design using 180nm technology SCL libraries is only 5644 GE, which highlights the design as a compact implementation of the AES-128 cipher and an optimal choice to ensure the safety of IoT devices.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-28 DOI: 10.1007/s10470-025-02352-w

R. Sivaraman, Srinidhi Magesh, S. Amruthavarshini, Manuj Aggarwal, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram

{"title":"Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF","authors":"R. Sivaraman, Srinidhi Magesh, S. Amruthavarshini, Manuj Aggarwal, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram","doi":"10.1007/s10470-025-02352-w","DOIUrl":"10.1007/s10470-025-02352-w","url":null,"abstract":"<div><p>Random Number Generators (RNGs) are pivotal in cryptographic applications, safeguarding the security and confidentiality of sensitive data through the generation of unpredictable cryptographic keys. Static Random Access Memory (SRAM)-based Physical Unclonable Functions (PUFs) offer a low-overhead alternative for generating randomness in Hybrid Random Number generator (HRNG) architectures, leveraging minimal hardware resources while maintaining robust performance. The proposed work presents a novel HRNG design that leverages an SRAM-based PUF as the entropy source. The extracted SRAM data undergoes a robust post-processing scheme involving a specialized one-way hash function, enhancing the randomness and unpredictability of the generated sequences. The HRNG architecture is implemented on Intel Cyclone IV E FPGA, which utilized 779 logic elements to achieve a throughput of 102.421 Mbps while consuming 148.02 mW of power dissipation to produce 2<sup>23</sup> bits. The performance was rigorously evaluated through NIST SP 800–22 test batteries that has 99.9% of pass rate, entropy analysis ensuring equidistribution, hamming distance, and correlation assessments. Compared to the state-of-the-art RNGs such as memristor chaos, metastable circuits, chaotic oscillators, the proposed method shows its efficacy in eliminating large hardware dependency while yielding robust randomness. Operating at 50 MHz, the proposed HRNG achieves a competitive balance between performance and power consumption, with a throughput that surpasses many existing implementations.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Glitch free transmission gate based linear and nonlinear PFD architectures for fast and low reference-spur PLL

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-28 DOI: 10.1007/s10470-025-02354-8

N. R. Sivaraaj, K. K. Abdul Majeed

{"title":"Glitch free transmission gate based linear and nonlinear PFD architectures for fast and low reference-spur PLL","authors":"N. R. Sivaraaj, K. K. Abdul Majeed","doi":"10.1007/s10470-025-02354-8","DOIUrl":"10.1007/s10470-025-02354-8","url":null,"abstract":"<div><p>This paper presents a Linear Phase Frequency Detector architecture (LPFD) and a Non-Linear Phase Frequency Detector (NLPFD) architecture. The proposed linear and nonlinear PFDs are free from the dead zone, blind zone, and glitches while maintaining a 360-degree detection range. The proposed Transmission Gate Voltage Divider Linear Phase Frequency Detector (TGVD-LPFD) is the best choice to provide better phase noise and reference spur for the PLL. However, the proposed transmission gate non-linear phase frequency detector (TG-NLPFD) is a better choice to have a faster locking PLL while maintaining all other better parameters. Phase-locked loop (PLL) has been implemented in a 180 nm CMOS process using these proposed linear and nonlinear PFD architectures and obtained a PLL with 2.72 GHz output frequency. A PLL built with a linear PFD has been found to offer a reference spur of <span>(-)</span>77.3 dBc and a lock time of 2.5 µs, which has been verified by modeling the PLL in the sdomain. The PLL built using non-linear PFD has been found to offer a reference spur of <span>(-)</span>74.5 dBc and a lock time of 2.3 µs, which has been verified by modeling the PLL in the state space analysis.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0