Analog Integrated Circuits and Signal Processing最新文献

{"title":"Energy efficient approximate full adder design using nano scale technology for image processing","authors":"Md. Shahbaz Hussain,&nbsp;Jyoti Kandpal,&nbsp;Mohd. Hasan,&nbsp;Athar Ali,&nbsp;Naeem Maroof","doi":"10.1007/s10470-026-02650-x","DOIUrl":"10.1007/s10470-026-02650-x","url":null,"abstract":"<div><p>Portable multimedia devices with multiple signal processing techniques and architectures require low power consumption. Earlier research has relied on voltage over-scaling to exploit error resilience, limiting errors through computational and architectural methodologies. This paper explores logic complexity reduction as an alternative method to maximize the benefits of flexible numerical accuracy. It investigates various types of approximate or imprecise Full Adder (FA) cells that are the building blocks of multi-bit approximate adders. Approximate computing is a promising solution for faster, energy-efficient, and less complex circuits. Approximate arithmetic circuits intentionally introduce errors into the circuit’s output to improve power and area efficiency by reducing complexity. Compared to the prior design (mirror adder apprx), the proposed multi-bit adder based on the proposed AHA5 full adder shows a 57.9% improvement in Power Delay Product (PDP) using 16-nm FinFET technology. The proposed approximate arithmetic units are employed in image processing applications to achieve better PSNR.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149189509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and optimization of low-power approximate multipliers for error-tolerant image processing and CNN applications","authors":"Gundugonti Kishore Kumar,&nbsp;Emandi Jagadeeswara Rao,&nbsp;Kundan Kumar,&nbsp;Kankanala Srinivas","doi":"10.1007/s10470-026-02645-8","DOIUrl":"10.1007/s10470-026-02645-8","url":null,"abstract":"<div><p>In error-tolerant applications such as image processing and neural network acceleration, the design of low-power architectures is critical. Approximate computing has emerged as an effective paradigm for developing energy-efficient arithmetic units by relaxing computational accuracy. This paper proposes a novel 4:2 approximate compressor architecture that complements exact compressors to form high-performance approximate multipliers. The proposed designs are synthesized using 90-nm CMOS technology in Cadence Genus and evaluated in terms of power, delay, and area. Simulation results demonstrate substantial improvements compared to existing state-of-the-art approximate multipliers. For 8-bit and 16-bit implementations, the proposed PM1, PHM, and PM2 multipliers achieve area reductions of 45%, 79%, and 18%, and 27%, 59%, and 13%, respectively. Power consumption is reduced by up to 31%, 77%, and 8% (10%, 51%, and 5% for 16-bit designs). Furthermore, the proposed architectures maintain acceptable image quality, exhibiting satisfactory peak signal-to-noise ratio (PSNR) values for image processing operations such as multiplication, smoothing, sharpening, and convolutional neural network (CNN) computations. These results confirm that the proposed approximate multipliers offer an effective trade-off between computational accuracy and hardware efficiency for error-tolerant image processing and CNN applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149190026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Theoretical design of a metamaterial-based antipodal vivaldi antenna with modifications in radiation slots and feed-line section for wideband applications","authors":"Innocent Kadaleka Phiri,&nbsp;Kumaresh Sarmah,&nbsp;Kandarpa Kumar Sarma","doi":"10.1007/s10470-026-02671-6","DOIUrl":"10.1007/s10470-026-02671-6","url":null,"abstract":"<div><p>A key challenge in wideband antenna design is the inherent trade-off between achieving wider bandwidth and maintaining high gain, as well as balancing structural modifications with the overall antenna size. This work presents a simulation-based design and performance analysis of a modified antipodal Vivaldi antenna (AVA) for enhanced performance. A basic AVA is first designed on a low-cost FR-4 epoxy substrate of size 54 mm × 35 mm × 1.6 mm. To enhance bandwidth, cuts are introduced in the radiation slots and the feed-line section. To improve gain and directivity, an “inverted double V” metamaterial unit cell is designed and then incorporated as a 6 × 6 array on the aperture of the modified AVA. The proposed antenna operates over a wide frequency range of 3.4 – 23.7 GHz (S₁₁ &lt; –10 dB), covering the Ultra-wideband (UWB), S-, C-, X-, Ku-, and K-band applications, with a maximum gain of 10.1 dB. Comparative analysis shows that our proposed design outperforms several previously reported designs and provides a valuable simulation-based reference for further experimental and practical implementations. The novelty of this work lies in the integration of a compact AVA structure with a novel metamaterial array and other optimized structural modifications, resulting in improved performance while maintaining low cost and compact size, thereby addressing key challenges in wideband antenna design.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149189447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leakage-aware wide fan-in domino logic architecture using controlled keeper and stacked footer for low-power high-speed CMOS with tag comparator design","authors":"Manoranjan Meher,&nbsp;Preetisudha Meher","doi":"10.1007/s10470-026-02669-0","DOIUrl":"10.1007/s10470-026-02669-0","url":null,"abstract":"<div><p>Wide fan-in domino logic circuits are widely used in high-speed applications such as tag comparators; however, their performance is degraded by contention, leakage and dynamic node instability in scaled CMOS technologies. A new wide fan-in domino logic circuit is presented to improve power efficiency, reduce contention and increase robustness. The proposed design employs a conditionally controlled keeper with a stacked footer network to regulate PDN, thereby suppressing leakage, reducing contention and minimizing unnecessary switching at the dynamic node. This results in lowering effective capacitance and improving evaluation speed. Simulation results in 90 nm CMOS technology for 8-64 input OR gates demonstrate up to 20% reduction in power consumption, 19% improvement in PDP and up to 1.8<span>(times)</span> improvement in noise immunity, along with 1.86<span>(times)</span> improvement in FOM and reduced variability under Monte Carlo analysis. A tag comparator implemented using the proposed circuit achieves up to 29% reduction in power consumption and 23% reduction in delay, while maintaining robust operation across PVT variations. Additional validation under low-frequency operation and UMC 28 nm CMOS technology further confirms the robustness of the proposed architecture.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149189254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a compact two-port MIMO antenna with an innovative metamaterial-based decoupling structure for 2.8–5.8 GHz 5G communication","authors":"Gopi Chand Naguboina,&nbsp;Jaya Laxmi Anem,&nbsp;Chitambara Rao Karedla,&nbsp;Santosh Pavada,&nbsp;Lakshmu Naidu Meesala","doi":"10.1007/s10470-026-02652-9","DOIUrl":"10.1007/s10470-026-02652-9","url":null,"abstract":"<div><p>In 5G applications, multiple-port antennas are essential because they improve data rates and ensure the communication system operates efficiently, improve signal quality, low interference, and ensure regulatory compliance. This research presents a novel metamaterial structure designed with a decoupling structure in the 5G sub-6 GHz balanced bands. The proposed structure is implemented in a MIMO antenna with a compact design featuring dimensions of 60.28 mm × 38.97 mm × 1.6 mm using an FR4 epoxy substrate. The integration of the metamaterial structure improves isolation between antenna elements and also helps to improve system integrity and efficiency. The antenna design is optimized for use in the 5G sub-6 GHz frequency range, offering wideband coverage while minimizing mutual coupling. Simulations and experimental results demonstrate that the newly designed antenna outperforms existing antenna designs for isolation and radiation characteristics analysis. Detailed analysis highlights the efficiency of the proposed metamaterial structure in reducing interference. The novel antenna design’s performance has obtained high gain and reflection coefficient at 13.03 dB and − 24.0202 dB.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149189358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Real-time FPGA-based secure semantic adaptive watermarking system for high-resolution medical images","authors":"K. Nandhini,&nbsp;R. Rajkumar","doi":"10.1007/s10470-026-02662-7","DOIUrl":"10.1007/s10470-026-02662-7","url":null,"abstract":"<div><p>Medical image watermarking plays a critical role in securing patient data while maintaining diagnostic fidelity, but suffers from Initialization Vectors (IV) reuse vulnerabilities and falsification of critical regions. Hence, the <b>EncryptAware Swin-Gray Watermark-Net</b> is used within an FPGA-based real-time framework to solve the problems. Traditional encryption methods remain vulnerable to key-recovery attacks caused by improper reuse of IV in block cipher modes. Thus, Key-Derivation and Authenticated Encryption Mechanism (KD-AEM) is utilized, where hierarchical key derivation provides cryptographically independent session keys for each session, and SIV-based Authenticated Encryption prevents IV reuse and ensures the confidentiality of embedded patient data. Additionally, existing embedding strategies alter diagnostically sensitive regions due to a lack of semantic awareness, which fail to accurately quantify sub-voxel micro-patterns, leading to faulty importance weighting. To accurately protect diagnostically sensitive regions, Swin-Gray-Level Firefly Wavelet Transform (Swin-GL-FWT) is introduced, which extracts voxel-level semantic importance maps, detects sub-voxel micro-patterns, and enhances recognition of low-amplitude, high-frequency variations. Finally, Firefly-Discrete Wavelet Transform (F-DWT) dynamically optimizes embedding strength and location based on these maps, thus balancing imperceptibility, and prevents over-embedding. Experimental results show that the proposed model beats the existing models in terms of watermarking with a higher SSIM of 0.995 and PSNR of 92 dB.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149098102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and isolation prediction of a quad-port orthogonal MIMO antenna with defective ground structure for sub-6 GHz applications using machine learning","authors":"Asokan V,&nbsp;Chitra S","doi":"10.1007/s10470-026-02658-3","DOIUrl":"10.1007/s10470-026-02658-3","url":null,"abstract":"<div><p>The rapid growth of 5G Sub-6 GHz applications, including vehicular communication, wireless networks, and 5G-enabled smartphones, has intensified the demand for compact, high-isolation MIMO antenna systems. However, achieving improved isolation, minimized Envelope Correlation Coefficient (ECC), and high radiation efficiency within limited space remains a critical challenge. To address these challenges, a machine learning (ML)-based compact quad port orthogonal Multiple Input Multiple Output (MIMO) antenna is proposed. The proposed MIMO antenna enhances isolation by chamfering edges on rectangular radiators and integrating a defected ground structure. This design employs an FR-4 substrate, with compact dimensions of 50.475 × 50.475 × 1.6mm³. Performance evaluation of the MIMO antenna demonstrates better isolation of −40.938 dB, radiation efficiency of ≥ 89%, an ECC less than 0.001, and CCL &lt; 0.08 bits/s/Hz. To overcome the computational complexity of traditional isolation prediction, ML techniques are employed to estimate the transmission coefficient, where the Random Forest Regressor (RFR) attains high prediction accuracy with an R² of 97.6% and minimal error metrics. In addition, the Specific Absorption Rate (SAR) is evaluated using a multilayer human tissue structure at 4.5 GHz, confirming suitability for wearable applications. The simulated performance closely matched the results obtained from the measurements of the fabricated antenna.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149132135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An RIS-empowered double-keyed index-chaos modulation scheme with signal fidelity equalization enhancement in massive MIMO-OFDM systems","authors":"V. Venmathi,&nbsp;C. Kavitha","doi":"10.1007/s10470-026-02647-6","DOIUrl":"10.1007/s10470-026-02647-6","url":null,"abstract":"<div><p>Massive Multiple-Input Multiple-Output-Orthogonal Frequency Division Multiplexing (MIMO-OFDM) systems with Reconfigurable Intelligible Surface (RIS) have been historically based on the coherent detection mechanism, where the receiver needs to be informed by precise Channel State Information (CSI). In real scenario, CSI acquisition is very difficult, however, because of high pilot overhead, rapid time-varying Base Station -RIS-User Equipment (BS-RIS-UE) cascaded channels, nonlinear multipath distortions, and likewise RIS induced phase uncertainties. Such drawbacks seriously reduce the Bit Error Rate (BER), spectral efficiency, as well as throughput of the current schemes of chaos-based modulation of communications. This paper proposes a Double-Keyed Subcarrier Modulation with Signal Fidelity Enhancement (DKSMF) which removes CSI but enhances resistance to distortion. The proposed transmitter is a collaborative system to create a hybrid dual-keyed mapping system, where the information is carried on subcarrier indices, sign polarity states, and chaotic spreading patterns. In order to address nonlinear distortions and Inter-Carrier Interference (ICI), Signal fidelity enhancement algorithm is presented in four synchronized stages. Signal decomposition is used to separate the hybrid dual-keyed mapping components, adaptive linear filtering is used to suppress nonlinear artifacts and RIS-induced distortions, hybrid dual-keyed mapping demodulation is used to reconstruct the active subcarrier indices and sign patterns, and hybrid dual-keyed mapping demodulation is used to reconstruct chaotic spread bits using correlation-based detection to perform a precise and reliable decoding. Analytical BER expressions are derived for Rayleigh fading channels using the proposed cascaded BS–RIS–UE model and hybrid modulation statistics. Extensive MATLAB-based experiments confirm the analytical results shows that the proposed DKSMF framework achieves substantial performance gains, attaining significantly lower BER with higher spectral efficiency and throughput compared to DCSK-based benchmark schemes over Rayleigh fading channels in RIS-aided massive MIMO–OFDM systems. The proposed DKSMF framework significantly reduces the BER, achieving a target BER of <span>(:{10}^{-4})</span>at lower SNR levels compared to existing benchmark schemes.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149133123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 155 V/ns-CMTI on-chip digital multi-layer coreless transformer-based isolated gate driver using 0.18-(mu)m HV CMOS process","authors":"Pradyumna Vellanki,&nbsp;Yun-Che Chang,&nbsp;L S S Pavan Kumar Chodisetti,&nbsp;Mitch Ming-Chi Chou,&nbsp;Chua-Chin Wang","doi":"10.1007/s10470-026-02654-7","DOIUrl":"10.1007/s10470-026-02654-7","url":null,"abstract":"<div><p>The increasing demand for efficient and reliable power electronic systems in applications such as data centers, motor drivers, solar inverters, and industrial automation has necessitated advancements in gate driver technologies. This paper presents a novel isolated gate driver (IGD) that incorporates a coreless, six-layer overlapping coil structure integrated into a digital transformer, fabricated using a standard 0.18-<span>(mu)</span>m HV CMOS process. The design achieves high mutual inductance within a compact footprint, with an overall chip area of 1980 <span>(mu)</span>m <span>(times)</span> 1580 <span>(mu)</span>m and a core area of 1514.96 <span>(mu)</span>m <span>(times)</span> 1205.36 <span>(mu)</span>m on silicon. The IGD was evaluated through both simulations and measurements to assess its common-mode transient immunity (CMTI) and signal regeneration capabilities. The results demonstrate a CMTI tolerance of up to 155 V/ns in post-layout simulations. The IGD maintains stable operation across a wide input frequency range from 1 kHz to 5 MHz, demonstrates reliable duty-cycle regeneration from 5% to 95%, and achieves a maximum measured power consumption of 248 mW at 1 MHz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149133034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Three new fully-uncoupled voltage mode third-order sinusoidal oscillators with inverting current feedback operational amplifier","authors":"Tajinder Singh Arora","doi":"10.1007/s10470-026-02648-5","DOIUrl":"10.1007/s10470-026-02648-5","url":null,"abstract":"<div><p>This paper presents three new fully-uncoupled voltage-mode third-order sinusoidal oscillators utilizing inverting current feedback operational amplifiers (ICFOAs), along with four passive resistors and three grounded capacitors. The proposed circuits offer several advantageous features, including the availability of voltage-mode quadrature outputs from low-impedance ports, fully decoupled tuning laws, and the exclusive use of grounded capacitors. Furthermore, all circuit performance-controlling parameters are governed solely by grounded or virtually grounded passive resistors. The validity of the proposed designs has been established through theoretical analysis, software simulations, and hardware experimentation. Additionally, the application of the proposed circuit as a voltage-controlled oscillator (VCO) is also demonstrated.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149133021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}