Analog Integrated Circuits and Signal Processing最新文献

Dual ultra-wideband high-efficiency rectenna for RF energy harvesting from UMTS and UNII bands 用于UMTS和UNII频段射频能量收集的双超宽带高效整流天线

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-22 DOI: 10.1007/s10470-025-02332-0

Shailendra Singh Ojha, P. K. Singhal, Vandana Vikas Thakare

{"title":"Dual ultra-wideband high-efficiency rectenna for RF energy harvesting from UMTS and UNII bands","authors":"Shailendra Singh Ojha, P. K. Singhal, Vandana Vikas Thakare","doi":"10.1007/s10470-025-02332-0","DOIUrl":"10.1007/s10470-025-02332-0","url":null,"abstract":"<div><p>A dual-band ultra-wideband rectenna is being designed to work from 1.8 GHz to 2.7 GHz with a bandwidth of 900 MHz, and 3.4 GHz to 7.5 GHz with a bandwidth of 4.1 GHz. The projected antenna can operate over the lower, medium, and upper frequency bands of the Unlicensed National Information Infrastructure (UNII), as well as the frequency band utilized by the Universal Mobile Telecommunication System (UTMS) at 2100 MHz. The antenna used operates within the specified frequency bands and has an octagonal shape. A defective ground structure is incorporated into an octagonal-shaped antenna to enable its operation within the prescribed frequency ranges. The antenna gains for UTMS-2100 MHz and UNII band are 3 decibels isotropic (dBi) and 5.5 dBi, respectively. The rectifier consists of two branches, and the DC combining technique is chosen to achieve enhanced conversion efficiency (CE). The CE, evaluated at an input power level (IPL) of 0 dBm and a frequency of 2.1 GHz, is 52%. At a frequency of 5.8 GHz, the conversion efficiency is 35%. Nevertheless, the recorded conversion efficiency stands at 85% when operating at a frequency of 2.1 GHz, with an input power level (IPL) of 15 dBm. The highest recorded conversion efficiency at a frequency of 5.8 GHz is 80%, achieved with an IPL of 15 dBm. The optimum value for the load resistor is 330 Ω.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142995763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance comparison on various parameters of area dependent capacitive accelerometer and air gap dependent capacitive accelerometer for high frequency applications 高频应用中面积相关电容式加速度计与气隙相关电容式加速度计各参数性能比较

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-22 DOI: 10.1007/s10470-025-02303-5

P. Balakrishna, Joseph Daniel Rathanasami, Y. V. Narayana

{"title":"Performance comparison on various parameters of area dependent capacitive accelerometer and air gap dependent capacitive accelerometer for high frequency applications","authors":"P. Balakrishna, Joseph Daniel Rathanasami, Y. V. Narayana","doi":"10.1007/s10470-025-02303-5","DOIUrl":"10.1007/s10470-025-02303-5","url":null,"abstract":"<div><p>Microelectronics and mechanical system (MEMS) capacitive accelerometers are very much required for high frequency applications like weapons navigation, submarine navigation and many more. Here, authors design MEMS capacitive accelerometers and also compare their performances. The bulk micro machined multiple beams area changed capacitance accelerometer and air gap comb drive capacitive accelerometer structures are designed. Generally in capacitive accelerometers due to high gap between parallel plates linearity is high and sensitivity is low and vice versa. It is not possible for achieving high linearity and sensitivity at a time. Here, authors concentrated to achieve high mechanical sensitivity and high voltage sensitivity with better linearity for capacitive Accelerometers. So authors performed some analysis like non-linearity, capacitive, noise, temperature, displacement and voltage sensitivity in various works for both the capacitive accelerometers and compared<b>.</b> The cross axis sensitivity for air gap is 10.75% and for area is 0.45%, voltage sensitivity for air is 0.3642 V/g and for area is 0.8466 V/g. Noise figure for air is 0.428 <span>(frac{ug}{{sqrt {{text{hz}}} }})</span> and noise figure for area is 3.73 pg/<span>(sqrt {{text{Hz}}})</span>, Mechanical sensitivity for air is 0.007 µm/g and for area is 0.26 µm/g and linearity is nearly equal to both the capacitive accelerometers. From all these comparisons authors concluded that area changed capacitive accelerometer is best one when compared to air gap changed accelerometer. The primary advantage of this structure is that no changes to the fabrication process flow are required when constructing it.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142995766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Artifact removal of EEG data using wavelet total variation denoising and independent component analysis 基于小波全变差去噪和独立分量分析的脑电信号伪影去除

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-21 DOI: 10.1007/s10470-025-02315-1

Santhosh Kumar Veeramalla, Vasu Deva Reddy Tatiparthi, E. Bharat Babu, Ratikanta Sahoo, T. V. K. Hanumantha Rao

{"title":"Artifact removal of EEG data using wavelet total variation denoising and independent component analysis","authors":"Santhosh Kumar Veeramalla, Vasu Deva Reddy Tatiparthi, E. Bharat Babu, Ratikanta Sahoo, T. V. K. Hanumantha Rao","doi":"10.1007/s10470-025-02315-1","DOIUrl":"10.1007/s10470-025-02315-1","url":null,"abstract":"<div><p>The Electroencephalogram (EEG) signals have very small amplitudes, which allow for the data to be readily contaminated by numerous artifacts. When it comes to clinical assessment, the presence of artifacts makes the study of EEG more complex. Power Line noise, eye movements, Electromyogram (EMG), and Electrocardiogram (ECG) are the most often seen artifacts that impact the EEG. Various researchers have developed a variety of strategies and procedures to deal with these artifacts. We provide a method for denoising the EEG signal in this work. The suggested method is implemented using a combined approach of wavelet total variation denoising method (WATV) and Independent Component Analysis (ICA). ICA technique entails running ICA algorithm on independent components to derive the components. In the case of artifactual events, just the wavelet-ICA components related to that event are used and then eliminated. To create artifact-free EEG, the artifact-free wavelet components are reconstructed. The complete approach may be confirmed for simulated signals and may be utilized for processing biological data, which may include EEG signal measurements, and for images, such as MRIs, contaminated by additional random noise. Signal to Noise Ratio (SNR) and Root Mean Square Error (RMSE) will be used to evaluate the algorithm’s performance. The WATV-ICA framework improves SNR more than the other techniques, according to simulation results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142995395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of a novel microwave planar sensor for the fruit quality detection using free space transmission method 自由空间传输法检测水果品质的微波平面传感器的研制

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-20 DOI: 10.1007/s10470-025-02304-4

Kalindi S. Shinde, Shweta N. Shah, Piyush N. Patel

引用次数: 0

Fpga implementation of an efficient phase shift beamformer for narrow band sub-GHz applications 用于窄带sub-GHz应用的高效移相波束形成器的Fpga实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-20 DOI: 10.1007/s10470-025-02308-0

P. Jeyakumar, K. Sudhakar, P. Thanapal, C. Navaneethan, S. Meenatchi

{"title":"Fpga implementation of an efficient phase shift beamformer for narrow band sub-GHz applications","authors":"P. Jeyakumar, K. Sudhakar, P. Thanapal, C. Navaneethan, S. Meenatchi","doi":"10.1007/s10470-025-02308-0","DOIUrl":"10.1007/s10470-025-02308-0","url":null,"abstract":"<div><p>To improve the received signal strength beams are formed by multi-element arrays. These beams are focused on the direction of arriving signals, with an intention of maximizing the received signal power. The signals with noise and interference arrived from a distinct direction will be estimated by Uniform Linear Array (ULA) with 10 antenna elements. The earlier signal will be phase-shifted with the help of phase shift beamformer. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used compute the vector angle in signal cluster. The CORDIC algorithm is employed determint the phase shift and frequency offset. The beamformer assumes that incoming signal are narrow banded, a phase shift can estimate the required delay and preserve the incoming signal strength. The beamformer circuit is designed in Xilinx Vivado for simulation and synthesized using both Virtex-7 device and their results are compared with exisiting methods, which is evidence that the proposed design is formidable pertaining to power and delay. This design can operate at 100 MHZ with total on-chip power consumption of 725 mW.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142995328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 10 W 93.7% peak efficiency load balanced single inductor double output (SIDO) hysteretic buck converter with 0.0063 mV/mA low cross regulation 一个10瓦93.7%峰值效率负载平衡单电感双输出（SIDO）迟滞降压变换器，0.0063 mV/mA低交叉调节

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-18 DOI: 10.1007/s10470-025-02302-6

Seyrani Korkmaz, Gunhan Dundar

{"title":"A 10 W 93.7% peak efficiency load balanced single inductor double output (SIDO) hysteretic buck converter with 0.0063 mV/mA low cross regulation","authors":"Seyrani Korkmaz, Gunhan Dundar","doi":"10.1007/s10470-025-02302-6","DOIUrl":"10.1007/s10470-025-02302-6","url":null,"abstract":"<div><p>This paper presents a novel Single Inductor Double Output (SIDO) Hysteretic Buck converter which balances one output with respect to the other by continously monitoring the load demands of both outputs and then aligning the outputs such that each output regulates its load with minimal disturbance to the other. Load balancing prioritizes the inductor current delivery in the case of a large load current request. The controller aims to finalize the ongoing regulation of the recent output in a prompt manner and then directs the inductor current to the steep load demand output and afterwards returns to the initial output regulation in an iterative way. In conjunction with iterative duty cycle adjustment of outputs, a frequency counter is utilized to accelerate the iteration process to enhance the transient response further. In addition, a delay locked loop fine tunes the duty cycle further to reduce the steady state cross regulation and also limits the switching frequency spectrum. Consequently, both static cross regulation and transient cross regulation performance are further improved compared to previous SIDO architectures. Post-layout simulation results indicate that this architecture has a static cross regulation of 0.0009 mV/mA and transient cross regulation of 0.0063 mV/mA. This SIDO buck converter outperforms the previous studies with a total power delivery capability by supplying 3A load current at each output and 10 W of total power with a peak efficiency of 93.7%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142995066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A comparative study on nonlinear dynamics: between peak current mode, peak V2 and enhanced V2 modulated buck converter 峰值电流模式、峰值V2和增强V2调制降压变换器的非线性动力学比较研究

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-17 DOI: 10.1007/s10470-025-02307-1

Shilpi Saha, Sukanya Parui

{"title":"A comparative study on nonlinear dynamics: between peak current mode, peak V2 and enhanced V2 modulated buck converter","authors":"Shilpi Saha, Sukanya Parui","doi":"10.1007/s10470-025-02307-1","DOIUrl":"10.1007/s10470-025-02307-1","url":null,"abstract":"<div><p>The studies on Nonlinear Phenomena have been carried out in buck converter controlled by three different types of modulation technique—Peak current, Peak V<sup>2</sup> and Enhanced V<sup>2</sup>. These three modulation methods are rippled based control methods as inductor current ripple is used in Peak current modulation (PCM) method and output ripple voltage used in both Peak V<sup>2</sup> and Enhanced V<sup>2</sup> modulation methods and due to that all three modulation methods provide fast dynamic response. Here three modulation techniques have been explained in details and simulation results have been provided. For designing the modulators—we consider two loops i.e. inner loop or fast feedback path (FFBP) and outer loop or slow feedback path (SFBP). The outer loop of all these three modulation methods contains same information, the difference between reference voltage and output voltage. Mathematical model has been developed with the help of state space equation in continuous conduction mode (CCM). Bifurcation diagrams are obtained with load resistance, input voltage and reference voltage as bifurcation parameter. To validate the bifurcation pattern, time plot and phase plane trajectory at each transition have been shown for these three types of modulated system. A comparative study has been made. Experiments are conducted on an enhanced V<sup>2</sup> modulated buck converter to validate the nature of the nonlinearities. To check the dependency of the system on ESR value, parameter space plots are developed and compared for all these three types of control technique.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142995270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modelling of efficient nano-scale code converters using quantum dot cellular automata 基于量子点元胞自动机的高效纳米码转换器建模

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-16 DOI: 10.1007/s10470-025-02300-8

Javeed Iqbal Reshi, M. Tariq Banday, Farooq A. Khanday

引用次数: 0

Temperature dependence of analog/RF performance, linearity and harmonic distortion figures of merit in negative capacitance quad-FinFET 负电容四finfet中模拟/射频性能、线性度和谐波失真值的温度依赖性

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-13 DOI: 10.1007/s10470-025-02324-0

K. Vanlalawmpuia, Aditya Sankar Medury

{"title":"Temperature dependence of analog/RF performance, linearity and harmonic distortion figures of merit in negative capacitance quad-FinFET","authors":"K. Vanlalawmpuia, Aditya Sankar Medury","doi":"10.1007/s10470-025-02324-0","DOIUrl":"10.1007/s10470-025-02324-0","url":null,"abstract":"<div><p>This paper presents an investigation on the impact of temperature variations (150 –400 K) on the DC, analog/RF performance such as total gate capacitance (<i>C</i><sub>gg</sub>), transconductance (<i>g</i><sub>m</sub>), output conductance (<i>g</i><sub>d</sub>), intrinsic gain, transconductance efficiency, cut-off frequency (<i>f</i><sub>T</sub>), and transconductance frequency product (TFP) of the negative capacitance quad-FinFET (NCQ-FinFET). A comparative evaluation of the analog/RF performance of the NCQ-FinFET and SOI NC-FinFET is carried out. Additionally, the influence of temperature on the linearity figures of merit in the NCQ-FinFET is analysed for a wide range of temperature, including higher order harmonics, higher order voltage intercept points, third-orders power-intercept points and intermodulation distortion, and 1-dB compression point. Furthermore, the harmonic distortion (HD) metrics such as second and third order harmonic distortion (HD2 and HD3), as well as total harmonic distortion (THD) are presented for different temperature range. The analog/RF, linearity and HD metrics are observed to be significantly impacted by temperature variation. According to the analysis, when temperature increases from 150 K to 400 K, the analog/RF characteristics deteriorates while the linearity and HD metrics are improved.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142994584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and optimization of UWB fractal micro strip patch antenna for vehicular communication applications under futuristic frequencies 未来频率下车载通信用超宽带分形微带贴片天线的设计与优化

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-10 DOI: 10.1007/s10470-025-02301-7

Raghavendra Karanam, Deepti Kakkar

引用次数: 0