Analog Integrated Circuits and Signal Processing最新文献

FPGA design and implementation of TRNG architecture using ADPLL based on fir as loop filter 使用基于杉木作为环路滤波器的 ADPLL 的 TRNG 架构的 FPGA 设计与实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-11-27 DOI: 10.1007/s10470-024-02295-8

Huirem Bharat Meitei, Manoj Kumar

{"title":"FPGA design and implementation of TRNG architecture using ADPLL based on fir as loop filter","authors":"Huirem Bharat Meitei, Manoj Kumar","doi":"10.1007/s10470-024-02295-8","DOIUrl":"10.1007/s10470-024-02295-8","url":null,"abstract":"<div><p>This article presents a comprehensive examination of the design, implementation, as well as analysis of a true random number generator (TRNG). The TRNG utilizes an all-digital phase-locked loop (ADPLL) that incorporates a finite impulse response (FIR) filter as the digital loop filter. The TRNG is implemented on the Artix 7 (XC7A35T-CPG236-1) FPGA board, leveraging the Xilinx Vivado v.2015.2 design suite. The computation of the coefficients for a third-order broadcast low pass digital FIR filter is performed via the Keiser window technique. The MATLAB filter design and analysis tool is utilized for the computation of filter coefficients. Following the application of the XOR-corrector post-processing method to mitigate bias in the sequence, the proposed designs of ADPLL-based TRNGs successfully generated an unbiased stochastic random number. These designs achieved an overall throughput of 200 Mbps for both configurations. The initial proposed design for a TRNG based on a Finite Impulse response-all-digital phase-locked loop (FIR-ADPLL), referred to as FAT-1, exhibits a power consumption of 0.072 W. In contrast, the subsequent proposed TRNG design, also based on a FIR-ADPLL, known as FAT-2, demonstrates a slightly higher power consumption of 0.074 W. The bitstream that is obtained is assessed for randomness through the application of the NIST test, which is conducted after post-processing. The Artrix-7 field-programmable gate array board is utilized to establish a connection with the DSO for the purpose of capturing the waveforms produced by the TRNG. Both of the suggested designs for FIR-based all-digital phase-locked loop true random number generators successfully underwent testing according to the NIST SP 800-22 standard. This indicates that these designs exhibit strong compatibility with a wide range of industrial applications, such as network security, cybersecurity, banking security, smart cards, RFID tags, the internet of things, and industrial internet of things.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142714631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TCAD simulation of sub-10 nm high-k SOI GaN FinFET by implementing fin optimization approach for high-performance applications 针对高性能应用实施鳍片优化方法，进行 10 纳米以下高 K SOI GaN FinFET 的 TCAD 仿真

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-11-27 DOI: 10.1007/s10470-024-02292-x

Vandana Singh Rajawat, Ajay Kumar, Bharat Choudhary

{"title":"TCAD simulation of sub-10 nm high-k SOI GaN FinFET by implementing fin optimization approach for high-performance applications","authors":"Vandana Singh Rajawat, Ajay Kumar, Bharat Choudhary","doi":"10.1007/s10470-024-02292-x","DOIUrl":"10.1007/s10470-024-02292-x","url":null,"abstract":"<div><p>This paper reports, the enhanced electrical parameters of sub-10 nm High-k SOI GaN FinFET by implementing fin optimization approach using TCAD simulation. The results show that as the fin aspect ratio (AR) increases, keeping the channel cross-sectional area constant, the static and analog performance of the suggested device enhances. On current of 0.15 mA, higher switching ratio (I<sub>ON</sub>/I<sub>OFF</sub>) ratio (1.74 × 10<sup>9</sup>), reduced subthreshold swing (by 20%), and higher intrinsic gain has achieved for High-k SOI GaN FinFET having a higher fin AR (3.75) as compared to the lower fin aspect ratio (1.67) owing to the significant reduction in short channel effects. For more insight into the static/analog performances of the device; some other parameters such as transconductance (g<sub>m</sub>), energy band profile, surface potential, output conductance (g<sub>d</sub>), output resistance (R<sub>o</sub>), and early voltage have also been investigated under fin optimization approach (fin aspect ratio modulation). Thus, the enhanced static/analog performances of the High-k SOI GaN FinFET clear the way for RFIC design.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142714645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel analog circuit fault diagnosis method based on multi-channel 1D-resnet and wavelet packet transform 基于多通道 1D-resnet 和小波包变换的新型模拟电路故障诊断方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-09-29 DOI: 10.1007/s10470-024-02291-y

Xin Zhou, Xuanzhong Tang, Wenhai Liang

{"title":"A novel analog circuit fault diagnosis method based on multi-channel 1D-resnet and wavelet packet transform","authors":"Xin Zhou, Xuanzhong Tang, Wenhai Liang","doi":"10.1007/s10470-024-02291-y","DOIUrl":"10.1007/s10470-024-02291-y","url":null,"abstract":"<div><p>To quickly and accurately locate the fault location and fault parameter deviation of analog circuits, a novel incipient fault diagnosis method based on multi-channel one-dimensional residual networks (MC-1D-ResNet) and wavelet packet transform(WPT) is proposed in this paper. The WPT is employed to preprocess the time-domain response signals of analog circuit, and the proposed MC-1D-ResNet is utilized for feature mining and fault classification.The two-level WPT is first carried out on the time-domain response signal to generate one approximate signal and three detailed signals. Secondly, MC-1D-ResNet further performs feature mining on approximate signals and three detailed signals, and realizes fault diagnosis. Through simulation analysis, the proposed method is fully evaluated with the Sallen-Key bandpass filter circuit and the four-op-amp biquad high-pass filter circuit. Even in complex Four-op-amp biquad high-pass filtering circuits, the diagnostic accuracy can reach 99.74%. This article also designs a hardware testing platform based on FPGA, and conduct actual fault diagnosis tests on the four-op-amp biquad high-pass filter circuit. The results show that the average accuracy of 50 actual diagnoses for each type of fault in the circuit was 97.80%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"121 1-3","pages":"25 - 38"},"PeriodicalIF":1.2,"publicationDate":"2024-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA-based implementation and verification of hybrid security algorithm for NoC architecture 基于 FPGA 的 NoC 架构混合安全算法的实现与验证

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-09-14 DOI: 10.1007/s10470-024-02290-z

T. Nagalaxmi, E. Sreenivasa Rao, P. ChandraSekhar

{"title":"FPGA-based implementation and verification of hybrid security algorithm for NoC architecture","authors":"T. Nagalaxmi, E. Sreenivasa Rao, P. ChandraSekhar","doi":"10.1007/s10470-024-02290-z","DOIUrl":"10.1007/s10470-024-02290-z","url":null,"abstract":"<div><p>Networks on Chip (NoCs) are a crucial component in modern System on Chips (SoCs), which provide the communication infrastructure for various processing elements such as CPUs, GPUs, DSPs, and other IPs. As a result, security is a critical aspect of NoCs, and it is essential to protect them from various security threats such as information leakage, denial of service attacks, and unauthorized access. The communication over NoCs carries sensitive and confidential information, which needs to be protected from unauthorized access, interception, or tampering. A Hybrid Secure technique is proposed in this research paper to protect the data during NoC transmission. The Noekeon and RSA algorithms are combined to create the hybrid secure algorithm for NoC architecture. The Noekeon algorithm provides a high level of security, efficiency, flexibility, and resistance to side-channel attacks, making it an ideal choice for securing communication in NoC and other applications. The RSA encryption algorithm is modified to minimize the number of calculations. The proposed hybrid secure algorithm is tested on 4 × 4 2D mesh NoC architecture. The average throughput of the proposed algorithm is increased to 64% and 51% latency is reduced when compared to existing research work.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"121 1-3","pages":"13 - 23"},"PeriodicalIF":1.2,"publicationDate":"2024-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142261545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A multiple resonant microstrip patch heart shape antenna for satellite and Wi-Fi communication 用于卫星和 Wi-Fi 通信的多谐振微带贴片心形天线

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-08-27 DOI: 10.1007/s10470-024-02281-0

A. Yogeshwaran

{"title":"A multiple resonant microstrip patch heart shape antenna for satellite and Wi-Fi communication","authors":"A. Yogeshwaran","doi":"10.1007/s10470-024-02281-0","DOIUrl":"10.1007/s10470-024-02281-0","url":null,"abstract":"<div><p>Microstrip antennas are in high demand because of their low profile and lightweight, leading to a recent surge in the need for low-profile antennas for wireless communications. Due to the growing significance of wireless communication in recent years, very inventive research has been conducted. By extending current trends, microstrip antennas provide solutions for various problems. A heart-shaped microstrip patch antenna was introduced in this proposed methodology. The shape of the microstrip patch antenna dimensions are 29 mm × 32 mm × 1.6 mm. The FR-4 substrate material is used in a heart-shaped antenna with a tangent loss is 0.02 and a dielectric constant is 4.4. the high-frequency structure simulator software is used to design and implement a heart-shaped microstrip patch antenna. The patch features four inverted L-shaped slots and one S-shaped slot to provide multiple resonant frequencies for satellite and WI-FI connectivity. At 0.9 GHz, 1.4 GHz, and 2.45 GHz, the antenna is in use. Its two lower working frequency bands show good symmetry in its radiation patterns. The antenna covers a range of frequencies, including WLAN (5.15–5.35 GHz), 5G (5.725–5.825 GHz), TD-LTE (B-TrunC) (1.447–1.467 GHz), LTE42/43 (3.4–3.8 GHz), WiMAX (3.3–3.8 GHz), 5G band n78 (3.4–3.8 GHz), and more bands. Furthermore, the measurement and construction of the prototype are finished. The results show that its gains at 0.9 GHz, 1.4 GHz, and 2.45 GHz are − 32.2 dBi, − 18.8 dBi, and − 19.1 dBi.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"121 1-3","pages":"1 - 11"},"PeriodicalIF":1.2,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142213018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low power content addressable memory using common match line scheme for high performance processors 采用通用匹配线方案的低功耗内容可寻址存储器，适用于高性能处理器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-08-03 DOI: 10.1007/s10470-024-02275-y

K. Muralidharan, S. Uma Maheswari, T. Balakumaran

{"title":"Low power content addressable memory using common match line scheme for high performance processors","authors":"K. Muralidharan, S. Uma Maheswari, T. Balakumaran","doi":"10.1007/s10470-024-02275-y","DOIUrl":"10.1007/s10470-024-02275-y","url":null,"abstract":"<div><p>Content Addressable Memory (CAM) is utilized in Artificial Neural Networks, data compression, IP packet filtering, and network routers due to its high performance in the microprocessor. However, the use of CAM is limited because of its increased power consumption, especially in high capacitive Match-Lines (ML). The activation of every comparison circuit on every clock cycle is primarily responsible for the significant power dissipation, which leads to increased recharge activity and multiple transition occurrences in the ML. In order to overcome this issue, a novel Common Match Line Scheme (CMS) with a Pull Up/Pull Down (PUPD) Circuit is proposed. The new design of the CMS CAM architecture leverages by utilizing these technique, the mismatched tagline entries are kept in the pre-discharged phases, and only the matching tagline entry gets charged. Consequently, these approaches effectively reduce pre-charge activity and mitigate evaluate-power, thereby alleviating power dissipation concerns associated with CAM 13–45% and reducing delay 3–16% while comparing to the existing architectures without significant impact on the performance of the processor. Proposed CMS CAM outperforms the existing architectures in terms of noise also with minimal area overhead and it is a technology independent one which can be used in high performance microprocessor systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 2-3","pages":"183 - 194"},"PeriodicalIF":1.2,"publicationDate":"2024-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An ultra-low power fully CMOS sub-bandgap reference in weak inversion 弱反相超低功率全 CMOS 亚带隙基准器件

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-15 DOI: 10.1007/s10470-024-02289-6

Reza Mohammadi Nowruzabadi, Javad Mostofi Sharq, Emad Ebrahimi

{"title":"An ultra-low power fully CMOS sub-bandgap reference in weak inversion","authors":"Reza Mohammadi Nowruzabadi, Javad Mostofi Sharq, Emad Ebrahimi","doi":"10.1007/s10470-024-02289-6","DOIUrl":"10.1007/s10470-024-02289-6","url":null,"abstract":"<div><p>This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 2-3","pages":"173 - 182"},"PeriodicalIF":1.2,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141647923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Secure and reliable communication using memristor-based chaotic circuit 利用基于忆阻器的混沌电路实现安全可靠的通信

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-13 DOI: 10.1007/s10470-024-02278-9

Usha Kumari, Rekha Yadav

{"title":"Secure and reliable communication using memristor-based chaotic circuit","authors":"Usha Kumari, Rekha Yadav","doi":"10.1007/s10470-024-02278-9","DOIUrl":"10.1007/s10470-024-02278-9","url":null,"abstract":"<div><p>This research paper demonstrates behavior of memristor emulator circuit at various input frequencies. It is a critical circuit having a vast potential for constructing digital and analog circuits, FM-to-AM converters, filters, cellular neural networks, sensors, analog circuits, and chaotic oscillators are all designed with memristor circuits. It has some unique properties such as nonlinear behaviour, analog signal processing, adaptive and reconfigurable system, memory and state retention and also high density and low power consumption. These properties build the communication system more reliable secure and more efficient. To enhance the design of the memristor model, implementation doing using analog multiplier and operational transconductance amplifier with a constant transcoductance gain is employed. In addition to the input supply voltage frequency (f) and amplitude (Vm), the operational transconductance amplifier provides a control parameter known as the transconductance (gm). Modifications in amplitude have an impact on memory resistance, and variations in biassing voltage influence transconductance (gm) of OTA. The research shows memristor-based chaotic circuit use for secure transmission system. The operational frequency that exhibits the maximum value is 10 kilohertz, accompanied by a power dissipation of 24.1 microwatts with noise <span>(51.9text{ nV}/{text{Hz}}^{1/2})</span> at room temperature. This study employs a circuit electronic design automation (EDA) tool to demonstrate the behavior of a memristor circuit under varying input conditions.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 2-3","pages":"155 - 171"},"PeriodicalIF":1.2,"publicationDate":"2024-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141611960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quad ports flexible MIMO antenna with connected ground and high isolation for UWB applications 用于 UWB 应用的四端口柔性 MIMO 天线，具有连接地线和高隔离度功能

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-09 DOI: 10.1007/s10470-024-02280-1

Heba Aboelleil, Ashraf A. M. Khalaf, Ahmed A. Ibrahim

{"title":"Quad ports flexible MIMO antenna with connected ground and high isolation for UWB applications","authors":"Heba Aboelleil, Ashraf A. M. Khalaf, Ahmed A. Ibrahim","doi":"10.1007/s10470-024-02280-1","DOIUrl":"10.1007/s10470-024-02280-1","url":null,"abstract":"<div><p>This study proposes a flexible MIMO antenna with improved isolation and connected ground designed on a flexible substrate that makes it compatible with various shapes and surfaces, including curved, irregular, or non-planar structures. The suggested single unit consists of a slotted rectangular radiator on the front layer with a partial ground connected to a circular stub on the other side. As well it is created on a flexible substrate (Rogers RO3003) that has a dielectric constant (ε<sub>r</sub>) of 3 and a thickness of 1.52 mm. The Four copies of the single unit with orthogonal orientation are added to improve the system performance. The antenna units are connected through their ground to introduce the connected ground antenna. The size of the proposed design is compact (50 × 50 × 1.524 mm<sup>3)</sup>. The simulating and testing results demonstrate that the antenna operates within a frequency range of 3–12 GHz and achieves a high isolation of ≥ 17 dB over most frequency range. The MIMO parameters and the radiation patterns are analyzed to evaluate the performance of the MIMO antenna. Finally, the four elements of the flexible antenna are fabricated and tested under flat and bending conditions. The simulation and testing results demonstrate that the suggested design exhibits excellent performance, such as broad bandwidth, high isolation, simple structure, and decreased correlation coefficient, which suggest it for the UWB applications and its flexibility allows it for integration into a wide range of devices, such as wearable technology, Internet of Things (IoT) devices, and curved surfaces of vehicles or aircraft.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"59 - 70"},"PeriodicalIF":1.2,"publicationDate":"2024-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and design of a GHz bandwidth adaptive bias circuit for an mmW Doherty amplifier 分析和设计用于毫米波 Doherty 放大器的 GHz 带宽自适应偏置电路

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-07 DOI: 10.1007/s10470-024-02288-7

Christian Elgaard, Henrik Sjöland

{"title":"Analysis and design of a GHz bandwidth adaptive bias circuit for an mmW Doherty amplifier","authors":"Christian Elgaard, Henrik Sjöland","doi":"10.1007/s10470-024-02288-7","DOIUrl":"10.1007/s10470-024-02288-7","url":null,"abstract":"<div><p>This paper derives theoretical results for adaptive bias in Doherty amplifiers and presents the design and measurements of an integrated adaptive bias circuit tailored for high peak-to-average high bandwidth signals. Fundamental equations for output power, impedance, and efficiency of the complete Doherty amplifier are derived. Even with ideal transistor models, the Doherty amplifier is fundamentally nonlinear due to saturation of the main amplifier and class-C nonlinearity of the auxiliary. Increasing the transconductance of the auxiliary amplifier mitigates the distortion. Adaptive bias offers the possibility to control the output current characteristic of the auxiliary amplifier. This means that adaptive bias linearises and mitigates the need for an oversized auxiliary amplifier. Both methods, transconductance scaling and adaptive bias, are analysed and compared as well as having a band limited adaptive bias signal. The design of a multiple GHz bandwidth adaptive bias circuit is presented. To verify the circuit design and the theoretical predictions, an mmW Doherty amplifier in 22 nm CMOS-FD-SOI, utilizing the presented adaptive bias circuit, is measured and compared with and without adaptive bias. Comparison is conducted both using continuous-wave and modulated high bandwidth signals. Measured results confirm the predicted improvements by the adaptive bias as derived by the theoretical analysis.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"39 - 58"},"PeriodicalIF":1.2,"publicationDate":"2024-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02288-7.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0