Analog Integrated Circuits and Signal Processing最新文献

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Optimal charging of nonlinear capacitors in RC and LRC circuits with bypass resistor
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-26 DOI: 10.1007/s10470-025-02398-w
Lingen Chen, Shaojun Xia
{"title":"Optimal charging of nonlinear capacitors in RC and LRC circuits with bypass resistor","authors":"Lingen Chen,&nbsp;Shaojun Xia","doi":"10.1007/s10470-025-02398-w","DOIUrl":"10.1007/s10470-025-02398-w","url":null,"abstract":"<div><p>The optimal-charging problem of nonlinear capacitors in RC and LRC circuits with bypass resistor is investigated by utilizing finite-time thermodynamics. Under condition that both charging time and total energy stored in capacitors are given, the optimal time-paths of source-voltage and capacitor-voltage for the minimum Joule heat dissipation of circuits are determined by applying optimal-control theory. Analytical solutions for linear capacitor case are derived based on universal optimal results, and optimal strategies are also compared with linear and constant source-voltage operation charging strategies. While for the nonlinear capacitor cases, numerical solutions are obtained, and effects of various parameters on optimal results are analyzed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143877723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Antenna design for RFID: a comparative investigation in near field communication and electronic article surveillance systems
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-26 DOI: 10.1007/s10470-025-02403-2
Muhammad Noaman Zahid, Liu Jiajun
{"title":"Antenna design for RFID: a comparative investigation in near field communication and electronic article surveillance systems","authors":"Muhammad Noaman Zahid,&nbsp;Liu Jiajun","doi":"10.1007/s10470-025-02403-2","DOIUrl":"10.1007/s10470-025-02403-2","url":null,"abstract":"<div><p>This paper presents an overview of antenna designs for passive radio frequency identification (RFID) tags for near field communication (NFC) and electronic article surveillance (EAS) systems. We discussed several antenna designs such as handheld reader antennas and fixed reader antennas for various applications. The paper also provides a brief discussion on RFID technology with its current state-of-the-art applications. We compare NFC and EAS technologies by reviewing contemporary research in these with reported antenna designs and applications. The paper discusses the design procedure for these antennas along with their characteristics and results. Moreover, the results presented by different researchers have been discussed in detail. It has been observed from the presented literature that RFID technology is key to many existing as well as future applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143877719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A voltage reference implemented in GaAs pHEMT for SoC application
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-24 DOI: 10.1007/s10470-025-02368-2
Tingwei Gong, Zhiqun Cheng, Zhekan Ni, Chao Le, Daopeng Li, Xuefei Xuan, Zhiwei Zhang, Bangjie Zheng
{"title":"A voltage reference implemented in GaAs pHEMT for SoC application","authors":"Tingwei Gong,&nbsp;Zhiqun Cheng,&nbsp;Zhekan Ni,&nbsp;Chao Le,&nbsp;Daopeng Li,&nbsp;Xuefei Xuan,&nbsp;Zhiwei Zhang,&nbsp;Bangjie Zheng","doi":"10.1007/s10470-025-02368-2","DOIUrl":"10.1007/s10470-025-02368-2","url":null,"abstract":"<div><p>Using III-V compound semiconductor materials, particularly gallium arsenide (GaAs) devices instead of compared to silicon-based complementary metal oxide semiconductor, a voltage reference (VR) circuit applied for radio frequency (RF) applications with significant advantages in RF performance is proposed in the paper. Given lattice defects, GaAs pseudomorphic high electron mobility transistor (pHEMT) technology faces difficulties in realizing P-channel metal oxide semiconductor devices, necessitating new circuit structures to achieve the functionality of traditional VRs. To leverage the superior RF performance of compound semiconductors in implementing RF transceiver systems-on-chip, this paper proposes a VR based on GaAs pHEMT technology. The proposed VR circuit was fabricated and tested using a 0.15 μm GaAs pHEMT process. The test results demonstrated that the designed VR circuit exhibits a current load capability of 17 mA, a temperature coefficient of 186 ppm/℃, and a power line regulation of 22.5 mV/V. This VR circuit occupies a total chip area of 0.2 mm<sup>2</sup> and can be applied to wireless fidelity or other transceiver systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2-way interleaving 3-tap analog feedforward equalization for high-speed analog multiplexing
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-23 DOI: 10.1007/s10470-025-02387-z
Thomas Gorzka, Mark Ingels, Xin Wang, Joris Van Kerrebrouck, Nishant Singh, Guy Torfs, Johan Bauwelinck, Jan Craninckx, Piet Wambacq
{"title":"A 2-way interleaving 3-tap analog feedforward equalization for high-speed analog multiplexing","authors":"Thomas Gorzka,&nbsp;Mark Ingels,&nbsp;Xin Wang,&nbsp;Joris Van Kerrebrouck,&nbsp;Nishant Singh,&nbsp;Guy Torfs,&nbsp;Johan Bauwelinck,&nbsp;Jan Craninckx,&nbsp;Piet Wambacq","doi":"10.1007/s10470-025-02387-z","DOIUrl":"10.1007/s10470-025-02387-z","url":null,"abstract":"<div><p>With the rapid growth of data traffic, there is an increasing demand for larger bandwidths in fixed networks. The transmitter bandwidth extension is usually achieved by combining analog multiplexers (AMUX) with digital-to-analog converters (DAC) designed in CMOS. Additionally, feedforward equalization (FFE) is incorporated at the high-speed front-end. However, this adds complexity and significant power consumption. In this work, we describe an alternative FFE approach that reduces the complexity of power-hungry high-speed front-ends, thereby improving power efficiency. This approach uses a 28 nm CMOS chip that sends two outputs with FFE predistorted data at 40/80 Gbps NRZ/PAM4. When combined with an AMUX, it generates equalized eye diagrams at 80/160 Gbps NRZ/PAM4 after a channel model with an insertion loss of 8.4 dB at 40 GHz, with a voltage swing of 100 mVpp,diff/190 mVpp,diff, while dissipating 0.889 W of power (5.56 pJ/bit).</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143865508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimised elliptic curve cryptography architecture for improved V2x communication
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-23 DOI: 10.1007/s10470-025-02378-0
S. Vijayakumar, M. Mathivanan, M. Sathiya, A. Kamaraj
{"title":"Optimised elliptic curve cryptography architecture for improved V2x communication","authors":"S. Vijayakumar,&nbsp;M. Mathivanan,&nbsp;M. Sathiya,&nbsp;A. Kamaraj","doi":"10.1007/s10470-025-02378-0","DOIUrl":"10.1007/s10470-025-02378-0","url":null,"abstract":"<div><p>Today’s world, communication devices installed in roadside, pedestrians, and all moving entities can able to communicate with each other, through the vehicular to anything communication called as V2X. These communications have to taken in to account security and privacy issues also. The aim of this research work is to provide secured cryptographic techniques to help the vehicles in obtaining necessary keys and information from Roadside Units (RSU), the data network, or from other vehicles while also ensuring a highest security in different ways of vehicular communication (V2I, V2V, and V2N). One of the many cryptographic methods that provide the solution to the objective is Elliptic Curve Cryptography (ECC). The fundamental operations of ECC such as point multiplication and point addition are carried out for 256-bits; also the proposed ECC processor follows the Koblitz curve secp256k1. “Divide and Conquer” is being followed in Karatsuba algorithm to increase speed of multiplication process. The incorporation of Pipelining also increases the speed of the multiplication on the ECC processor with additional area overhead. The novel Karatsuba ECC processor operates at a clock frequency of 238.40 MHz, computing point multiplication of 256-bit in 0.937 ms, throughput of 273.21kbps and area is 8.42 k slices in a FPGA Virtex-7. Integrating Pipelining in the proposed system increases the clock frequency up to 7.97%. Because of it, the time consumption is reduced by 9.90% and throughput is increased by 10.99%. This novel ECC processor performs well compared to the existing methods in terms of area-delay product, operating frequency, throughput and area.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143865507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SEC-DED-Hsiao code protection for SRAM memories used in space applications
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02391-3
Ghenam Dahmane, Benabdellah Yagoubi
{"title":"SEC-DED-Hsiao code protection for SRAM memories used in space applications","authors":"Ghenam Dahmane,&nbsp;Benabdellah Yagoubi","doi":"10.1007/s10470-025-02391-3","DOIUrl":"10.1007/s10470-025-02391-3","url":null,"abstract":"<div><p>The low cost of commercial-off-the-shelf static random access memory (SRAM) devices allows wide use in space applications. The proper functioning of microsatellites in orbit is ensured by data and instruction set (program) stored in these devices. The SRAM memory that operates in the space environment risks data corruption due to single-event upset (SEU) and single-event multiple-bit upset. Therefore error detection and correction (EDAC) based on shortened Hamming (12,8) code and quasi-cyclic (16,8) code are ordinarily used for protecting the SRAM against errors due to SEU. The proposed EDAC is based on the Single Error Correcting and Double Error Detecting Hsiao (72,64) code which is compared with the two previous EDACs in terms of the number of Field Programmable Gate Array that implements these codes, delay time for encoding/decoding operations, memory overhead, and error detection and correction capability.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A compact flexible dual band coplanar waveguide fed antenna for 5 G applications 用于 5 G 应用的紧凑型灵活双频共面波导馈电天线
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02393-1
Abhilash S. Vasu, T. K. Sreeja
{"title":"A compact flexible dual band coplanar waveguide fed antenna for 5 G applications","authors":"Abhilash S. Vasu,&nbsp;T. K. Sreeja","doi":"10.1007/s10470-025-02393-1","DOIUrl":"10.1007/s10470-025-02393-1","url":null,"abstract":"<div><p>A novel, compact, and flexible dual-band ring-shaped radiating antenna with coplanar waveguide (CPW) feed is proposed for 5G applications. The radiating elements are printed on top of substrate with dimension 29 × 21.3 mm<sup>2</sup> and a compact radiating structure is obtained by setting the width of main radiating element and signal strip that are same. To enhance the radiation characteristics of lower and upper band, two rectangular stubs are used. The flexibility of antenna is examined by a convex E-plane bending with radius of 50 mm. The simulated and fabricated antenna have good matching results (bend antenna and without bend antenna). The measured result produces a 10-dB impedan2ce bandwidth of 1.35 GHz (3.17–4.52 GHz) for lower band and a 1.59 GHz (5.71–7.30 GHz) for upper band for covering all 5G bands in lower and upper 3.5 GHz, lower and upper 6 GHz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of the polarity reversal effect of memristor and memristor fuse in 2D cellular nonlinear network
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02395-z
Aliyu Isah
{"title":"Comparison of the polarity reversal effect of memristor and memristor fuse in 2D cellular nonlinear network","authors":"Aliyu Isah","doi":"10.1007/s10470-025-02395-z","DOIUrl":"10.1007/s10470-025-02395-z","url":null,"abstract":"<div><p>Memristor sparks interest in neuromorphic and bioinspired systems owing to its dynamic conductance, which resembles chemical synapse. However, the conductivity of a memristor depends strongly on the amount and direction of the flowing charge through it, and it is primarily due to its intrinsic asymmetry. This phenomenon becomes disadvantageous and a massive hindrance to consider memristors in some biomimetic networks, such as memristive grid networks, where sensitivity of direction is important. This drawback can be avoided by using memristor fuse which is formed by connecting two identical memristors anti-serially. To effectively compare the polarity reversal effect of these circuit elements, a network of 2 RC cells in the form of passive neurons coupled by a memristor and then a memristor fuse is considered, thereby allowing to observe and compare the interaction of these circuit elements bidirectionally. The system is studied analytically and the result is visualized in the phase plane. The comparison is done by observing the evolution patterns of the trajectories with respect to the direction of flow of the charge through these circuit elements. In terms of functionality as demonstrated in this paper, the memristor fuse shows a promising symmetry with respect to the quantity and direction of the flowing charge through it.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Off-the shelf components-based inverse memristor emulator and its application in bandwidth extension of memristor emulator
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02410-3
Praveen Kumar, Mayank Srivastava
{"title":"Off-the shelf components-based inverse memristor emulator and its application in bandwidth extension of memristor emulator","authors":"Praveen Kumar,&nbsp;Mayank Srivastava","doi":"10.1007/s10470-025-02410-3","DOIUrl":"10.1007/s10470-025-02410-3","url":null,"abstract":"<div><p>The article explores the application of a reverse memristor emulator utilizing easily accessible components. This emulator comprises two Operational Amplifiers (Op-amps), one Operational Transconductance Amplifier (OTA), and two passive elements. The utilization of Op-Amps and OTA renders the circuit effortlessly implementable with commercially accessible Integrated Circuits (ICs), presenting a notable advantage of the suggested architecture. Upon close examination of the proposed design, accounting for terminal parasitics and non-ideal gains, the observed behavior closely matches the ideal characteristics of the circuit. The emulator’s functionality underwent testing in the PSPICE simulation environment, considering the 0.18 μm technology. The credibility of the proposed circuit concept was further substantiated by employing widely available ICs like µA741 and LM13700, with the results extensively discussed. Furthermore, the article showcases an essential application of this emulator by enhancing the bandwidth of a low-frequency memristor emulator. At last, the experimental results are also demonstrated to validate the reported application.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Control of off-board bidirectional plug-in electric vehicle charger using a hybrid optimization approach 使用混合优化方法控制车外双向插电式电动汽车充电器
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02372-6
Manickam Vinoth Kumar, K. Dhayalini
{"title":"Control of off-board bidirectional plug-in electric vehicle charger using a hybrid optimization approach","authors":"Manickam Vinoth Kumar,&nbsp;K. Dhayalini","doi":"10.1007/s10470-025-02372-6","DOIUrl":"10.1007/s10470-025-02372-6","url":null,"abstract":"<div><p>In the modern era, Electric Vehicles (EVs) have gained immense consideration in developed nations due to diminished usage of fossil fuels as well as lessening the release of gases that cause global warming. Radiation of Greenhouse gases in the atmosphere can be diminished by the utilization of EVs. The charging component is essential for PEVs, as they require electricity from the power grid to charge their batteries. With the appropriate control, the existing charger’s converter architecture can offer additional functionalities. The expansion of Off-board fast-CS is the primary cause of the widespread utilization of EVs. The demand for load increases when the EV battery is charged from the grid. This study examines the application of a V2G-enabled bidirectional off-board EV battery charger using the HBIAO and AIChOa algorithm. The HBIAO algorithm inherits the characteristics and features of Honey Badger and Aquila Optimization Algorithm, while AIChOa algorithm inherits the features of Sooty Tern Optimization Algorithm and Chimp Optimization Algorithm (ChOA). The hybrid optimization algorithms assist in the achievement of global optimal solutions, neglecting the local optimal solutions. The proposed EV charger is modeled and simulated in MATLAB/Simulink, and the controller’s efficiency is validated. The simulation findings show that the system can function efficiently compared to various traditional methodologies. With different simulation and testing outcomes, quick dynamic reactions and excellent steady-state system performances can be demonstrated.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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