Analog Integrated Circuits and Signal Processing最新文献

A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers 输出匹配射频功率放大器效率的研究

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-17 DOI: 10.1007/s10470-025-02517-7

Davide Pecile, Alberto Gambarrucci, Stefan Kokorovic, Andrea Bevilacqua

引用次数: 0

Design of miniaturized graphene-based reconfigurable fourth-order quasi-elliptic SIW filter in the THz band 太赫兹波段小型化石墨烯可重构四阶拟椭圆SIW滤波器设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-15 DOI: 10.1007/s10470-025-02519-5

Narges Kiani, Majid Afsahi, Farzad Tavakkol Hamedani, Pejman Rezaei

{"title":"Design of miniaturized graphene-based reconfigurable fourth-order quasi-elliptic SIW filter in the THz band","authors":"Narges Kiani, Majid Afsahi, Farzad Tavakkol Hamedani, Pejman Rezaei","doi":"10.1007/s10470-025-02519-5","DOIUrl":"10.1007/s10470-025-02519-5","url":null,"abstract":"<div><p>The inimitable and terrific attributes of graphene have drawn attention to this 2D carbon allotrope for a vast range of applications in science. One of the tools to achieve the integration of planar and non-planar circuits is substrate integrated waveguide technology. The reason is the use of the planar manufacturing procedure. This work offers a fourth-order quasi-elliptic graphene-based substrate integrated waveguide filter. The designed filter is wideband. Other essential features of this filter include frequency reconfigurability and miniaturization. In summary, the innovation of a graphene-based reconfigurable fourth-order quasi-elliptic SIW filter in the THz band combines advanced materials science with cutting-edge filter design, resulting in a versatile and high-performance component suitable for next-generation THz systems. The three transmission zeroes (TZs) of this quasi-elliptic fourth-order graphene-based substrate integrated waveguide filter are located at 10.1 THz, 13.3 THz, and 15 THz. The poles of this quasi-elliptic fourth-order graphene-based substrate integrated waveguide filter are located in these four positions: 10.4 THz, 11.7 THz, 12.1 THz, and 12.5 THz, respectively. The central frequency (f<sub>0</sub>) of the filter is located at 11.6 THz. The perfect bandwidth of the quasi-elliptic fourth-order graphene-based substrate integrated waveguide filter is estimated at about 2 THz. It’s placed on a single-layer substrate from silicon dioxide (SiO<sub>2</sub>) material. The results of this structure exhibit a suitable selectivity, and an insertion loss of 1.8 dB. Fractional bandwidth is estimated at about 17.24%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145296789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A design and simulation methodology for radio frequency receiver front-ends with frequency selective limiting devices 具有频率选择限制装置的射频接收器前端设计与仿真方法

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-09 DOI: 10.1007/s10470-025-02518-6

Yunfan Gao, Hussein M. E. Hussein, Mengting Yan, Chunan Chen, Miriam Leeser, Cristian Cassella, Marvin Onabajo

引用次数: 0

60µW high precision fully integrated in-vivo impedance spectroscopy using synchronous detection of magnitude and phase 60µW高精度全集成体内阻抗谱，采用同步检测幅度和相位

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-09 DOI: 10.1007/s10470-025-02516-8

Moustafa Nawito

引用次数: 0

An improved exploration–exploitation mechanism of reptile search algorithm for quadrature mirror filter bank design and its FPGA implementation 一种改进的爬行动物搜索算法在正交镜像滤波器组设计中的探索利用机制及其FPGA实现

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-09 DOI: 10.1007/s10470-025-02495-w

Raina Modak Aich, Supriya Dhabal, Palaniandavar Venkateswaran

{"title":"An improved exploration–exploitation mechanism of reptile search algorithm for quadrature mirror filter bank design and its FPGA implementation","authors":"Raina Modak Aich, Supriya Dhabal, Palaniandavar Venkateswaran","doi":"10.1007/s10470-025-02495-w","DOIUrl":"10.1007/s10470-025-02495-w","url":null,"abstract":"<div><p>This paper presents an enhanced version of the Reptile Search Algorithm (RSA) based on the Differential Evolution (DE). In the proposed RSADE algorithm, the exploration and exploitation phases of RSA are enriched by the DE mutation phase. This is done to avoid trapping solutions into both global and local minima. The proposed algorithm is used to design a Near-Perfect Reconstruction (NPR) Quadrature Mirror Filter (QMF) bank. A minimized closed-form objective function is constructed by combining the values of pass-band ripple, amplitude distortion, transition-band error, and stop-band error. Initially, a test on standard IEEE CEC 2014 benchmark functions is performed, where the RSADE algorithm obtains rank 1. Compared to the current cutting-edge algorithms, the proposed algorithm exhibits a 26.79% increase in stop-band attenuation, 90.90%, 80.39%, 75.59%, 75.85%, and 67.10% decrease in transition-band error, stop-band error, pass-band error, overall amplitude distortion, and peak reconstruction error, respectively. Further, the proposed design is simulated with the Xilinx ISE Design Suite and executed on three Field Programmable Gate Array (FPGA) platforms using Spartan 6, Virtex 5, and Kintex 7 for filter tap 32. For instance, the average improvements in Spartan 6 compared to some recent algorithms are 4.75%, 6.78%, 5.07%, and 0.06% in the number of slice LUTs, occupied slices, fully used LUT-FF pairs, and total power consumption, respectively. The experimental outcomes of the proposed algorithm show its improvement in solving complex multimodal problems compared to the existing state-of-the-art algorithms.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145256210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of CMOS low power variable gain amplifier for biomedical applications 生物医学用CMOS低功率变增益放大器的设计与分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-08 DOI: 10.1007/s10470-025-02521-x

Rahma Aloulou, Maroua Ben Belgacem, Sawssen Lahiani, Hassen Mnif, Mourad Loulou

{"title":"Design and analysis of CMOS low power variable gain amplifier for biomedical applications","authors":"Rahma Aloulou, Maroua Ben Belgacem, Sawssen Lahiani, Hassen Mnif, Mourad Loulou","doi":"10.1007/s10470-025-02521-x","DOIUrl":"10.1007/s10470-025-02521-x","url":null,"abstract":"<div><p>This study falls within the radio frequency transmission of biomedical applications, where the variable gain amplifier (VGA) presents a key element since it adjusts the radio receiver performance. Due to the sensitivity of this field, the VGA must respect the imposed constraints. In this contribution, an optimized VGA structure in CMOS technology for biomedical applications is proposed. It realizes considerable improvements over the existing characteristics of biomedical signal processing by ensuring a wide dynamic range and low power topology and noise. The optimizations are performed at two levels; architectural and dimensional. For the architecture, the optimization is mainly presented by the addition of a telescopic operational transconductance amplifier and Common Mode Feedback circuit blocks to an optimized VGA cell in order to extend the gain variation range. As for the dimensional optimization, based on a heuristic maximization methodology, an optimization algorithm is developed to adjust the optimal dimensioning of the VGA structure that achieves significant performance improvements. In fact, it presents a reliable low power topology (consumption of 33.52 µW), which ensures a wide dynamic gain range that reaches 89.65 dB varying from − 19.72 dB to 69.93 dB.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145256428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermally Stable and Cost-Efficient QCA-Based Co-Planar Design of a 4-Bit CSA with Optimized Cell Size Scaling 基于优化单元尺寸缩放的4位CSA共面设计的热稳定和成本效益qca

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-10-08 DOI: 10.1007/s10470-025-02510-0

Hemanshi Chugh, Sonal Singh

{"title":"Thermally Stable and Cost-Efficient QCA-Based Co-Planar Design of a 4-Bit CSA with Optimized Cell Size Scaling","authors":"Hemanshi Chugh, Sonal Singh","doi":"10.1007/s10470-025-02510-0","DOIUrl":"10.1007/s10470-025-02510-0","url":null,"abstract":"<div><p>Quantum-dot Cellular Automata (QCA) offers a promising paradigm for ultra-low-power nanoscale computing. This paper introduces a novel co-planar design of a 4-bit, three-input carry-save adder (QCA-3<span>(times)</span>4B-CSA), leveraging an optimized full adder structure to enhance performance, reduce area, and minimize quantum cost. The proposed architecture is developed using QCADesigner v2.0.3 and benchmarked against state-of-the-art CSA implementations across multiple cell sizes (18<span>(times)</span>18 <i>nm</i>, 16<span>(times)</span>16 <i>nm</i>, and 14<span>(times)</span>14 <i>nm</i>). The proposed design achieves a 76.35% reduction in quantum cost compared to recent CSA implementations, while also minimizing cell count, layout area, and delay. Energy dissipation metrics is evaluated using QCAPro and QCADesigner-E, confirming significant energy efficiency. Thermal analysis further reveals robust output polarization stability up to 8<i>K</i>, demonstrating the circuit’s resilience under cryogenic conditions. Notably, the 14<span>(times)</span>14 <i>nm</i> cell layout delivers superior results across all performance metrics. These findings establish the QCA-3<span>(times)</span>4B-CSA as robust and scalable solution for future nano scale digitalarithmetic systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145256427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel direct calculation algorithm using Taylor expansion in FPGA for DDS signal quality enhancement 在FPGA中提出了一种新的直接计算算法，用于DDS信号质量的增强

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-30 DOI: 10.1007/s10470-025-02473-2

Dingyi Ma, Ze Liu, Jingming Cao, Junjie Li, Zewen Wan, Yizhou Zhou

{"title":"A novel direct calculation algorithm using Taylor expansion in FPGA for DDS signal quality enhancement","authors":"Dingyi Ma, Ze Liu, Jingming Cao, Junjie Li, Zewen Wan, Yizhou Zhou","doi":"10.1007/s10470-025-02473-2","DOIUrl":"10.1007/s10470-025-02473-2","url":null,"abstract":"<div><p>The precision measurement of capacitance necessitates the utilisation of a precision capacitance bridge, wherein a sine signal serves as a reference. Consequently, the precision of the sine signal is of paramount importance for the precision measurement of capacitance. In the conventional method of generating a sine signal, a look-up table is employed as the data source. However, the look-up table approach necessitates an excessive amount of read-only memory space to fulfil the requirements of high-precision scenarios. In this paper, we proposes an novel algorithm based on Taylor expansion to calculate the sine function. This algorithm doesn’t use any read-only storage space. Compared with the Coordinate Rotation Digital Computer algorithm in computer, it is based on the pipelined architecture to balance latency and digital signal processor resource consumption. For the Lagrange residual term error problem of Taylor expansion, the optimization algorithm using trigonometric periodicity and the complementary algorithm of sine and cosine functions is proposed. To evaluate the accuracy of the sine function generated by the algorithm, direct digital synthesis and digital to analog converter outputs are utilized to improve the accuracy and enhance the total harmonic distortion as compared to the conventional algorithm.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient hilbert envelope and factor analysis based Estimation of R-peaks in ECG signal 基于希尔伯特包络和因子分析的心电信号r -峰估计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-30 DOI: 10.1007/s10470-025-02508-8

Varun Gupta, Vikas Mittal, Monika Mittal, Sandeep Santosh, Zahied Azam

{"title":"An efficient hilbert envelope and factor analysis based Estimation of R-peaks in ECG signal","authors":"Varun Gupta, Vikas Mittal, Monika Mittal, Sandeep Santosh, Zahied Azam","doi":"10.1007/s10470-025-02508-8","DOIUrl":"10.1007/s10470-025-02508-8","url":null,"abstract":"<div><p>In the present situation of health informatics, appropriate pre-processing tools are necessary to judge actual condition. In this direction, Electrocardiogram (ECG) is the right tool which shows electrical activity of the heart. This tool gives its output in the form of electrical signal having three different wave components namely; P-wave, QRS wave (complex), and T-wave. In this paper combination of three efficient techniques viz. Digital bandpass filtering (DBPF), Hilbert envelope, and Factor analysis is used for ECG signal analysis. The analysis of ECG signal is done by estimating position of R-peaks in MIT-BIH Arrhythmia (MIT-BIH Arr) database. The proposed technique has proved its utility in cardiology by establishing Sensitivity (Se) of 99.95%, Positive Predictivity (Pp) of 99.97%, Accuracy (Acc) of 99.92% and Signal-to-Noise Ratio (SNR) of 37.71dB in considered 18 datasets of MIT-BIH Arr database. In the common datasets used by different researchers, the proposed methodology secured Se of 99.98%, Pp of 99.98%, Acc of 99.96%, and SNR of 39.78dB. The proposed methodology is also compared with well established research works and showing significant improvements in their parameters viz. Se, Pp and Acc. Different work proposed by various authors on ECG signal analysis have been compared. The proposed technique is definitely important for medical engineering applications in estimating correct health condition (by R-peaks detection).</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance characterization of compact pentagon-based 4 × 4 and 8 × 8 MIMO antennas 基于五角大楼的紧凑4 × 4和8 × 8 MIMO天线的性能表征

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-27 DOI: 10.1007/s10470-025-02491-0

Shibani Tripathy, Diptimayee Konhar, Ananda Kumar Behera

{"title":"Performance characterization of compact pentagon-based 4 × 4 and 8 × 8 MIMO antennas","authors":"Shibani Tripathy, Diptimayee Konhar, Ananda Kumar Behera","doi":"10.1007/s10470-025-02491-0","DOIUrl":"10.1007/s10470-025-02491-0","url":null,"abstract":"<div><p>This manuscript presents a 4-element (40 × 40 mm<sup>2</sup>) and 8-element (80 × 80 mm<sup>2</sup>) Multiple-Input Multiple-Output (MIMO) antenna designed for 5th generation technology within the sub-6 GHz frequency range. Each element of the MIMO antenna, which comprises a perturbed pentagon rectangular-cut antenna, is arranged in an orthogonal configuration on a single substrate. To ensure optimal performance, a circular ring-like strip is added on the pentagon-shaped patch. The novel printed sub-6 GHz antenna is fed by a microstrip line. Parallel strips (4-element) and corner isolating strips on the ground plane (8-element) are the key segments that improve isolation. The unique MIMO antenna design contributes to the desired return loss and isolation characteristics. The achieved parameters for the designed antenna; Envelope Correlation Coefficient (ECC) < 0.002, Diversity Gain (DG) ≈9.99 dB and Channel Capacity Loss (CCL) < 0.1bps/ Hz, show acceptable MIMO performance. This design will support large-scale IoT utilization with better dependability and data throughput.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0