Analog Integrated Circuits and Signal Processing最新文献

Design of 32 × 32 (1 KB) SRAM array using 10T SRAM cell for portable low power biomedical applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-27 DOI: 10.1007/s10470-025-02386-0

Appikatla Phani Kumar, Rohit Lorenzo

{"title":"Design of 32 × 32 (1 KB) SRAM array using 10T SRAM cell for portable low power biomedical applications","authors":"Appikatla Phani Kumar, Rohit Lorenzo","doi":"10.1007/s10470-025-02386-0","DOIUrl":"10.1007/s10470-025-02386-0","url":null,"abstract":"<div><p>Biomedical applications like body area networks (BAN) necessitate the construction of power optimized SRAMs to enhance the batteries life at BAN nodes. In this work, we have designed one-sided near threshold 10TSRAM array for low power portable biomedical applications. The proposed near threshold 10T SRAM (PNT10T SRAM) employs a cross-connected schmitt trigger (ST) inverter and normal inverter in its cell core. The separate path for reading is also employed to eliminate the reading disturbance. The write disturbance is removed in the PNT10T SRAM by removing the trail from VDD and ground. The writing ability is improved with the use of feedback-cutting approach. The standby power dissipation of the memory is mitigated with the use a tail transistor, virtual ground (VGND). The proposed design mitigates the half-select problem due to column-based transistor controlled by CCL. To evaluate the performance, the PNT10T SRAM is compared with C6T, ST11T, ST9T, TG9T, SE9T, and SLE10T SRAM cells using FinFET 18 nm technology at 0.6 V power supply. The PNT10T SRAM mitigates the read power, write power, and leakage power by 51.10%, 50.57%, and 78.97%. Furthermore, the read and write static noise margins improved by 54% and 39.5% respectively, compared to conventional6T (C6T) SRAM.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Privacy preserved two factor authentication system using spread spectrum watermarking of fingerprint and crypto code

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-27 DOI: 10.1007/s10470-025-02369-1

Priyanka Priyadarshini, Kshiramani Naik

{"title":"Privacy preserved two factor authentication system using spread spectrum watermarking of fingerprint and crypto code","authors":"Priyanka Priyadarshini, Kshiramani Naik","doi":"10.1007/s10470-025-02369-1","DOIUrl":"10.1007/s10470-025-02369-1","url":null,"abstract":"<div><p>The two-factor authentication (2FA) method provides an additional layer of security to the user accounts and systems beyond a single authentication factor like a simple password. Nowadays, biometric-based authentication is widely adopted as it reduces impersonation fraud and account takeover attacks. Biometric data are relevant to the user’s personal information and can potentially be exploited by the attacker to compromise the user’s additional data. Hence, the protection of the biometric data is also vital, along with the secure authentication of the protected data. This proposed work, a 2FA mechanism is implemented using the Spread Spectrum Watermarking method. Instead of storing fingerprint biometric data in the database, it is embedded in the physical token/security token as invisible watermarking with the user’s image. The user’s unique ID (UID) is stored in the database and embedded as an invisible watermark in the physical or security token, the second factor. This physical or security token, commonly known as a ‘smart card, ‘is a portable device that stores the user’s authentication information and can be used for secure access to systems and services. It becomes a smart card once authentication factors and other user information are embedded. The user’s fingerprint is compared to the embedded fingerprint on the smart card for identification to access protected data. To further validate the user’s identity, the embedded UID is decrypted and matched against the stored UID in the database. A detailed simulation analysis demonstrates the enhanced outcomes of the proposed watermarking-based 2FA model. A comparative study of the results confirms the superiority of the proposed model over traditional biometric-based 2FA systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143717051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low-noise wideband fixed IF subharmonic mixer at W-band

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-27 DOI: 10.1007/s10470-025-02388-y

Sadhana Kumari, Naveen Kumar Maurya, Gaurav Varshney

{"title":"Design of a low-noise wideband fixed IF subharmonic mixer at W-band","authors":"Sadhana Kumari, Naveen Kumar Maurya, Gaurav Varshney","doi":"10.1007/s10470-025-02388-y","DOIUrl":"10.1007/s10470-025-02388-y","url":null,"abstract":"<div><p>This paper provides an idea for designing a highly efficient, second-order broadband fixed-IF subharmonic mixer. Attention is paid to the step-by-step design process with detailed fabrication methods. With the purpose to improve the accuracy of simulation, the diode model is separated into the passive (linear) and the active (nonlinear) model. HFSS is utilized for the linear simulation of the mixer model while ADS is utilized for the non-linear simulation of the mixer. A tapered RF probe at the RF port is utilized to achieve wideband performance. The circuit of the presented mixer is printed on the 75 μm Quartz substrate and mounted in a waveguide block using split block technology. Measured results indicate an admissible conversion loss (better than 10.2 dB) over the RF bandwidth from 84 to 105 GHz. A moderate local oscillator power (9 dBm) is needed for this operation. The proposed mixer circuit is verified by test data. The measured port isolation between LO and RF is at least 36 dB. The least measured value of DSB noise temperature and conversion loss is 845 K and 7.2 dB, respectively at 85.2 GHz. The proposed Anti-parallel diode pair (APDP) based diode mixer shows better LO–RF isolation and conversion loss over other W-band mixers reported to date.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA implementation of hybrid Namib beetle and battle royale optimization algorithm fostered linear phase finite impulse response filter design

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-24 DOI: 10.1007/s10470-025-02385-1

P. Selvaprasanth, R. Karthick, P. Meenalochini, A. Manoj Prabaharan

{"title":"FPGA implementation of hybrid Namib beetle and battle royale optimization algorithm fostered linear phase finite impulse response filter design","authors":"P. Selvaprasanth, R. Karthick, P. Meenalochini, A. Manoj Prabaharan","doi":"10.1007/s10470-025-02385-1","DOIUrl":"10.1007/s10470-025-02385-1","url":null,"abstract":"<div><p>Nowadays, low complexity analysis is important for the better digital filter design. Although the linear phase finite impulse response (LPFIR) filter design requires less array complexity, existing methods are purely intended to attenuate both passband and stopband ripples. The main objective is to achieve a less complex design, which reduces deployment complexity and equipment cost. Therefore, in this manuscript, the FPGA Implementation of optimization-dependant LPFIR Filter design utilizing hybrid Namib beetle and battle royale optimization algorithm (HNBOA-LPFIR) is proposed. The proposed HNBOA-LPFIR filter design reduces waves of both pass bands and stop band. The transition bandwidth for deploying an LPFIR filter that follows the designated frequency reduces the sparsity. The superiority of filter design has the optimal outcome which conserves the exchange between the several specifications. The proposed HNBOA-LPFIR Filter design is simulated in Xilinx ISE14.7 (Virtex7) environment. The proposed HNBOA-LPFIR Filter methods are executed at FPGA and the efficiency of proposed HNBOA-LPFIR method is estimated with the help of performance metrics. The proposed HNBOA-LPFIR method provides 18.13%, 19.53%, 20.73% lower pass band ripples, 17.19%, 18.28%, 19.83% lower stop band ripple, 19.53%, 18.78%, 20.73% lower transition band when compared to the existing methods: Multi objective FIR filter design utilizing Salp swarm approach and its improved version (SSOA-FIR), Design and analysis of Linear Phase Finite Impulse Response filter utilizing Water Strider Optimization Approach at FPGA (WSOA-LPFIR), Optimal model of digital FIR filter based upon Grasshopper Optimization Approach (GHOA-DFIR) respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

QCA based programmable logic block for implementation of digital circuits in multilayer framework

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-24 DOI: 10.1007/s10470-025-02375-3

Rupali Singh, Pankaj Singh

{"title":"QCA based programmable logic block for implementation of digital circuits in multilayer framework","authors":"Rupali Singh, Pankaj Singh","doi":"10.1007/s10470-025-02375-3","DOIUrl":"10.1007/s10470-025-02375-3","url":null,"abstract":"<div><p>Quantum Dot Cellular Automata (QCA) is gathering attention from researchers in recent years due to its attractive features of low power, high density and high speed to serve as transistor-less paradigm for next generation circuits. Programmable or configurable architectures in QCA are needed to promote multifunctional capability of logic circuits along with ease of demonstration and fabrication. Moreover, multilayer approach in QCA adds the area efficacy and immunity against random interference. This paper presents the design of novel programmable logic block (PLB) in QCA configuration in multilayer framework which can be easily used to generate variety of digital circuits. The proposed QCA based PLB is further used to realize combinational circuit such as adder etc<i>.</i> and sequential circuits such as D flip flop, random access memory (RAM) element, shift registers etc<i>.</i> The circuits are further analyzed to obtain performance metrics. A comparative assessment has been carried out for the proposed PLB circuit to establish compatibility with the existing circuits. The proposed PLB sets path towards development of future generation complex and configurable computing systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel approximate Booth multipliers (ABm-eRx) based on efficient encoding and reduction for error-tolerant applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-24 DOI: 10.1007/s10470-025-02365-5

Jayasheela Moses, Sukanya Balasubramani, Umapathi Krishnamoorthy

{"title":"Novel approximate Booth multipliers (ABm-eRx) based on efficient encoding and reduction for error-tolerant applications","authors":"Jayasheela Moses, Sukanya Balasubramani, Umapathi Krishnamoorthy","doi":"10.1007/s10470-025-02365-5","DOIUrl":"10.1007/s10470-025-02365-5","url":null,"abstract":"<div><p>Energy efficient and performance optimised multiplier hardware is of high demand as they are the fundamental and most significant block in every signal processing and computing unit. In addition, they are the most power-hunger blocks too. Thus, in this article, two novel and efficient Booth encoded multiplier architectures are proposed utilising approximate computing techniques. Efficient optimisation with good accuracy is achieved by using a combination of approximate encoding and approximate partial product reduction. The multiplier architectures ABm-eR1 and ABm-eR2 are implemented in Xilinx. Results reveal that the multipliers ABm-eR1, ABm-eR2 consume 9% and 10% lesser area in terms of LUTs along with noticeable power and delay reduction when compared to exact Booth encoded architecture. Simulations depict a minimal error of 1.31 × 10<sup>–3</sup> NMED which is on-par with existing approximate multipliers. In addition, the multipliers ABm-eR1 and ABm-eR2 when evaluated across image multiplication, sharpening and smoothing produced a PSNR of 42.27 db, 41.19 db, 40.26 db and 40.61 db, 39.32 db, 39.05 db respectively. These results demonstrate that the proposed multiplier architectures perform on-par with the existing approximate Booth multipliers when used for image processing applications. Intrinsic to their efficient performance, the proposed architectures are good candidates for realising error-resilient applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a high-gain N-path filter with harmonic rejection

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-21 DOI: 10.1007/s10470-025-02374-4

Shuxiang Song, Changping Liu, Pinqun Jiang, Mingcan Cen

引用次数: 0

Very compact ultra-wideband slot antenna with integrated LTE band 非常紧凑的超宽带插槽天线，集成 LTE 频段

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-21 DOI: 10.1007/s10470-025-02382-4

Boualem Hammache, Idris Messaoudene, Abderraouf Messai, Arun Kesavan, Tayeb A. Denidni

引用次数: 0

Reducing impulsive noise in active noise control systems using FxLMS algorithm based on soft thresholding techniques

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-21 DOI: 10.1007/s10470-025-02380-6

V. Saravanan, N. Santhiyakumari, P. Shanmuga Sundaram

{"title":"Reducing impulsive noise in active noise control systems using FxLMS algorithm based on soft thresholding techniques","authors":"V. Saravanan, N. Santhiyakumari, P. Shanmuga Sundaram","doi":"10.1007/s10470-025-02380-6","DOIUrl":"10.1007/s10470-025-02380-6","url":null,"abstract":"<div><p>Impulsive noise significantly impacts signal quality and system performance, necessitating effective methods for its reduction. This paper introduces two adaptive filtering techniques based on the FxLMS algorithm, designed to address this challenge. The first method employs dynamic input thresholding, incorporating gradient-based and SNR-driven adjustments to suppress impulsive noise while retaining essential signal components. The second method builds on this by introducing hybrid thresholding applied to both input signals and filter coefficients, supported by double error smoothing to improve stability and adaptability under varying noise conditions. To evaluate the proposed methods, a comparative analysis is conducted with the Variable FxLMS Hybrid Thresholding (VFxLHT) technique, considering metrics such as steady-state noise suppression and computational efficiency. The results demonstrate that the proposed methods perform reliably across diverse noise conditions, maintaining signal fidelity while efficiently utilizing computational resources. These methods are intended as practical solutions for applications where impulsive noise control is essential to ensure reliable system operation without excessive computational complexity.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast and ultra-low energy subthreshold level shifter using split-gate buffer for low-power digital VLSI systems 利用分裂栅极缓冲器实现低功耗数字 VLSI 系统的快速和超低能耗阈下电平转换器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-21 DOI: 10.1007/s10470-025-02377-1

S. A. Sivakumar, B. Senthilkumar, Selvakumar Rajendran

{"title":"Fast and ultra-low energy subthreshold level shifter using split-gate buffer for low-power digital VLSI systems","authors":"S. A. Sivakumar, B. Senthilkumar, Selvakumar Rajendran","doi":"10.1007/s10470-025-02377-1","DOIUrl":"10.1007/s10470-025-02377-1","url":null,"abstract":"<div><p>Low-energy operation is predominant feature in the modern wireless sensor node and implantable biomedical applications. Scaling the supply voltage towards sub-/near-threshold level is vital design methodology to achieve energy-efficient operation. Voltage scaling can be adopted in the multiple supply voltage design incorporating interfacing circuit called voltage level shifters to attain power-efficient operation. This paper presents differential cascode voltage switch structure based high-speed and low-energy voltage level shifter for converting subthreshold voltage to nominal output voltage. The proposed level shifter (LS) utilizes NMOS/PMOS diode pairs along with the cross-coupled PMOS to address the current contention issue by suppressing the current from pull-up network while pull-down network is activated. The switching speed of the level conversion is enhanced by pass transistor and boosting devices in the pull-down network. Further, split-gate inverter/buffer at the output stage ensures high performance by alleviating static power and accelerating speed performance. The proposed LS is implemented in CMOS 180 nm technology on Cadence (Virtuoso) platform and analyzed using Spectre circuit simulator. The simulation results reveal the subthreshold level conversion from 220 mV to 1.8 V and wider frequency range of conversion. In addition, it ensures the delay of 8.57 ns, energy/transition of 39.4 fJ for level conversion from 0.4 to 1.8 V with input signal frequency of 1 MHz. Moreover, the LS consumes static power of 0.302 nW at standby mode.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0