Analog Integrated Circuits and Signal Processing最新文献

Resistorless memcapacitor emulator 无电阻记忆电容器仿真器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-06 DOI: 10.1007/s10470-026-02596-0

Pratik Kumar, Garima Shukla, Sajal K. Paul

引用次数: 0

Design and analysis of gate underlapped GOI junctionless FinFET in presence of temperature variations for RF IC design applications 射频集成电路设计中存在温度变化的栅极叠置GOI无结FinFET的设计和分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-06 DOI: 10.1007/s10470-026-02593-3

Arnab Som, Meenu Yadav, Sanjay Kumar Jana

{"title":"Design and analysis of gate underlapped GOI junctionless FinFET in presence of temperature variations for RF IC design applications","authors":"Arnab Som, Meenu Yadav, Sanjay Kumar Jana","doi":"10.1007/s10470-026-02593-3","DOIUrl":"10.1007/s10470-026-02593-3","url":null,"abstract":"<div><p>Recently junctionless transistors have gained popularity due to lower fabrication complexity than conventional physically doped transistors. In this work, we have presented gate underlapped GaAs on insulator (GOI) Junctionless(JL) FinFET considering 20nm channel length. The gate underlap engineering has been performed at both the source side and the drain side to improve key short channel effects like leakage current and sub-threshold swing. The DC performances of the proposed device are compared with the conventional Silicon-based SOI JL FinFET and the proposed device provides significant improvement in terms of <span>(text {I}_text {ON})</span>(76%), <span>(text {I}_text {OFF})</span>(3255 times), <span>(text {I}_text {ON})</span>/<span>(text {I}_text {OFF})</span>( 13895 times), and SS (5.80%) than the conventional Silicon-based SOI JL FinFET. The Analog/RF Figures of Merits such as Transconductance, Cut-off frequency, Gain-Bandwidth Product, Transit time, Transconductance Generation Factor, and Transconductance Frequency Product of the proposed device are studied considering the impact of temperature variations from 300K to 500K. Furthermore, several linearity parameters such as higher-order transconductances (<span>(text {g}_text {m2})</span>,<span>(text {g}_text {m3})</span>) and voltage intersection points (VIP2, VIP3) of the proposed device are evaluated for a wide range of temperature variations. In addition, the circuit-level performances are also investigated by designing the proposed device-based Current-Starved Voltage Controlled Oscillator (CS VCO) using the Cadence Virtuoso tool. The proposed FinFET-based CS VCO provides a wider tuning range of 99% which is 8% better than other recently published work. The proposed device-based CS VCO also provides a higher VCO gain of 9.91 GHz/V. Thus, the proposed device can be better suitable for Radio-Frequency circuit-level applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147829313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of high performance capacitorless 1T-DRAM with PDSOI-UTB FinFET 基于PDSOI-UTB FinFET的高性能无电容1T-DRAM设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-06 DOI: 10.1007/s10470-026-02588-0

Mitali Rathi, Guru Prasad Mishra

引用次数: 0

Binary wind driven optimization techniques for Metamaterial Cross Polarizer 二元风驱动的超材料交叉偏振器优化技术

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-05 DOI: 10.1007/s10470-026-02587-1

Chetan Barde, Prakash Ranjan, Neelesh Kumar Gupta, Arvind Choubey, Komal Roy

{"title":"Binary wind driven optimization techniques for Metamaterial Cross Polarizer","authors":"Chetan Barde, Prakash Ranjan, Neelesh Kumar Gupta, Arvind Choubey, Komal Roy","doi":"10.1007/s10470-026-02587-1","DOIUrl":"10.1007/s10470-026-02587-1","url":null,"abstract":"<div><p>This article presents synthesized Metamaterial Cross Polarizer (MCP) using Binary Wind Driven Optimization (BWDO) technique. BWDO is an advance version of WDO techniques. To achieve wideband response uttermost number of iterations is done at the time of synthesis. The wideband responses below − 10 dB is considered as a bandwidth and its ranges from 7.56 to 11.94 GHz. To achieve best response 50 number of iterations has to be performed. The Polarization Conversion Ratio (PCR) is considered at three distinct peaks i.e., at 8.3, 10.6 and 11.9 GHz with 99.87, 98.93 and 96.71% respectively. For explaining polarization conversion mechanism two different techniques is discussed in this article. The first technique is explained using the effective Electromagnetic (EM) parameters, i.e., <span>(:{varvec{epsilon:}}_{varvec{e}varvec{f}varvec{f}})</span> & <span>(:{varvec{mu:}}_{varvec{e}varvec{f}varvec{f}})</span>, whereas the second technique is explained using current distribution. The structure is mounted on dielectric substrate (FR-4). The mounted structure is tested and measured inside the anechoic chamber. The measured result obtained from the chamber are in close agreement with the simulated one which slightly differs due to fabrication tolerance. At last, the presented MCP structure is compared with the past articles and listed in the form of a table.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147829379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA-based implementation of the mechanization block 基于fpga实现的机械化块

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-02 DOI: 10.1007/s10470-026-02595-1

A. Aboutalebi, H. Alaeiyan, M. R. Mosavi

引用次数: 0

Power-aware test pattern generation with LP-LFSRs and counter-assisted gray code for VLSI BIST 基于lp - lfsr和反辅助灰色码的VLSI BIST功耗感知测试图生成

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-02 DOI: 10.1007/s10470-026-02586-2

C. Thangam, R. Manjith

{"title":"Power-aware test pattern generation with LP-LFSRs and counter-assisted gray code for VLSI BIST","authors":"C. Thangam, R. Manjith","doi":"10.1007/s10470-026-02586-2","DOIUrl":"10.1007/s10470-026-02586-2","url":null,"abstract":"<div>\u0000 \u0000 <p>In Very Large Scale Integrated Circuits, the Built in Self-Test (BIST) is intended to minimize power consumption while providing fault coverage. Weighted pseudorandom (W-Pr) BIST mechanism is employed to minimize the several vectors requirement for attaining entire fault coverage. The weights 0, 0.5 and 1 are included in the weight sets so far to create test patterns for reducing the duration of testing and amount of energy consumed. LP-LFSRs, or Low Power Linear Feedback Shift Registers, are used in this study for creating test patterns. A single input change (SIC) pattern is created when seeds from an LP-LFSR are Exclusive ORed with a Grey code (GC) generator and counter. The inclusion of accumulators, which are widely found in current VLSI chips, effectively lowers the amount of hardware needed for the production of BIST patterns when using this technique. Modelism 6.4c is used to validate the suggested technique and Verilog HDL is used to simulate it. The simulation results exhibit that the power consumed for testing utilizing the recommended architecture is significantly decreased.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147829691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High precision time-to-digital converter chip design based on cycle and average logic 基于周期和平均逻辑的高精度时数转换芯片设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-28 DOI: 10.1007/s10470-026-02589-z

Kaizhuo Chen, Zhiwei Huang, Chongzhuo Zhao, Chuanxin Teng, Ming Chen, Libo Yuan, Shijie Deng

{"title":"High precision time-to-digital converter chip design based on cycle and average logic","authors":"Kaizhuo Chen, Zhiwei Huang, Chongzhuo Zhao, Chuanxin Teng, Ming Chen, Libo Yuan, Shijie Deng","doi":"10.1007/s10470-026-02589-z","DOIUrl":"10.1007/s10470-026-02589-z","url":null,"abstract":"<div>\u0000 \u0000 <p>In this work, a three-stage Time-to-digital converter (TDC) based on the average measurement in the system is proposed for ranging. The ranging chip needs to provide 20 MHz reference clock signal externally, which is doubled to 1 GHz through the Phase-Locked Loop (PLL) circuit and sent to TDC to provide stable high frequency reference clock signal for the circuit. The circuit uses PLL cascaded oscillator units to generate multiple clock signals and vernier delay structures to construct two-stage interpolation. During the measurement process, the input signal is allocated to different channels of the TDC for multiple measurements and averaging. This not only reduces the random error caused by clock jitter due to noise, but also improves the utilization of TDC channels. The chip is based on X-Fab 0.18 μm CMOS process, the core TDC layout area is 500 μm × 350 μm, the power consumption is about 16.55 mW, and the resolution is 14 ps. Analysis of the results of the post-simulation shows that the differential nonlinear peak is less than 0.4 LSB, and the integral nonlinear peak is less than 0.6 LSB. The dynamic range can increase the number of high-segment counter bits according to the needs of actual application scenarios. High measurement accuracy, linearity and wide dynamic range are achieved.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analog circuit fault diagnosis based on feature attention 基于特征关注的模拟电路故障诊断

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-28 DOI: 10.1007/s10470-026-02590-6

Xianjun Du, Yan Yin, Lei Cao, Shengyi Cheng

引用次数: 0

Improving operational efficiency in photovoltaic systems with advanced fault monitoring solutions using machine learning algorithms 使用机器学习算法的先进故障监测解决方案提高光伏系统的运行效率

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-28 DOI: 10.1007/s10470-026-02597-z

N Vijayasarathi, Vijay Ravindran

{"title":"Improving operational efficiency in photovoltaic systems with advanced fault monitoring solutions using machine learning algorithms","authors":"N Vijayasarathi, Vijay Ravindran","doi":"10.1007/s10470-026-02597-z","DOIUrl":"10.1007/s10470-026-02597-z","url":null,"abstract":"<div><p>As photovoltaic (PV) systems become used widely, reliability and efficiency improvements are essential. Faults caused in the PV systems could produce energy losses up to 20% yearly. Fault detection is essential to diminish these losses and maintain the system efficiently. This work focuses on machine learning for reliable and accurate detection of faults in PV systems. The work proposes Gradient Boosted Decision Tree (GBDT) algorithms with ensemble method to identify arc faults, line to line faults and open circuit faults using real time data collected from voltage, current and irradiance sensors. GBDT integrates with ensemble methods to improve predictive performance and reliability. Both training and testing of this model were performed with the dataset. After trained, the framework is deployed on a web server for instantaneous fault condition monitoring. Also, the data for the algorithm was generated using MATLAB/Simulink simulations under different operating conditions to validate the datasets. Experimental results shown that the design achieving 100% accuracy during training and 98.54% accuracy during testing on randomly split datasets. If any fault occurs, the notification mail or Message will be sent to the user, provided the fault details through the server. These findings exhibit the framework potential to considerably improve the reliability and efficiency of PV systems in real world developments.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A comprehensive review and multi-parameter analysis of CMOS double-balanced Gilbert cell mixers across technology nodes from 180-22 nm 从180- 22nm跨技术节点的CMOS双平衡吉尔伯特电池混频器的综合回顾和多参数分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-24 DOI: 10.1007/s10470-026-02585-3

Richa Gupta, P. Hari Krishna Prasad

{"title":"A comprehensive review and multi-parameter analysis of CMOS double-balanced Gilbert cell mixers across technology nodes from 180-22 nm","authors":"Richa Gupta, P. Hari Krishna Prasad","doi":"10.1007/s10470-026-02585-3","DOIUrl":"10.1007/s10470-026-02585-3","url":null,"abstract":"<div><p>This review examines how the design philosophy of double-balanced CMOS Gilbert cell mixers changes as technologies scale, rather than assuming that scaling alone leads to uniform performance improvement. Reported mixer implementations spanning mature 180 nm CMOS to 22 nm fully depleted silicon-on-insulator (FD-SOI) technologies are analyzed to identify cross-technology trends in conversion gain, noise figure (NF), linearity, and power consumption that are not apparent from node-specific or technique-focused studies. The review shows that, in advanced CMOS nodes, reduced voltage headroom, parasitic-dominated behavior, device variability, and flicker noise place practical limits on conventional mixer architectures. As a result, many of the performance gains reported in scaled technologies arise from architectural adaptation and biasing strategy rather than from transistor scaling itself. Examples include modification or removal of the transconductance stage, the use of passive or hybrid mixing approaches, and systematic <span>(g_m/I_D)</span>-based device sizing. By linking circuit-level behavior with system-level considerations such as robustness, process–voltage–temperature (PVT) sensitivity, and system-on-chip (SoC) integration, this review explains why modern mixer designs often accept reduced standalone analog performance in favor of energy efficiency, predictability, and receiver-level optimization. The resulting synthesis provides RFIC designers and system architects with a technology-aware perspective for selecting and adapting Gilbert cell mixer architectures in deeply scaled CMOS technologies.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147738598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0