Analog Integrated Circuits and Signal Processing最新文献_第2页

Development of arithmetic optimized low-visibility image enhancement VLSI architecture with saturation-aware transmission map estimation 基于饱和感知传输图估计的算法优化低可见度图像增强VLSI架构的开发

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-15 DOI: 10.1007/s10470-025-02407-y

Koteswar Rao, Chandrasekhar Reddy, Giri Babu

{"title":"Development of arithmetic optimized low-visibility image enhancement VLSI architecture with saturation-aware transmission map estimation","authors":"Koteswar Rao, Chandrasekhar Reddy, Giri Babu","doi":"10.1007/s10470-025-02407-y","DOIUrl":"10.1007/s10470-025-02407-y","url":null,"abstract":"<div><p>Low light levels can cause a noticeable deterioration in the quality of photos. The visual quality of images and the execution of difficult visual tasks can both be effectively enhanced by resolving a number of low-light image degradation issues. One of the most difficult aspects of low-light enhancement is finding a balance between the three main aspects of image improvement: color integrity, detail presentation, and light intensity. The multi-distribution of spatial domain illumination characteristics in natural scenes complicates the balancing process and affects the effectiveness of such real-time systems. To address these issues, a real-time hardware simulation of an image improvement system is essential. Thus, the VLSI-based pixel-wise saturation-aware transmission map estimation unit is created in this study to eliminate halo artifacts and artefacts around depth discontinuities from the input low-quality images. Prior to that, the Arithmetic Optimized Atmospheric Light Estimation Unit module applies a 15 × 15 minimum filter to determine the atmospheric light by down sampling the input low-light image. In the end, an image restoration unit is created to transform low-visibility images into high-visibility ones. Furthermore, in each step of the proposed architecture, the optimized tree structured magnitude comparator, a reconfigurable unified adder and subtractor unit, and a Divide-and-Conquer based LUT oriented booth multiplier architectures are developed to replace the complexities while maintaining the image quality. At last, the VLSI architectures of the proposed low-visibility enhancement system are implemented in FPGA using Xilinx Verilog coding. The result analysis displayed that the proposed method consumes 0.254W power as well as 0.575 ns delay to complete the whole process, which is considerably lower than the existing methods.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144074087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis on sensitivity enhancement of MEMS based capacitive pressure sensor for low pressure healthcare monitoring

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-13 DOI: 10.1007/s10470-025-02411-2

Kavitha Jagabathuni, Swapna Peravali

引用次数: 0

Advances in nanomaterial-based sensors: a study of carbon nanotubes, quantum dots, nanorods, nanowires, and nanopillars in emerging applications 纳米材料传感器的进展：碳纳米管、量子点、纳米棒、纳米线和纳米柱在新兴应用中的研究

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-12 DOI: 10.1007/s10470-025-02417-w

Sneha Bherade, Aaditya Bhalerao, Prajwala Khapale, Vilas Jagatap

{"title":"Advances in nanomaterial-based sensors: a study of carbon nanotubes, quantum dots, nanorods, nanowires, and nanopillars in emerging applications","authors":"Sneha Bherade, Aaditya Bhalerao, Prajwala Khapale, Vilas Jagatap","doi":"10.1007/s10470-025-02417-w","DOIUrl":"10.1007/s10470-025-02417-w","url":null,"abstract":"<div><p>Nanomaterials constitute a vital component of modern technological advancements and have attracted a great deal of attention. These advanced materials are now utilized in a broad spectrum of applications across various sectors, making substantial contributions to numerous aspects of our lives. Numerous sensors specifically engineered using them demonstrate their versatility and value in technological advancements. They find applications across a range of sensor types, including optical, chemical, biological, physical, thermal, and digital sensors. These sensors generate electrical signals to detect and measure physical phenomena. They also convert biological reactions into electrical impulses in response to physical inputs, enabling the detection and monitoring of a wide range of conditions and processes. This article focuses on nanomaterial-based sensors, covering their development and applications in diverse sectors. They find their applications in identifying adulterants in food, impurities in medicine, and early diagnosis of illnesses.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143938640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 6 bit and 500 MS/s hybrid ADC with energy efficient CDAC switching scheme 一个6位和500 MS/s的混合ADC，具有节能的CDAC开关方案

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-10 DOI: 10.1007/s10470-025-02408-x

Dinesh Kumar Balasubramanian, Navneet Gupta, Amara Amara, Hitesh Shrimali

{"title":"A 6 bit and 500 MS/s hybrid ADC with energy efficient CDAC switching scheme","authors":"Dinesh Kumar Balasubramanian, Navneet Gupta, Amara Amara, Hitesh Shrimali","doi":"10.1007/s10470-025-02408-x","DOIUrl":"10.1007/s10470-025-02408-x","url":null,"abstract":"<div><p>We propose a 6-bit hybrid flash-successive approximation (SAR) analog-to-digital converter (ADC) with a switched capacitor digital-to-analog converter (CDAC). Compared to a conventional switching scheme, the dynamic switching energy of the proposed switching scheme is reduced by <span>(69%)</span> for an m-bit/cycle ADC. The total area of the proposed CDAC is reduced by 87.5 and <span>(50.5%)</span>, when compared with the conventional binary weighted CDAC and the split capacitor CDAC, respectively. An inverter-based comparator with a common-mode-feedback (CMFB) is used to reduce the power consumption (<span>(hbox {P}_{text {avg}})</span>) of the proposed design. The conversion time of the 6-bit ADC is reduced to 3 cycles by using a 3-bit/cycle architecture. The ADC is fabricated in a standard 130 nm CMOS technology with a sampling rate of 500 MS/s. Measured peak signal-to-noise distortion ratio (SNDR) is 31.36 dB with 2.96 mW average power consumption. Achieved effective-number-of-bits (ENOB) and Walden’s figure-of-merit (FOM) are 4.92 and 195 fJ/conversion-step, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143932298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of novel sense amplifier for bio-medical applications 新型生物医学传感器放大器的设计与分析

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-10 DOI: 10.1007/s10470-025-02409-w

Pavankumar Bikki

{"title":"Design and analysis of novel sense amplifier for bio-medical applications","authors":"Pavankumar Bikki","doi":"10.1007/s10470-025-02409-w","DOIUrl":"10.1007/s10470-025-02409-w","url":null,"abstract":"<div><p>This paper presents the realization of a novel sense amplifier for biomedical applications, with a primary focus on its application in cardiac pacemakers. The researchers focus on low-power biomedical devices, achieving this by advanced active devices like the Differential Voltage Current Conveyor (DVCC). In a pacemaker, both sensing and pacing functions are crucial. The sense amplifier consists of an instrumentation amplifier, a bandpass filter, and a comparator, enabling it to recognize the PQRST complex in the cardiac cycle. We introduce a novel model for the sense amplifier, employing a DVCC, and conduct analyses using the TSMC 130 nm technology. The gain of the current-mode instrumentation amplifier is 56.3, and the CMRR is 60.7. Moreover, the proposed design analysis addresses power dissipation, temperature, and noise. Furthermore, experiments performed with the analog IC AD844 have demonstrated the efficiency of the proposed sense amplifier design. Additionally, we analyzed the electrocardiogram (ECG) signal by identifying its patterns. We have used the Fast Fourier transform (FFT) to determine the power spectrum and frequency response of the signal. Studies that looked at signal analysis in the literature used radix-2, SRFFT, and other algorithms. These can save up to 5.066% of power compared to using an FFT ASIC. Hence, we proposed a modified radix-2 approach for the low power spectrum of an ECG cycle. The Radix-2 customized method drastically reduces the number of computations, resulting in a low power consumption of 3.339 mW, and a leakage power of 1.272 mW. Furthermore, it would promote real-time adaptability and increase accuracy in pattern recognition for ECG signals. The results demonstrate that the new sense amplifier model achieves substantial gain and a CMRR, making it more efficient than previous versions.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143932258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-speed and area efficient low-power dynamic parity generator and parity checker 高速高效的低功耗动态奇偶校验器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-06 DOI: 10.1007/s10470-025-02394-0

Preeti Verma, Ajay K. Sharma, Vinay Shankar Pandey, Dhandapani Vaithiyanathan

{"title":"High-speed and area efficient low-power dynamic parity generator and parity checker","authors":"Preeti Verma, Ajay K. Sharma, Vinay Shankar Pandey, Dhandapani Vaithiyanathan","doi":"10.1007/s10470-025-02394-0","DOIUrl":"10.1007/s10470-025-02394-0","url":null,"abstract":"<div><p>The strategic detection of errors using a parity generator and checker is essential, compelling design engineers to refine and enhance system performance. Even in advanced modern communication systems, errors can still arise due to signal loss and noise, making robust error detection indispensable. This paper brings to light the design of the superior high-speed, low-power 3-bit dynamic parity generator and checker. Two, four, eight, and sixteen-bit XOR gates have been implemented using previous and proposed techniques. The proposed true single-phase dynamic XOR gate builds the parity checker and generator circuits. The proposed dynamic XOR gate, designed 3-bit parity generator, and checker circuits are compared with recently reported techniques. All circuits have been simulated using Cadence Specter on 90 nm technology parameters and tested up to 1 GHz of clock frequency. Comparison is made to showcase the superiority of the proposed design in terms of power consumption, propagation delay, PDP (93.8%), EDP (98.8%), number of transistors, the figure of merit, and unity noise gain. This new 3-bit dynamic parity generator and checker would add a colossal perspective for a design engineer.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multiscroll chaotic attractors and multistability in a ring of three coupled inertial Hopfield neurons: theoretical analysis and circuit simulation 三个耦合惯性Hopfield神经元环中的多涡旋混沌吸引子和多稳定性：理论分析和电路仿真

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-05 DOI: 10.1007/s10470-025-02397-x

Jean Baptiste Koinfo, Jacques Kengne, Jean Chamberlain Chedjou

引用次数: 0

A double single-ended resonant inverter for low harmonic line frequency applications 双单端谐振逆变器低谐波线路频率的应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-05 DOI: 10.1007/s10470-025-02415-y

Jafar M. Daoud

引用次数: 0

Hybrid-SWO-QIRSA: a novel optimization approach for VLSI circuit design with improved wirelength reduction and floor planning Hybrid-SWO-QIRSA：一种新颖的VLSI电路设计优化方法，具有改进的布线减少和地板规划

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-05 DOI: 10.1007/s10470-025-02400-5

M. Prema, K. R. Kavitha

{"title":"Hybrid-SWO-QIRSA: a novel optimization approach for VLSI circuit design with improved wirelength reduction and floor planning","authors":"M. Prema, K. R. Kavitha","doi":"10.1007/s10470-025-02400-5","DOIUrl":"10.1007/s10470-025-02400-5","url":null,"abstract":"<div><p>Wire length reduction, floor planning, and partitioning have become more difficult as a result of the VLSI circuit design industry's explosive expansion. The growing system complexity, dead space, and connection delays present important design challenges. This study presents a new hybrid optimization technique called Quantum-Inspired Reptile Search technique (QIRSA) and Hybrid Spider Wasp Optimization (SWO) to tackle these issues. The primary objective is to reduce latency, area, wire length, and power consumption by optimizing VLSI circuit partitioning and floor planning. While QIRSA shortens wire length to increase overall efficiency, the SWO component concentrates on improving floor planning and partitioning. Simulations using MCNC benchmark circuits, such as S1196, S1238, S3350, and S8378, are used to validate the suggested approach. The findings show that Hybrid-SWO-QIRSA consistently performs better than other optimization algorithms that are currently in use, including LOA-OPFP, BIOA-OPFP, SBO-OPFP, and MFOA-OPFP. More affordable and power-efficient VLSI designs are the result of the hybrid approach's successful reduction of dead space, floor plan area, and routing wire lengths. Important variables like area, latency, power consumption, and wire length demonstrate notable gains in the performance comparison. Hybrid-SWO-QIRSA is proven to be an effective optimization technique for VLSI circuit design by this research.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143908757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An optimized LNA utilizing MGA for high performance 24 GHz radar applications 利用MGA优化的LNA，适用于高性能24 GHz雷达应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-05 DOI: 10.1007/s10470-025-02396-y

Unal Aras, Tahesin Samira Delwar, Murod Khurbanov, Yangwon Lee, Jee Youl Ryu

{"title":"An optimized LNA utilizing MGA for high performance 24 GHz radar applications","authors":"Unal Aras, Tahesin Samira Delwar, Murod Khurbanov, Yangwon Lee, Jee Youl Ryu","doi":"10.1007/s10470-025-02396-y","DOIUrl":"10.1007/s10470-025-02396-y","url":null,"abstract":"<div><p>In this paper, a novel 24 GHz low noise amplifier (LNA) is presented which is optimized using a modified genetic algorithm (MGA). A cascade topology and a noise canceling common source circuit are employed in the proposed LNA. To improve reverse isolation and increase power gain, the cascade structure is employed. Besides being in practice on other notes, simple genetic algorithms (SGAs) have difficulty exploring the extensive search space due to the high dimensionality of LNA circuit parameters, such as resistor and capacitor values. Also, SGA is challenging to escape local optima and arrive at the global optimal due to the fitness landscape’s nonlinearity and multimodality. To mitigate those issues, the MGA is proposed to optimize the LNA circuit efficiently. In optimizing LNA, a MGA is advantageous since it can efficiently explore a large design space and identify optimal solutions. Also, the proposed MGA reduces randomness in offspring generation. At 24 GHz, the measurement results show that optimized LNA achieves a gain of 13.8 dB and a noise figure of 3.8 dB. The IP<sub>1</sub>dB of the optimized LNA circuit is –9 dB. We have achieved a S<sub>11</sub> of –12 dB and a S<sub>22</sub> of –11 dB by matching the input and output impedances.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143908754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0