Analog Integrated Circuits and Signal Processing最新文献_第2页

A low-noise high-gain broadband inductor-less inverter-based transimpedance amplifier in 22-nm FDSOI CMOS process 基于22nm FDSOI CMOS工艺的低噪声高增益宽带无电感逆变器跨阻放大器

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-24 DOI: 10.1007/s10470-026-02668-1

Sareh Bavandi, Kamran Entesari

引用次数: 0

Multi-rate LMS-based digital calibration for a 12-bit SAR ADC 基于多速率lms的12位SAR ADC数字校准

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-24 DOI: 10.1007/s10470-026-02657-4

Wei Liu, Qiteng Zhang, Shiguang Shang

{"title":"Multi-rate LMS-based digital calibration for a 12-bit SAR ADC","authors":"Wei Liu, Qiteng Zhang, Shiguang Shang","doi":"10.1007/s10470-026-02657-4","DOIUrl":"10.1007/s10470-026-02657-4","url":null,"abstract":"<div><p>To address conversion-accuracy degradation in successive approximation register analog-to-digital converters (SAR-ADCs) caused by capacitor mismatch, this paper presents a 12-bit SAR-ADC design flow based on a multi-rate least mean square (MR-LMS) digital calibration algorithm. A sub-binary segmented capacitor array is adopted, weight errors are extracted through dither-assisted code comparison, and capacitor weights are iteratively updated by LMS. To reduce digital calibration power, the calibration engine is partitioned into a high-speed sampling domain and a low-speed weight-update domain. In addition, a radiation-aware output protection architecture combining two-stage operation, three-channel redundancy, and median voting is proposed at the functional level to suppress transient output outliers caused by single-event disturbances. The SAR-ADC core circuit and layout are implemented in a TSMC 0.35-μm CMOS process, while the calibration logic is realized and co-verified in Verilog HDL. MATLAB/Simulink system-level simulation improves the ENOB from 7.03 bits to 11.55 bits, and FPGA co-simulation with the fabricated SAR-ADC core achieves 11.24-bit ENOB after off-chip foreground calibration. Compared with the conventional LMS implementation, the MR-LMS scheme reduces the estimated dynamic power of the FPGA-based calibration logic by 62.6% and the estimated total FPGA calibration-logic power by 19.7%. These results support the feasibility of low-power digital calibration for medium-speed high-resolution SAR-ADCs, while the radiation-tolerant architecture remains a functional-level design strategy that requires future hardware validation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149035333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A survey on circuit innovations in operational amplifiers 运算放大器电路创新综述

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-23 DOI: 10.1007/s10470-026-02644-9

Aya M. Shaaban, Sherif M. Sharroush, Yasser Abdalla, Ahmed Lutfi Awad Elgreatly

引用次数: 0

MaIC-Net: Learnale weight scabling and complexity scalable deep neural network for massive mimo detection MaIC-Net：用于大规模mimo检测的学习权值和复杂度可扩展深度神经网络

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-19 DOI: 10.1007/s10470-026-02666-3

R. Anil Kumar, Sarala Patchala, R. Prakash Kumar, Ummiti Sreenivasulu, Shaik Fairooz

{"title":"MaIC-Net: Learnale weight scabling and complexity scalable deep neural network for massive mimo detection","authors":"R. Anil Kumar, Sarala Patchala, R. Prakash Kumar, Ummiti Sreenivasulu, Shaik Fairooz","doi":"10.1007/s10470-026-02666-3","DOIUrl":"10.1007/s10470-026-02666-3","url":null,"abstract":"<div><p>Massive multiple-input multiple-output (MIMO) is a crucial method for next-generation communication systems that must satisfy user performance as well as quality of service (QoS) standards. A vast MIMO uplink receiver’s symbol analyzers became increasingly complicated as the number of antennas and radio frequency (RF) chains increased. Thus, research into the ideal massive MIMO detection method with high efficiency as well as minimal complexity has garnered a lot of attention through the last decade. Therefore, this paper presents a Multiuser Accelerated Interference Cancellation Network (MaIC-Net) to perform massive MIMO detection in the uplink communication system. In addition, a monotonic non-increasing profile function is designed to scale each layer presented in the MaIC-Net, allowing the proposed MaIC-Net model to dynamically learn the attenuation function. In addition, the sparsity-inducing regularization requirement is combined with accessible weight scaling methods to decrease model size and computational complexity. Similarly, the SoftS activation function is intended to enhance detection results by higher-order modulation. The Matlab tool is used to execute the proposed model and evaluate the performance of the proposed mode using various performance parameters. The result analysis reveals that the proposed method outperforms existing methods by achieving 0.000319 less symbol error rate (SER) against 8dB Signal-to-Noise-Ratio (SNR) for the 64-Quadrature Amplitude Modulation (QAM) modulation technique.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148986765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A compact design of R-LWE crypto processor using customizable parallel polynomial multiplication on FPGA 在FPGA上采用可定制并行多项式乘法的R-LWE加密处理器的紧凑设计

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-17 DOI: 10.1007/s10470-026-02661-8

B. Nithyasundari, R. Vinodhini

{"title":"A compact design of R-LWE crypto processor using customizable parallel polynomial multiplication on FPGA","authors":"B. Nithyasundari, R. Vinodhini","doi":"10.1007/s10470-026-02661-8","DOIUrl":"10.1007/s10470-026-02661-8","url":null,"abstract":"<div><p>Polynomial multiplications are time-consuming because the encryption approach uses high-degree polynomial rings. One major limitation of RLWE-based encryption is polynomial multiplication over rings. A polynomial multiplier and a discrete Gaussian sampler are two essential parts of the R-LWE hardware implementation. By employing a Streamlined Tree Gaussian sampling-based Cumulative Distribution Table (STGS-CDT), the proposed R-LWE crypto-processor will eliminate large comparators and complex comparison procedures. The hardware design of discrete Gaussian sampling is more efficient than most previous designs; it has a constant execution time and can accommodate various sampling principles. The customized parallel school book polynomial multiplication-CP-SPM is designed to compute polynomial multiplication. Scalable parallelism in architecture aims to improve both time and area efficiency. The design minimizes the bit-lengths of intermediate values by directly applying modular reduction to partial products. The proposed architecture is implemented in the Xilinx platform using the Virtex 7 FPGA series. The proposed design consumes less area with frequency and delay of 935.4 MHz and 2.34 ms, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148986586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Speech disfluency recognition using convolutional neural networks (CNNs) 基于卷积神经网络的语音不流畅识别

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-17 DOI: 10.1007/s10470-026-02659-2

Moshera Mohammed, Ahmed Galal, Yehia Sayed, Reda Gharieb

引用次数: 0

A structurally fortified tetramorphic mixed MWCNT bundle-based through-silicon vias for signal integrity analysis 一种用于信号完整性分析的结构强化的四晶混合纳米碳管束通硅通孔

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-16 DOI: 10.1007/s10470-026-02656-5

Gaurav Mitra, Sangeeta Kamboj, Mayank Kumar Rai

引用次数: 0

A comparative logic-style framework for 8-Bit 12-function efficient ALU design using transmission gate and NMOS pass transistor logic in 90-nm CMOS 采用传输门和NMOS通管逻辑在90纳米CMOS中设计8位12功能高效ALU的比较逻辑风格框架

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-16 DOI: 10.1007/s10470-026-02664-5

Saquib Farhan, Sadman Rahman, Sunjida Sultana, Md Tawfiq Amin, Gourab Datta

{"title":"A comparative logic-style framework for 8-Bit 12-function efficient ALU design using transmission gate and NMOS pass transistor logic in 90-nm CMOS","authors":"Saquib Farhan, Sadman Rahman, Sunjida Sultana, Md Tawfiq Amin, Gourab Datta","doi":"10.1007/s10470-026-02664-5","DOIUrl":"10.1007/s10470-026-02664-5","url":null,"abstract":"<div><p>Energy-efficient and high-speed arithmetic units are fundamental building blocks in resource-constrained systems, including Internet of Things (IoT) devices and embedded processors. This requirement necessitates the development of Arithmetic Logic Units (ALUs) optimized in terms of power consumption, silicon area, and performance in advanced nanoscale technologies. In this work, the design and comparative analysis of two 8-bit, 12-function ALUs implemented using Transmission Gate (TG) logic and NMOS Pass Transistor Logic (N-Pass) are presented using Cadence Virtuoso with GPDK 90 nm technology. The proposed architectures support a wide range of operations, such as addition, subtraction, multiplication, bitwise shifting, and parity generation. The performance is evaluated based on critical parameters, including propagation delay, power consumption, operating frequency, and transistor count. Simulation results at a supply voltage of 1.8 V indicate that the TG-based ALU achieves superior speed performance, exhibiting a propagation delay of 0.1655 ns and an operating frequency of 58.9 MHz, making it suitable for high-performance computing applications such as microprocessors. Conversely, the N-Pass-based ALU demonstrates improved power efficiency, with an average power consumption of 0.19275 W and power dissipation of 1.67 mW, which are favorable for low-power IoT applications. The comparative analysis highlights the inherent design trade-offs, revealing a 99.76% reduction in delay for the TG implementation and a 98.36% reduction in power dissipation for the N-Pass design, thereby providing valuable insights for selecting appropriate logic styles in application-specific integrated circuit design.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148986576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Metamaterial inspired hybrid polarization frequency reconfigurable patch antenna with H –shaped slots for 5G applications 5G应用的H型槽超材料混合极化频率可重构贴片天线

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-15 DOI: 10.1007/s10470-026-02651-w

Jhanani Shree U, Sathish M

{"title":"Metamaterial inspired hybrid polarization frequency reconfigurable patch antenna with H –shaped slots for 5G applications","authors":"Jhanani Shree U, Sathish M","doi":"10.1007/s10470-026-02651-w","DOIUrl":"10.1007/s10470-026-02651-w","url":null,"abstract":"<div><p>The fifth generation (5G) of telecommunication technology is developing quickly, as evidenced by continuous research and application around the world. However, patch antenna technology has been growing effectively in the field of 5G applications. The Reconfigurable patch antenna adapts dynamically to changing communication needs and environmental situations by altering its radiation pattern, polarization, and frequency characteristics. The traditional reconfigurable monopole antenna based multi-stage metamaterial in 5G application exhibits some limitations like high radiation loss and poor impedance matching. To overcome these issues, in this study designed a novel polarization and reconfigurable based frequency antenna for 5G application. In the proposed reconfigurable patch antenna, the overall dimension of the substrate is <span>(35text{m}text{m}times 35text{m}text{m})</span>, with a dielectric constant of 4.4 and a thickness of 1.6 mm. The present antenna model has been operating at a frequency range of 50 GHz to 80 GHz. The polarization reconfigurability of the antenna has been attained by adding an H shaped slot to the antenna patch, and truncated corners are made in the patch to attain Linear Polarization, which is switched to horizontal and vertical by use of PIN diodes. Similarly, the PIN diode is added to the diamond slit to attain frequency reconfigurability, which is resonated on two different frequencies of 59.86 GHz and 71.93 GHz for ON and OFF condition; at the same time polarization also reconfigurable. Moreover, the proposed antenna is designed with Epsilon-negative (ENG) metamaterial, and a Microstrip feedline is added to the bottom of the patch. Based on performance analysis, the proposed antenna obtains a gain value at the ON condition of 3.6 dB and OFF condition of 8.4 dB, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148986437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reconfiguring FINFET SRAM for next-generation AI robotics: a review 面向下一代人工智能机器人的FINFET SRAM重构研究综述

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-12 DOI: 10.1007/s10470-026-02641-y

Tamilarasi Raja

{"title":"Reconfiguring FINFET SRAM for next-generation AI robotics: a review","authors":"Tamilarasi Raja","doi":"10.1007/s10470-026-02641-y","DOIUrl":"10.1007/s10470-026-02641-y","url":null,"abstract":"<div><p>In recent decades, most embedded systems have incorporated microprocessors paired with volatile cache memory, predominantly based on Static Random-Access Memory (SRAM) technology. Globally, SRAM has become indispensable, receiving significant attention due to its critical impact on system performance. Approximately 75% of on-chip memory in System-on-Chip (SoC) designs utilizes SRAM, with the remaining 25% supporting arithmetic and control operations. As artificial intelligence (AI)-driven electronics and robotic applications continue to evolve, there is an increasing demand for high-speed, energy-efficient, and reliable memory architectures to meet real-time computational needs. To address these challenges, advanced transistor technologies are being explored, with FinFET-based 3D structures emerging as a promising solution. FinFETs offer better immunity to short-channel effects, improved electrostatic control, and reduced leakage current, making them well-suited for high-density and low-power SRAM integration. Additionally, various SRAM cell topologies, including 6T, 7T, 8T, 9T, 10T, and 11T designs, have been proposed to optimize trade-offs between performance, stability, power efficiency, and area. While the 6T cell remains a standard for high-speed caches, extended topologies such as 8T, 9T, 10T, and 11T provide improved read stability and soft-error resilience, which are essential for modern AI and robotic systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148927605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0