Analog Integrated Circuits and Signal Processing最新文献

{"title":"A low power frequency-programmable stimulation circuit for small rodent pacemaker","authors":"Fanny Pan,&nbsp;Émilie Avignon-Meseldzija,&nbsp;AlBaraa Elhabab,&nbsp;Alban Todesco,&nbsp;Olaf Mercier,&nbsp;Delphine Mika,&nbsp;David Boulate,&nbsp;Frédéric Perros,&nbsp;Anthony Kolar","doi":"10.1007/s10470-024-02282-z","DOIUrl":"10.1007/s10470-024-02282-z","url":null,"abstract":"<div><p>This article presents the design of an integrated, frequency-programmable stimulation circuit dedicated to small rodents for the study of pulmonary arterial hypertension. A complete architecture of the stimulation circuit is proposed, based on in vivo tests that have led to the stimulation waveform specification. The circuit is designed using XFAB 0.18 µm technology. The adopted design methodology allows to reduce the power consumption of command blocks to the minimum. Post-layout simulation results shows that the pacing rate can be tuned from 450 to 600 beats per minute (bpm). The total power consumption of the stimulation circuit is 196.1 µW, with 186 µW directly consumed by the voltage multipliers, H-Bridge and pacemaker load, 10.1 µW by the kilohertz-range VCO driver, and only 8.4 nW by the ultra-low power command generator.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"125 - 139"},"PeriodicalIF":1.2,"publicationDate":"2024-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and simulation of a low-power, universal & multi-mode filter for the commercial FM band in 20-nm CNFETs","authors":"S. Mohammadali Zanjani,&nbsp;Pouya Toghian","doi":"10.1007/s10470-024-02287-8","DOIUrl":"10.1007/s10470-024-02287-8","url":null,"abstract":"<div><p>This paper presents a new biquad filter based on carbon nanotube field-effect transistor (CNFET) technology. Implementing various filter modes (high-pass, low-pass, band-pass, and band-stop) in four operating modes (voltage, current, transconductance, and transresistance) with a unified circuit structure is the fundamental feature of the proposed filter. The proposed universal filter is intended for commercial radio communications in the FM band to reduce power consumption and chip area occupation. The proposed circuit can adjust a wide frequency range and thus cover multiple radio channels with minimum noise and distortion on the signal. The proposed filter in 20 nm technology has been simulated using advanced design system (ADS) software to investigate the effects of high-frequency effects. The minimum power consumption is 360 nW, with a supply voltage of 0.9 V, with the ability to independently adjust the center frequency (22 MHz &lt; f₀ &lt; 120 MHz) and filter quality factor (0.6 &lt; Q &lt; 23) and the use of grounded capacitors to absorb parasitic effects are among the advantages of the proposed circuit. The proposed Gm-C circuit has the highest figure of merit (FOM) value of 318.5. Moreover, its resistance to process variations, power supply, and temperature changes demonstrates the appropriate performance of the proposed filter.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"9 - 20"},"PeriodicalIF":1.2,"publicationDate":"2024-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of novel full-wave rectifier using second generation current conveyor (CCII)","authors":"Amit Agrawal,&nbsp;Amit Rai,&nbsp;Kulwant Singh,&nbsp;Ankita Bhatt,&nbsp;Ashish Shrivastava,&nbsp;Shubham Tiwari,&nbsp;Bidyut Mahato","doi":"10.1007/s10470-024-02279-8","DOIUrl":"10.1007/s10470-024-02279-8","url":null,"abstract":"<div><p>This paper presents a unique full-wave rectifier designed with the help of second generation current conveyor (CCII) which is a promising building block to design the analog circuits. The proposed circuit is designed &amp; simulated on OrCAD/PSpice using key ICAD844 as CCII, manufactured by Analog Devices corporation. The simulated results are extracted using EDA tool for the input of different frequencies till 1 MHz. The excellent output waveforms verify the proposed circuit with the characteristics of full-wave rectifier. The hardware prototype is implemented &amp; tested on printed circuit board using laboratory setup to validate the proposed concept. The resultant output signal is undistorted, fully rectified and maintained with sinusoidal shape for the input signal having frequency of 1.022 MHz. The metal oxide semiconductor structure with the small signal analysis of proposed circuit is also discussed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"21 - 30"},"PeriodicalIF":1.2,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A multiplier-less meminductor emulator with experimental results and neuromorphic application","authors":"B. Suresha,&nbsp;Chandra Shankar,&nbsp;S. B. Rudraswamy","doi":"10.1007/s10470-024-02286-9","DOIUrl":"10.1007/s10470-024-02286-9","url":null,"abstract":"<div><p>This research article presents a meminductor emulator without multiplier using double output second generation current conveyor (DO-CCII) and operational trans-conductance amplifiers (OTA) and minimum numbers of passive elements. The mathematical expression of meminductor is obtained and verified through various simulation i.e., hysteresis analysis, non-volatile analysis and process corner analysis. Also, presented post-layout simulation of silicon components (DO-CCII and OTA). Application of meminductor emulator as Amoeba behaviour is also incorporated in the Neuromorphic circuit. Furthermore, an experimental setup was also build using the off the shelf ICs AD844AN (for DO-CCII) and CA3080EZ (for OTA) to examine the experimental results. The proposed meminductor emulator is simulated in Cadence Virtuoso tool using standard CMOS 90 nm technology.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"109 - 123"},"PeriodicalIF":1.2,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Active block EX-CCII based electrical circuit for practical impedance data of OSCC","authors":"Bidhanshel Singh Athokpam,&nbsp;Ashish Ranjan,&nbsp;Sumita Banerjee,&nbsp;Vivek Bhatt,&nbsp;Mamata Maisnam,&nbsp;Saikat Mukherjee","doi":"10.1007/s10470-024-02273-0","DOIUrl":"10.1007/s10470-024-02273-0","url":null,"abstract":"<div><p>Oral Squamous Cell Carcinoma (OSCC) is the most common oral cancer, and its behavior can be analyzed using bio-impedance. A single dispersion Cole model is designed using active block Extra X Current Conveyor (EX-CCII), which generates the existing practical oral OSCC bio-impedance data. An experimental result of cancer bio-impedance in the 20 Hz to 5 MHz range is well modeled with an active block EX-CCII resistors (R <span>(_{infty })</span> and R₁) and fractional capacitor (C_α). The proposed design can serve as a step forward for designing a purposeful method for analyzing the behavior of oral cancer impedance without any practical data. The functionality of the proposed electrical circuit for OSCC is well verified through PSPICE simulation using both 0.25 μm CMOS TSMC Technology parameters and the macro model of EX-CCII. Simulation results agree well with experimental bio-impedance data.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"31 - 38"},"PeriodicalIF":1.2,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141522599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An offset calibration scheme for on-chip thermal profiling with differential temperature sensors","authors":"Mengting Yan,&nbsp;Marvin Onabajo","doi":"10.1007/s10470-024-02285-w","DOIUrl":"10.1007/s10470-024-02285-w","url":null,"abstract":"<div><p>This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage offset due to device mismatches and on-chip temperature gradients. The calibration circuits were designed in a standard 65 nm CMOS process for simulation. Results indicate that an input-referred offset with a mean of 0.2 μV can be achieved after calibration, through which the standard deviation is greatly reduced from <i>σ</i> = 880.3 to <i>σ</i> = 5086 μV. Furthermore, the proposed analog offset calibration scheme has negligible impact on the sensitivity of the complete temperature sensor circuit, as shown by Monte Carlo and process-temperature corner simulation results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"83 - 91"},"PeriodicalIF":1.2,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02285-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141522598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low voltage high performance CNTFET-based VDIBA and universal filter application","authors":"Şeyda Sunca Ulusoy,&nbsp;Mustafa Alçı","doi":"10.1007/s10470-024-02283-y","DOIUrl":"10.1007/s10470-024-02283-y","url":null,"abstract":"<div><p>With the reduction of CMOS technology to nanometric dimensions, it is thought that the end of atomic limits in integrated circuit applications is almost approached and some problems are encountered in production. Carbon nanotube field effect transistors (CNTFETs) are considered a proper option to replace CMOS near term owing to their superior properties such as scalability and better channel electrostatics. For this purpose, a low-voltage, low-power Voltage Differencing Inverting Buffered Amplifier (VDIBA) structure is propose with a 32 nm CNTFET, in this article. The proposed CNTFET VDIBA structure operates with a bias current of 1 µA and consumes 14.32 µW of power with a supply voltage of ± 0.3 V. Compared to the traditional CMOS VDIBA structure, the power consumption is reduced by 733 times. Besides, proposed VDIBA structure has a bandwidth of 43.788 GHz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"1 - 8"},"PeriodicalIF":1.2,"publicationDate":"2024-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141504163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High gain transimpedance amplification for wireless glucose monitoring in a wearable health sensor system","authors":"A. S. A. A. Bakar,&nbsp;S. F. W. M. Hatta,&nbsp;N. Soin,&nbsp;M. H. A. Nouxman,&nbsp;F. A. M. Rezali,&nbsp;M. H. M. Daut","doi":"10.1007/s10470-024-02276-x","DOIUrl":"10.1007/s10470-024-02276-x","url":null,"abstract":"<div><p>This paper presents the development of a wireless data acquisition system for a wearable health sensor designed to measure glucose levels, pulse rate, and body temperature. The method emphasizes non-invasive and continuous monitoring to provide timely healthcare interventions. The designed system prioritizes wearability, flexibility, compactness, and low power consumption for user comfort and convenience. A transimpedance amplifier is designed to increase the glucose sensor signal with optimal gain and bandwidth, utilizing modeling tools for accurate signal processing. Filters, amplifiers, analog-to-digital converters, and a microcontroller for data processing and wireless transmission were used to create an integrated multi-input readout circuit for all three sensors. The work aims to develop a small and efficient circuit consuming less than 100 mW and occupying less than 6 cm². This research extensively covers the design and optimization of a transimpedance amplifier, the development of an integrated multi-input readout circuit, and the incorporation of low-power Bluetooth data transfer for a wearable health sensor system. The biosensor’s 10 uA signal range was effectively amplified to a voltage level that is readable, guaranteeing a minimum gain of 10,000 and converting it from current to voltage for measurement. An important milestone was achieved by integrating the communication of the amplified signal, heart rate, and temperature characteristics to the host application using Bluetooth. The complete system has been efficiently contained within a compact 6 cm² footprint.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 2-3","pages":"141 - 153"},"PeriodicalIF":1.2,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141504222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluating FPGA-based denoising techniques for improved signal quality in electrocardiograms","authors":"G. Keerthiga,&nbsp;S. Praveen Kumar","doi":"10.1007/s10470-024-02277-w","DOIUrl":"10.1007/s10470-024-02277-w","url":null,"abstract":"<div><p>The alarming mortality rates associated with cardiac abnormalities emphasize the critical need for early and accurate detection of heart disorders to mitigate severe health consequences for patients. Electrocardiograms (ECG) are commonly employed instruments for the examination of cardiac disorders, with a preference for noise-free ECG signals to ensure precise interpretation. However, ECG signal recordings are susceptible to environmental interferences, including patient movement and electrode positioning. This paper introduces a hardware implementation for denoising ECG signals, leveraging a novel method by integrating high-order Synchrosqueezing Transform, Detrended Fluctuation Analysis, and Non-Local-Mean filter optimized by Particle Swarm Optimization (HSST-DFA-PSO-NLM) techniques on Field-Programmable Gate Array (FPGA) platforms. FPGA-based processing units are chosen for their outstanding performance attributes, including high re-programmability, speed, architectural flexibility, and low power consumption, resulting in efficient signal processing. The effectiveness of the designed filtering algorithm is evaluated using key criteria, including Signal-to-Noise Ratio (SNR) and Root Mean Square Error (RMSE) for performance assessment. Additionally, resource utilization metrics such as Look-Up Tables (LUTs), Flip Flops, and DSP Blocks, as well as power consumption measures including dynamic power and static or leakage power, are analysed across various FPGA boards (Virtex and Zedboards) utilizing the VIVADO environment. Comparative analyses are conducted to identify the most suitable FPGA board for implementation, highlighting the superior performance of the proposed design. Remarkably, the proposed denoising solution gives excellent SNR of 29.56, 29.68, and 28.86 by denoising various ECG noises. The RMSE attained by the model is also less than 0.05. This research advances the field of cardiac disorder detection by providing a reliable and efficient FPGA-based solution for ECG signal denoising, thereby enhancing the accuracy of early diagnosis and treatment.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"93 - 107"},"PeriodicalIF":1.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141504164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comprehensive review: ultra-low power all-digital phase-locked loop RF transceivers for biomedical monitoring applications","authors":"Abdul Khaliq,&nbsp;Jahariah Sampe,&nbsp;Fazida Hanim Hashim,&nbsp;Huda Abdullah,&nbsp;Noor Hidayah Mohd Yunus,&nbsp;Muhammad Asim Noon","doi":"10.1007/s10470-024-02272-1","DOIUrl":"10.1007/s10470-024-02272-1","url":null,"abstract":"<div><p>This paper comprehensively reviews the evolution and latest advancement of ultra-low All-Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical monitoring devices. With CMOS technology, these transceivers provide efficiency and simplicity, which are essential in the medical industry. As the size and power needs of these devices decrease due to CMOS scaling, they become more suitable for small and low-energy applications. In addition, this review also provides an insight into the ADPLL applications, Digital Controlled Oscillator (DCO), and Phase Frequency Detectors. The review highlights notable differences in performance between time-to-digital converters (TDC) and TDC-less designs. TDC-less design, like Digital Phase Frequency Detectors (DPFD), offers improvements in phase noise, small size, fast phase and frequency acquisition, and power efficiency at the expense of resolution. Comparing LC-DCO and ring-DCO revealed that at high operating frequencies, the ring-DCO consumes more power but has a simpler design and a smaller circuit area than LC-DCO. Future research should focus on enhancing the performance of the ADPLL RF transceiver for biomedical devices, specifically by using a low-voltage supply and implementing DPFD to achieve low power consumption, compact design and fast locking. The significant challenges remain in maintaining low power consumption at higher frequencies with Ring-DCO design. Using the Verilog HDL for ADPLL design and implementation provides modularity, simulation, synthesis, and flexibility, which makes it an excellent alternative to designing RF transceivers in biomedical applications which are efficient and reliable.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 3","pages":"391 - 415"},"PeriodicalIF":1.2,"publicationDate":"2024-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140939823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}