Analog Integrated Circuits and Signal Processing最新文献_第2页

Enhanced gain with CRM inspired star shaped microstrip patch antenna for wireless application 增强增益与CRM启发星形微带贴片天线无线应用

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-22 DOI: 10.1007/s10470-025-02502-0

M. V. Tirupatamma, B. Leela Kumari, B. Rama Rao

{"title":"Enhanced gain with CRM inspired star shaped microstrip patch antenna for wireless application","authors":"M. V. Tirupatamma, B. Leela Kumari, B. Rama Rao","doi":"10.1007/s10470-025-02502-0","DOIUrl":"10.1007/s10470-025-02502-0","url":null,"abstract":"<div><p>This paper presents a novel metamaterial-inspired star shaped microstrip patch antenna (MPA) designed for enhanced performances in wireless applications. Unlike conventional MPA designs that suffer from low gain, narrow bandwidth, and poor radiation efficiency, the proposed antenna introduced a circular ring metamaterial (CRM) structure with cross shaped defected ground structure (Cr-DGS) to significantly enhance gain, directivity, and radiation characteristics. The antenna is designed on FR-4 substrate material with a relative permittivity of 4.4 and loss tangent of 0.025, and resonating frequency of 2.82 GHz using a coaxial probe feeding mechanism for impedance matching. The antenna is designed with an overall dimension of <span>(50, times 50 times 1.6)</span> mm<sup>3</sup>, which is operated at 1 GHz to 4 GHz. A key innovation lies in the integration of symmetric CRM units and star shaped patch, which facilitates uniform current distribution and superior electromagnetic field confinement. Simulation and experimental results confirm maximum gain values of 7.3 dB and directivity of 6.6 dB, which outperform several recent benchmark designs. This unique combination of geometry and metamaterial engineering establishes the proposed model as a compact, high-performance solution for next generation wireless systems, including IoT and 5G.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Self-calibrated comparator and capacitor DAC design for high-precision SAR-ADC 高精度SAR-ADC的自校准比较器和电容DAC设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-22 DOI: 10.1007/s10470-025-02501-1

TaeIl Hwang, Fawad Khan Yousufzai, Syed Asmat Ali Shah, HyungWon Kim

{"title":"Self-calibrated comparator and capacitor DAC design for high-precision SAR-ADC","authors":"TaeIl Hwang, Fawad Khan Yousufzai, Syed Asmat Ali Shah, HyungWon Kim","doi":"10.1007/s10470-025-02501-1","DOIUrl":"10.1007/s10470-025-02501-1","url":null,"abstract":"<div><p>This paper introduces a self-calibration architecture for a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Single-ended SAR ADCs often encounter challenges such as comparator offset voltage and mismatch in the capacitive digital-to-analog converter (CDAC), which can significantly degrade the overall performance. To address these issues, the proposed ADC employs a self-calibration technique that compensates for comparator offset and DAC mismatch. The comparator calibration is realized using the metal oxide semiconductor (MOS) capacitors, and the DAC mismatch is corrected with an additional calibration DAC. The proposed 12-bit SAR ADC is designed and implemented in complementary metal oxide semiconductor (CMOS) 55 nm library using Cadence Virtuoso design suite. The self-calibration technique significantly enhances ADC performance, increasing the effective number of bits (ENOB) from 9.23 to 10.89 compared to the conventional SAR ADC. It also achieves a differential nonlinearity (DNL) of + 0.53/-0.51 LSB and an integral nonlinearity (INL) of + 0.024/-1.73 LSB, at sampling rate of 17.8 MS/s. The proposed architecture consumes an average power of 7.9µW, while occupies an active area of 0.077<span>(:m{m}^{2})</span>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly efficient analog emulator circuit of memristive behavior as substitute for real memristor 高效的忆阻行为模拟仿真电路，可替代真实的忆阻器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-22 DOI: 10.1007/s10470-025-02513-x

Rajeev Ranjan Kumar, Akhilesh Kumar, Abhishek Kumar

{"title":"Highly efficient analog emulator circuit of memristive behavior as substitute for real memristor","authors":"Rajeev Ranjan Kumar, Akhilesh Kumar, Abhishek Kumar","doi":"10.1007/s10470-025-02513-x","DOIUrl":"10.1007/s10470-025-02513-x","url":null,"abstract":"<div><p>The HP memristor model serves as a theoretical benchmark for comprehending memristive behaviour; nevertheless, fabrication difficulties limit its physical realisation. This research introduces a circuit-based design of an equivalent HP memristor model. In order to replicate the non-linear characteristics of the HP memristor using a charge-dependent resistance modulation technique, the proposed emulator is designed using off-the-shelf components such as an operational transconductance amplifier (OTA), a modified second-generation current conveyor (M-CCII), an operational amplifier (Op-amp), resistors, and a capacitor. The primary objective is to develop a low-cost, user-friendly emulator suitable for real-time applications. As per the simulation results, the charge-controlled memristor emulator successfully replicates key memristive properties including hysteresis, non-volatility, and dynamic resistance switching. The emulator’s performance is verified through PSpice simulations using 0.18 μm CMOS technology, demonstrating effective operation up to 120 kHz under low power conditions. Additionally, the proposed emulator has been validated by both simulation and experimental using the commercial ICs AD844 and LM13700. Finally, the functional applicability of the proposed emulator is demonstrated through its integration in an amoeba adaptive learning circuit.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

From planar to stacked: a comparative analysis of 2D and 3D ICs from the perspective of architecture, performance, and fabrication 从平面到堆叠：从架构、性能和制造角度对2D和3D集成电路的比较分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-17 DOI: 10.1007/s10470-025-02507-9

Radha R.C, Mihir Sangli, Spoorthi Sripad, Nithya R, Likhitha N, Eesha D

{"title":"From planar to stacked: a comparative analysis of 2D and 3D ICs from the perspective of architecture, performance, and fabrication","authors":"Radha R.C, Mihir Sangli, Spoorthi Sripad, Nithya R, Likhitha N, Eesha D","doi":"10.1007/s10470-025-02507-9","DOIUrl":"10.1007/s10470-025-02507-9","url":null,"abstract":"<div><p>This paper compares the performance, architecture, and challenges of two-dimensional (2D) and three-dimensional (3D) integrated circuits (ICs). As the semiconductor industry aims for enhanced performance, a noticeable shift has occurred from 2D to 3D designs. This study is based on a comprehensive review of approximately 33 papers published between 2000 and 2024. The extensive literature base enriches our research’s depth and nuance, Making it well-informed and impactful. Relying on simulations and experimental data, key issues such as heat Management, component density, and power efficiency are examined. It addresses essential factors, including processing speed, power consumption, heat management, and scalability, while analyzing the advantages and disadvantages of each design. The paper also investigates the challenges of manufacturing, reliability, costs, signal quality, and the ability of current design tools to meet the demands of these technologies. While 2D ICs are more straightforward and less expensive, 3D ICs offer significant advantages. They can accommodate more components in less space, operate at higher speeds, and consume less power due to the stacking of layers and reduced connection distances. This research enhances our understanding of future trends in IC technology. It could guide the semiconductor industry in addressing the growing demand for faster, more powerful, and more energy-efficient devices.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low pass/Band pass filter transformation using lumped capacitors and DGS configuration for wireless networks 一种使用集总电容器和DGS配置的无线网络低通/带通滤波器变换

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-15 DOI: 10.1007/s10470-025-02496-9

Ashraf E. Ahmed, Wael A.E. Ali, Mohamed I. Shehata, Ahmed A. Ibrahim

{"title":"A low pass/Band pass filter transformation using lumped capacitors and DGS configuration for wireless networks","authors":"Ashraf E. Ahmed, Wael A.E. Ali, Mohamed I. Shehata, Ahmed A. Ibrahim","doi":"10.1007/s10470-025-02496-9","DOIUrl":"10.1007/s10470-025-02496-9","url":null,"abstract":"<div><p>In this work, the design of the LPF/BPF transformation bandpass filter is specifically suitable for wireless communications. The filter utilizes microstrip lines and the defected ground structure (DGS) loaded with lumped capacitors. The overall dimensions of the filter are 20 × 30 <i>mm</i><sup>2</sup>. The design includes Rogers 4003 substrate with a dielectric constant of 3.55 and 0.813-mm thickness. First, the LPF is designed to have a cutoff frequency and attenuation pole at 3.5 and 5.4 GHz, respectively. The LPF achieved S<sub>21</sub> ≤ -0.6 dB in the pass band and band rejection ≤ -10 dB from 4.2 GHz to 8.17 GHz. Moreover, the resulting BPF exhibits a central frequency of 2.45 GHz, with a frequency range extended from 2.1 to 2.8 GHz (0.7 GHz) and the fractional bandwidth (FBW) of 28.57%. The S<sub>11</sub> is nearly − 17 dB, while the S<sub>21</sub> is about − 0.7 dB, with a transmission zero at 3.1 GHz and a band stop ≤ -10 dB from 3.1 to 8 GHz. The study includes a parametric analysis to achieve the ideal value of S<sub>21</sub> and S<sub>11</sub>. To assess the filter’s behavior, simulations and investigations were implemented using the EM simulator. The achieved outcomes illustrate that the LPF/BPF is appropriate for wireless applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145062157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring analog VLSI architectures for linear regulators and high-speed receivers: a comprehensive SLR and emerging innovations 探索线性稳压器和高速接收器的模拟VLSI架构：全面的单反和新兴创新

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-15 DOI: 10.1007/s10470-025-02486-x

Suresh Nagula, Sreehari Rao Patri, Ekta Goel

引用次数: 0

A clock-less coherent ultrawideband detector for active-reflector-based ranging with high interference rejection 一种无时钟相干超宽带探测器，用于基于主动反射器的高抗干扰测距

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-15 DOI: 10.1007/s10470-025-02504-y

Amirehsan Shahraki, Mohammad Taherzadeh, Shoeib Rahmatollahi , Frederic Nabki

{"title":"A clock-less coherent ultrawideband detector for active-reflector-based ranging with high interference rejection","authors":"Amirehsan Shahraki, Mohammad Taherzadeh, Shoeib Rahmatollahi , Frederic Nabki","doi":"10.1007/s10470-025-02504-y","DOIUrl":"10.1007/s10470-025-02504-y","url":null,"abstract":"<div><p>This paper introduces a clock-less coherent ultrawideband (UWB) detector tailored for active-reflector-based ranging systems, specifically engineered for robust performance in high-interference environments. Conventional impulse-radio UWB (IR-UWB) ranging systems often face challenges with various interference sources, which can degrade their precision. Non-coherent detectors, while offering design simplicity, typically exhibit lower sensitivity and greater susceptibility to interference. Conversely, existing coherent detectors, though inherently more robust, often introduce complexities related to precise clock synchronization and overall system cost. This research addresses these limitations by evolving a previously developed non-coherent two-way ranging system through the design and implementation of a novel coherent UWB detector. The proposed architecture enhances interference resilience by employing binary phase shift keying (BPSK) combined with pulse position modulation (PPM) for sync word encoding, a more robust alternative to on-off keying (OOK) based methods. A critical innovation lies in the sync word detector circuit, which features a configurable 4-bit sync word, tunable delay lines, and dual comparators, enabling high selectivity for the intended UWB signal. Fabricated using 65 nm CMOS technology, the proposed detector maintains comparable timing accuracy to its non-coherent predecessor while demonstrating markedly superior rejection capabilities against single-tone interference (STI), narrowband interference (NBI), and co-channel UWB interference. These empirical results underscore the detector’s suitability for demanding applications that require dependable ranging performance amidst pervasive radio frequency interference.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145062156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient transition from SMA to ESIW for planar slot array antennas in wireless systems 无线系统中平面槽阵天线从SMA到ESIW的有效过渡

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-11 DOI: 10.1007/s10470-025-02498-7

Ahmad Parsa, Pejman Rezaei, Ali AmneElahi, Amin Khatami, Zahra Mousavirazi

{"title":"Efficient transition from SMA to ESIW for planar slot array antennas in wireless systems","authors":"Ahmad Parsa, Pejman Rezaei, Ali AmneElahi, Amin Khatami, Zahra Mousavirazi","doi":"10.1007/s10470-025-02498-7","DOIUrl":"10.1007/s10470-025-02498-7","url":null,"abstract":"<div><p>In this manuscript, a planar slot array antenna is designed to operate at 10 GHz using empty substrate integrated waveguide (ESIW) technology. ESIW is an advanced form of substrate integrated waveguide (SIW) in which the dielectric material between the metal layers is removed and replaced with air to significantly reduce dielectric losses and improve radiation efficiency. The proposed structure is implemented on a standard PCB and consists of three main parts: (1) a coaxial (SMA) to SIW transition, (2) a tapered SIW-to-ESIW transition section, and (3) an eight-element ESIW-based slot array radiator. By eliminating most of the dielectric material, the ESIW-based design achieves enhanced radiation efficiency and lower insertion loss compared to conventional SIW slot arrays. The overall physical dimensions are 22 × 221 × 4.4 mm³, and the antenna achieves a fractional bandwidth of 3.85%, with a radiation efficiency of approximately 94% and a realized gain of 15.6 dB at the center frequency. The performance of the antenna was evaluated using full-wave simulations in CST, and the results show excellent agreement with experimental measurements.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145037139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards robust true random number generation: addressing vulnerabilities in dual entropy source design 面向鲁棒真随机数生成：解决双熵源设计中的漏洞

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-10 DOI: 10.1007/s10470-025-02488-9

R. Sivaraman, H. Naresh Kumar, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram

{"title":"Towards robust true random number generation: addressing vulnerabilities in dual entropy source design","authors":"R. Sivaraman, H. Naresh Kumar, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram","doi":"10.1007/s10470-025-02488-9","DOIUrl":"10.1007/s10470-025-02488-9","url":null,"abstract":"<div><p>Recently, Chen et al. introduced a dynamic dual entropy source-assisted True Random Number Generator (TRNG) implemented on a Field Programmable Gate Array (FPGA). They asserted that their design achieved superior true randomness and higher throughput. This paper comprehensively analyses Chen et al.‘s TRNG [1], identifying potential vulnerabilities. Chen et al. employed a Multiplexer Ring Oscillator (MRO) as the entropy source for generating true random numbers. This MRO leverages dual entropy sources—metastability and clock jitter—to create true randomness. By exploiting the weaknesses inherent in the MRO, we critically examine the results and validation of Chen et al.‘s TRNG. Despite the TRNG’s minimal hardware footprint on the AMD-Xilinx Artix-7 FPGA—utilizing only 10 number of LUTs, 2 number of DFFs, and 1 unit of MUX—and its impressive bit generation rate of 300 Mbps, it fails to produce adequate randomness. This inadequacy is evident when evaluated against standard metrics such as Shannon Entropy, Autocorrelation, and NIST SP 800 − 22. To address these deficiencies, we propose enhancing Chen et al.‘s TRNG, aimed at improving randomness without altering the entropy source, through lightweight post-processing. This approach yielded an 85.71% improvement in randomness after four rounds of post-processing. However, this enhancement significantly reduces throughput by a factor of ½. In conclusion, while the TRNG by Chen et al. demonstrates promising features, it necessitates a robust entropy source with a multi-ring structure rather than the dual-ring MRO for optimal performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigating the effects of interface trap charges and temperature on n-type step tunneling path TFET 研究界面陷阱电荷和温度对n型阶跃隧穿路径TFET的影响

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-10 DOI: 10.1007/s10470-025-02505-x

Jatismar Saha, Manosh Protim Gogoi, Bijit Choudhuri, Rajesh Saha

引用次数: 0