Analog Integrated Circuits and Signal Processing最新文献_第2页

Optimizing deep convolutional neural network with an IP-bounded binary optimization and optimal extreme learning machine for pulse repetition interval modulation recognition 基于ip有界二元优化和最优极值学习机的深度卷积神经网络脉冲重复间隔调制识别优化

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-21 DOI: 10.1007/s10470-026-02568-4

Xiaoxia Zheng, Seyed Majid Hasani Azhdari, Mohammad Khishe, Azar Mahmoodzadeh, Hamed Agahi

{"title":"Optimizing deep convolutional neural network with an IP-bounded binary optimization and optimal extreme learning machine for pulse repetition interval modulation recognition","authors":"Xiaoxia Zheng, Seyed Majid Hasani Azhdari, Mohammad Khishe, Azar Mahmoodzadeh, Hamed Agahi","doi":"10.1007/s10470-026-02568-4","DOIUrl":"10.1007/s10470-026-02568-4","url":null,"abstract":"<div>\u0000 \u0000 <p>The recognition of pulse repetition interval (PRI) modulation is one of the primary tasks of the modern electronic intelligence system (ELINT) and electronic support measure system (ESM) for accurately identifying threat radars. The PRI modulation recognition is a complex and challenging issue due to missing and spurious pulses and large outliers, which cause a very noisy sequence of PRI modulation changes in authentic settings. This paper presents an innovative three-phase technique to recognizing the five types of standard PRI modulation. First, an optimal deep convolutional neural network (ODCNN) structure is formed by the Internet Protocol-based bounded binary optimization (IP-BBO) using the data set as a feature extractor. Then, in the second step, the last fully connected layers of ODCNN are replaced by an extreme learning machine (ELM) to improve the time complexity of the proposed model and for real-time recognition. After that, in the third stage, BBO was introduced to adjust the biases and weights of ELM to reduce the complexity of the suggested method space. The proposed method performs better than other methods, with an accuracy of 99.22% and a training time of 109.46 s. The results indicate that the proposed method can be reliable and efficient in applications related to identifying PRI modulation by providing robust performance and high accuracy in all evaluation criteria. Also, the proper training time of this method has made it an ideal option for practical applications and sensitive environments that require fast and accurate processing.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147727322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.5V Energy efficient compact CMOS temperature sensor with a resolution of (0.08^circ text {C}) for portable applications 0.5V节能紧凑型CMOS温度传感器，分辨率为(0.08^circ text {C})，适用于便携式应用

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-13 DOI: 10.1007/s10470-026-02583-5

Chilaka Jayaram, Patri Sreehari Rao

{"title":"A 0.5V Energy efficient compact CMOS temperature sensor with a resolution of (0.08^circ text {C}) for portable applications","authors":"Chilaka Jayaram, Patri Sreehari Rao","doi":"10.1007/s10470-026-02583-5","DOIUrl":"10.1007/s10470-026-02583-5","url":null,"abstract":"<p>This paper introduces an energy-efficient CMOS temperature sensor suitable for portable device applications. The sensor’s front-end circuitry produces a voltage complementary to absolute temperature (CTAT) by passing the proportional to absolute temperature (PTAT) current through a diode connected MOSFET. The voltage to frequency conversion is achieved with the help of frequency locked loop (FLL) technique comprises a charge pump, voltage controlled oscillator, and a subtractor. By introducing the charge pump in the feedback mechanism, which effectively compensates the process and voltage variations across different operating conditions. Conversion from frequency to digital output is achieved through an asynchronous counter with an on-chip oscillator. Hence, there is no requirement for an additional clock reference for digital calibration. The proposed design is realized in a 0.18 <span>(mu)</span>m CMOS technology and attains a power usage of 983.2 nW at <span>(27^circ text {C})</span> with a power supply of 0.5V. Furthermore, it obtains an inaccuracy of <span>(pm 0.6^circ text {C})</span> across -40 to <span>(125^circ text {C})</span> temperature range with an active area of <span>(0.019hbox {mm}^{2})</span>. Moreover, the designed sensor circuit offers a resolution of <span>(0.08^circ text {C})</span> with a figure of merit (FoM) of <span>(1,hbox {pJ.K}^{2})</span>.</p>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147737665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Correction: Optimization of novel DPTL-PFD design for fast-settling PLL frequency synthesizer using Taguchi–ANOVA 修正：使用田口方差分析优化快速稳定锁相环频率合成器的新型DPTL-PFD设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-10 DOI: 10.1007/s10470-026-02569-3

Archana Singhal, Jyoti Sharma, Dheeraj Singh Rajput, Dharmendar Boolchandani, C. Periasamy

引用次数: 0

Reinforcement learning-driven fault-tolerant routing for mesh-based Network-on-Chip architectures 基于网格的片上网络架构的强化学习驱动容错路由

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-07 DOI: 10.1007/s10470-026-02584-4

Challa Muralikrishna Yadav, B. Naresh Kumar Reddy

{"title":"Reinforcement learning-driven fault-tolerant routing for mesh-based Network-on-Chip architectures","authors":"Challa Muralikrishna Yadav, B. Naresh Kumar Reddy","doi":"10.1007/s10470-026-02584-4","DOIUrl":"10.1007/s10470-026-02584-4","url":null,"abstract":"<div>\u0000 \u0000 <p>Network-on-Chip (NoC) has emerged as a promising interconnection framework for Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. However, in deep submicron technologies, NoCs are increasingly susceptible to faults in critical components such as links and routers, leading to reduced system performance and reliability. This paper presents a novel Deep Q-Network (DQN)-based Fault-Tolerant Routing (DQN-FTR) algorithm designed to optimize routing decisions in mesh-based NoC architectures. The proposed approach is evaluated against traditional Q-learning and static routing techniques under varying traffic patterns and fault conditions. A SystemC-based cycle-accurate NoC simulator is used to conduct extensive simulations across different mesh sizes and fault scenarios. Additionally, the algorithm’s real-time performance is validated using the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. Experimental results demonstrate that the DQN-FTR algorithm significantly outperforms Q-learning and static routing in terms of latency, throughput, and fault tolerance, providing a robust and scalable solution for fault-tolerant routing in NoCs.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147642767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power-efficient 2:1 MUX and 1:2 DEMUX architectures in 90 NM technology using SVL and FinFET approaches 采用SVL和FinFET方法的90纳米技术的2:1 MUX和1:2 DEMUX架构

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-06 DOI: 10.1007/s10470-026-02581-7

Shekhar Milind Mane, Dnyandeo J. Pete

{"title":"Power-efficient 2:1 MUX and 1:2 DEMUX architectures in 90 NM technology using SVL and FinFET approaches","authors":"Shekhar Milind Mane, Dnyandeo J. Pete","doi":"10.1007/s10470-026-02581-7","DOIUrl":"10.1007/s10470-026-02581-7","url":null,"abstract":"<div>\u0000 \u0000 <p>Low power, high speed 2:1 MUX designs using static CMOS and pseudo NMOS logic are listed in this study together with 1:2 DEMUXes using pass transistor-based and CMOS-based DEMUXes. Compared with previous studies, which evaluated SVL or FinFET approaches singly, this study provides a comprehensive comparative examination of numerous logic styles—static CMOS, pseudo-NMOS, and pass-transistor—under identical simulation settings. The suggested methodology offers useful design insights for selecting low-power MUX/DEMUX designs in 90 nm technology. When applied to a 2:1 MUX architecture with pseudo NMOS and static CMOS logic, SVL (Supply Voltage Level) is one of the most important low power techniques that effectively lowers leakage power. The SVL operates by combining the functions of the Upper and Lower SVL circuits. By sending a base ground state voltage and a maximum supply voltage separately to the dynamic load circuit, SVL circuits can optimize the 2:1 MUX circuit’s operating speed. Upper and Lower SVL circuits are run concurrently in order to minimize leakage power in SVL circuits. FinFET (Fin Shaped Field Effect Transistor) technology are used to implement the 1:2 DEMUX using static CMOS logic, pass transistor logic. Optimal current, entry dielectric spillage, short channel effects, and device-to-device variations are the primary obstacles to expanding bulk CMOS gate lengths. In any case, designs based on FinFETs provide increased yield, reduced leakage, and improved power over short channel effects.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147642806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Triple metal gate vertical TFET with SiGe/Si heterojunction for high-performance and low-power VLSI circuits 用于高性能和低功耗VLSI电路的SiGe/Si异质结三重金属栅极垂直TFET

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-04-04 DOI: 10.1007/s10470-026-02582-6

Debasish Mohanta, Sruti Suvadarsini Singh, Prasanna Kumar Sahu

{"title":"Triple metal gate vertical TFET with SiGe/Si heterojunction for high-performance and low-power VLSI circuits","authors":"Debasish Mohanta, Sruti Suvadarsini Singh, Prasanna Kumar Sahu","doi":"10.1007/s10470-026-02582-6","DOIUrl":"10.1007/s10470-026-02582-6","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a comprehensive simulation-based investigation of a Triple-Metal-Gate Vertical Tunnel Field-Effect Transistor (TMG-VTFET) on a doped silicon substrate and explores its potential for low-power analog and mixed-signal circuit applications. The proposed device employs a triple-segment gate, where the central segment is engineered with a higher work function as compared to the adjacent segments, forming an internal channel barrier that enables precise control of the band-to-band tunneling mechanism while significantly suppressing ambipolar current. To further enhance tunneling efficiency and ON-state performance, a SiGe source pocket is incorporated. Detailed Silvaco ATLAS TCAD simulations reveal that the optimized SiGe-pocket TMG-VTFET (TMG-VTFET-WP) achieves a steep subthreshold swing below 12.40 mV/dec, an I<sub>ON</sub>/I<sub>OFF</sub> ratio exceeding 10¹⁴, and an ON-state current on the order of 10⁻⁴ A/µm—performance metrics that remarkably surpass those of the pocket-less counterpart. Circuit-level suitability is evaluated using Cadence, where the TMG-VTFET-WP is integrated into CMOS inverter and ring oscillator circuits; the results confirm robust DC characteristics, improved switching speed, and reliable transient response. Ultimately, the simulation-based results confirm that the SiGe-pocket TMG-VTFET (TMG-VTFET-WP) achieves exceptional device performance, making it a promising candidate for energy-efficient integration in future analog and digital system designs.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analyzing time and power efficiency of machine learning models on edge devices 分析边缘设备上机器学习模型的时间和功率效率

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-26 DOI: 10.1007/s10470-026-02580-8

Heba Khdr, Mohamed Aboelenien Ahmed, Yiğit Oğuz, Jörg Henkel

{"title":"Analyzing time and power efficiency of machine learning models on edge devices","authors":"Heba Khdr, Mohamed Aboelenien Ahmed, Yiğit Oğuz, Jörg Henkel","doi":"10.1007/s10470-026-02580-8","DOIUrl":"10.1007/s10470-026-02580-8","url":null,"abstract":"<div>\u0000 \u0000 <p>Edge machine learning (EdgeML) refers to the execution of machine learning (ML) algorithms on devices located close to data sources. The primary goals of EdgeML are to reduce response time and preserve data privacy. Nevertheless, edge devices often face constraints in processing power, memory, and energy, making it challenging to deploy complex ML models, including neural networks (NNs). To address these limitations, significant efforts have focused on improving the time and power efficiency of EdgeML through model optimization and the use of hardware accelerators. Orthogonal to these efforts, this paper introduces EdgeMLProfiler, a novel open-source tool (https://gitlab.kit.edu/uexfc/EdgeMLProfiler), designed to evaluate the time and power consumption of training and inference processes for selected NNs across various hardware architectures and software libraries. Using EdgeMLProfiler, we present–for the first time–a comparative time and power analysis of several NN models, including widely used convolutional neural networks (CNNs) and custom-designed fully-connected neural networks (FNNs). Our analysis reveals distinct efficiency patterns across different models and hardware configurations, providing practical insights for selecting the most time- and power-efficient deployment configurations for ML models on edge devices.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-026-02580-8.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147560971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study and analysis of memristor for analog and digital design 研究和分析了忆阻器的模拟和数字设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-24 DOI: 10.1007/s10470-026-02566-6

Jalpaben Pandya, Ramji Gupta

{"title":"Study and analysis of memristor for analog and digital design","authors":"Jalpaben Pandya, Ramji Gupta","doi":"10.1007/s10470-026-02566-6","DOIUrl":"10.1007/s10470-026-02566-6","url":null,"abstract":"<div><p>To fulfill the demands of the expanding IoT industry, new nonvolatile memories with increased speed, density, and reduced power consumption are required. Nonvolatile memories using memristor device has demonstrated excellent performance in memory applications. These memories have an advantage over traditional CMOS memories as they can be scaled to the nanoscale range. Additionally, the memory circuits designed using memristor offer high speed and consumes less power. Memristor devices are compatible with today’s mostly used CMOS and CNTFET technology, however integration at the device level is still challenging due to the unavailability of mature models for memristor. This study examines the fundamental working of a memristor along with its behaviour, characteristic equations, and fingerprints. Different memristor models are examined and contrasted along with its applications spanning all domains. Furthermore, a comprehensive review of various window functions used in memristor modeling is presented to highlight their impact on device behaviour and simulation accuracy. This review aims to familiarize circuit designers with the behaviour, models, and application areas of memristors. Lastly, a memristor is designed through LTspice using the Joglekar window function which meets the required fingerprints criteria and produces a pinched hysteresis loop at 700 Hz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147560877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of a high-sensitivity Ge-source DGTFET biosensor 高灵敏度锗源DGTFET生物传感器的研制

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-17 DOI: 10.1007/s10470-026-02579-1

Anil Kumar, Sandeep S. Gill, Kanika Sharma

{"title":"Development of a high-sensitivity Ge-source DGTFET biosensor","authors":"Anil Kumar, Sandeep S. Gill, Kanika Sharma","doi":"10.1007/s10470-026-02579-1","DOIUrl":"10.1007/s10470-026-02579-1","url":null,"abstract":"<div><p>This research proposes a Germanium-source-based Double Gate Tunnel Field-Effect Transistor (DGTFET) for biosensing applications, incorporating a nanocavity above the gate region for effective biomolecule detection. The hetero-material DGTFET architecture utilizes materials such as germanium and silicon to enhance band-to-band tunneling efficiency, reduce threshold voltage, and improve on-state current (Ion) through bandgap engineering across different gate regions. The sensing mechanism is based on variations in the drain current (Id) of an optimized germanium-source DGTFET, which is strongly influenced by the dielectric constant of immobilized biomolecules within the cavity. In the proposed design, the cavity dimensions range from 5–10 nm in length and 3–5 nm in width, allowing the accommodation of different analytes such as Keratin, APTES, and Biotin. Biomolecules with higher dielectric constants enhance the electrostatic coupling between the gate and channel, leading to an increase in the on-current and thereby improving the sensitivity of the device. However, as the cavity length increases, the effective capacitance decreases, resulting in a slight reduction in the drain current (Id).Furthermore, the impact of device scaling on the DGTFET performance is systematically analyzed with respect to the Si₁₋ₓGeₓ heterostructure model at the source and gate regions, along with variations in gate length, oxide thickness, and pocket thickness, under different doping concentrations (cm⁻³) across all regions. The scaling of pocket thickness in the channel region, combined with the incorporation of germanium at the source with optimized doping concentration, significantly enhances both voltage sensitivity and current sensitivity. Comparative analysis indicates that the proposed DGTFET biosensor demonstrates superior voltage sensitivity, improved subthreshold characteristics, enhanced carrier transport, optimized electrostatic control, and better device performance compared to previously reported Double Gate TFET devices in the literature.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147560013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGAs: architecture, design flow, and emerging applications—industrial perspectives fpga：架构，设计流程和新兴应用-工业前景

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-14 DOI: 10.1007/s10470-026-02563-9

Huu Q. Tran

{"title":"FPGAs: architecture, design flow, and emerging applications—industrial perspectives","authors":"Huu Q. Tran","doi":"10.1007/s10470-026-02563-9","DOIUrl":"10.1007/s10470-026-02563-9","url":null,"abstract":"<div>\u0000 \u0000 <p>The convergence of artificial intelligence, cyber–physical systems, and sustainable manufacturing is reshaping the industrial landscape under the principles of Industry 5.0. This evolution calls for hardware platforms that seamlessly combine real-time determinism, reconfigurability, and energy efficiency while ensuring long-term reliability in demanding environments. Field-Programmable Gate Arrays (FPGAs) have become pivotal in this transition, bridging the gap between general-purpose processors and application-specific hardware. This paper presents a comprehensive survey of modern FPGA technology from an Industry 5.0 perspective. More than one hundred recent studies, industrial reports, and vendor architectures are synthesised to characterise FPGA evolution across three dimensions: architectural foundations, unified design methodologies, and emerging application domains. The survey highlights how heterogeneous SoC integration, high-level synthesis, partial reconfiguration, and AI-assisted EDA workflows collectively enable deterministic, low-power, and adaptive hardware platforms for robotics, smart manufacturing, intelligent transportation, healthcare systems, and edge AI. Furthermore, the review outlines future directions, including chiplet-based integration, virtualized reconfigurable fabrics, neuromorphic/quantum hybrids, and sustainability-aware lifecycle design. By consolidating cross-domain insights, this survey positions FPGAs as a core enabling technology for human-centric, resilient, and sustainable Industry 5.0 cyber-physical ecosystems.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147441562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0