{"title":"An optimized LNA utilizing MGA for high performance 24 GHz radar applications","authors":"Unal Aras, Tahesin Samira Delwar, Murod Khurbanov, Yangwon Lee, Jee Youl Ryu","doi":"10.1007/s10470-025-02396-y","DOIUrl":null,"url":null,"abstract":"<div><p>In this paper, a novel 24 GHz low noise amplifier (LNA) is presented which is optimized using a modified genetic algorithm (MGA). A cascade topology and a noise canceling common source circuit are employed in the proposed LNA. To improve reverse isolation and increase power gain, the cascade structure is employed. Besides being in practice on other notes, simple genetic algorithms (SGAs) have difficulty exploring the extensive search space due to the high dimensionality of LNA circuit parameters, such as resistor and capacitor values. Also, SGA is challenging to escape local optima and arrive at the global optimal due to the fitness landscape’s nonlinearity and multimodality. To mitigate those issues, the MGA is proposed to optimize the LNA circuit efficiently. In optimizing LNA, a MGA is advantageous since it can efficiently explore a large design space and identify optimal solutions. Also, the proposed MGA reduces randomness in offspring generation. At 24 GHz, the measurement results show that optimized LNA achieves a gain of 13.8 dB and a noise figure of 3.8 dB. The IP<sub>1</sub>dB of the optimized LNA circuit is –9 dB. We have achieved a S<sub>11</sub> of –12 dB and a S<sub>22</sub> of –11 dB by matching the input and output impedances.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2000,"publicationDate":"2025-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02396-y","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a novel 24 GHz low noise amplifier (LNA) is presented which is optimized using a modified genetic algorithm (MGA). A cascade topology and a noise canceling common source circuit are employed in the proposed LNA. To improve reverse isolation and increase power gain, the cascade structure is employed. Besides being in practice on other notes, simple genetic algorithms (SGAs) have difficulty exploring the extensive search space due to the high dimensionality of LNA circuit parameters, such as resistor and capacitor values. Also, SGA is challenging to escape local optima and arrive at the global optimal due to the fitness landscape’s nonlinearity and multimodality. To mitigate those issues, the MGA is proposed to optimize the LNA circuit efficiently. In optimizing LNA, a MGA is advantageous since it can efficiently explore a large design space and identify optimal solutions. Also, the proposed MGA reduces randomness in offspring generation. At 24 GHz, the measurement results show that optimized LNA achieves a gain of 13.8 dB and a noise figure of 3.8 dB. The IP1dB of the optimized LNA circuit is –9 dB. We have achieved a S11 of –12 dB and a S22 of –11 dB by matching the input and output impedances.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.