Analog Integrated Circuits and Signal Processing最新文献_第3页

A low-voltage and low-power gm-C low-pass filter with tunable cut-off frequency suitable for a wide range of biomedical applications 具有可调截止频率的低压低功耗gm-C低通滤波器，适用于广泛的生物医学应用

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-11 DOI: 10.1007/s10470-026-02660-9

Ali Jalili, Soolmaz Abbasalizadeh, Mohsen Javadi

{"title":"A low-voltage and low-power gm-C low-pass filter with tunable cut-off frequency suitable for a wide range of biomedical applications","authors":"Ali Jalili, Soolmaz Abbasalizadeh, Mohsen Javadi","doi":"10.1007/s10470-026-02660-9","DOIUrl":"10.1007/s10470-026-02660-9","url":null,"abstract":"<div><p>This paper presents a low-pass Butterworth gm–C filter with a widely tunable cut-off frequency suitable for biomedical applications. The filter’s main building block, the operational transconductance amplifier (OTA) with a new tunable tail current sources generation circuit, provides a wide transconductance tuning range using a voltage supply to support the specifications of various biomedical applications. Moreover, this paper employs a source-degeneration technique to enhance the linearity of the OTA, which can deteriorate under low supply voltage conditions. The circuits are designed in a 0.18 μm CMOS process with a 1.2 V supply voltage. The filter has 302 nW power consumption, 47 Hz to 333 Hz tunable cut-off frequency, 313 μV<sub>rms</sub> to 90 μV<sub>rms</sub> input-referred noise voltage, and a dynamic range of 56.17 dB to 71.15 dB in the cut-off frequency tuning range. Besides, the paper uses process corners and temperature variations simulation to verify the efficiency of the filter after fabrication. The resulting specifications confirm the filter’s suitability for EEG, EMG, ECG, EOG, ERG, IEGM, and ENG biomedical applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148927490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-power RF down-conversion mixer design for emerging applications: review, analysis and technical recommendations 新兴应用的低功率射频下变频混频器设计：回顾，分析和技术建议

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-09 DOI: 10.1007/s10470-026-02665-4

Raja Mahmou

{"title":"Low-power RF down-conversion mixer design for emerging applications: review, analysis and technical recommendations","authors":"Raja Mahmou","doi":"10.1007/s10470-026-02665-4","DOIUrl":"10.1007/s10470-026-02665-4","url":null,"abstract":"<div><p>RF mixers are critical blocks in receiver chains; their design involves compromises between power consumption, conversion gain (CG), noise figure (NF), linearity, and isolation, taking particular account of the specific requirements of each RF targeted application, which imposes critical thresholds on one or more of these parameters. This study aims to provide a reference framework for relevant technical approaches to down-conversion mixer design. Passing through a reminder of passive and active topologies; towards a review of recent work (2020–2025) to identify the latest achievements. On this basis, an analysis was conducted on the evolution of critical parameters for each RF domain: IoT, 5G, Wi-Fi, millimeter-wave (mmWave), satellite, and automotive radars, this was followed by an analysis of the technologies used, such as Complementary Metal–Oxide–Semiconductor (CMOS), Silicon-On-Insulator (SOI), Silicon–Germanium (SiGe), and High Electron Mobility Transistor (HEMT), in relation to the achieved performances and functional requirements for RF analog designs. These studies allowed for the evaluation of the relative weight of NF, CG, Input Third-Order Intercept Point (IIP3), and Power Consumption according to the cited RF applications, which served as the basis for defining a Figure of Merit for down-conversion mixer (AM-FOM) adapted to RF applications. In addition, and regardless of application requirements, a Decision Flowchart for RF Down-Conversion Mixer Technology Selection (DFMTS) integrating frequency criteria and level of integration is proposed in this paper. Finally, an empirical function was suggested to illustrate the impact of operating frequency, technological node, and mixer topology on estimated consumption.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148926937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analog computation model using second generation voltage conveyors: numerical analysis 第二代电压输送机模拟计算模型：数值分析

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-09 DOI: 10.1007/s10470-026-02663-6

Ankit Kumar Gaur, Manish Verma, Dhandapani Vaithiyanathan

{"title":"Analog computation model using second generation voltage conveyors: numerical analysis","authors":"Ankit Kumar Gaur, Manish Verma, Dhandapani Vaithiyanathan","doi":"10.1007/s10470-026-02663-6","DOIUrl":"10.1007/s10470-026-02663-6","url":null,"abstract":"<div><p>This research paper presents a brief examination of analog computation employing the novel use of second-generation voltage conveyors (VCII). The focus is on performing basic arithmetic and mathematical functions such as differentiation, integration, inversion, logarithmic, modulus, multiplication, square root, squaring, subtraction, and summer computations. The findings of this work add to a better knowledge of analog computation techniques, paving the way for further exploration and innovation in the domain of analog computation and analog signal processing, where input parameters can be customized as voltage or current, and their magnitudes can be adjusted by using a weighted and non-weighted approach to meet specific requirements. The results of experiments and performance evaluations are presented, providing empirical evidence of the viability and precision of analog computation employing voltage conveyors. To confirm the operational integrity of the suggested circuits, we utilize a supply voltage of ±1.65 V and LTspice simulations with parameters corresponding to 0.18 µm CMOS technology.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148926936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A hybrid channel-spatial attention mechanism in capsule networks for histopathology analysis 胶囊网络中混合通道-空间注意机制的组织病理学分析

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-06 DOI: 10.1007/s10470-026-02646-7

B. Syambabu, V. D. Ambeth Kumar, V. D. Ashok Kumar

{"title":"A hybrid channel-spatial attention mechanism in capsule networks for histopathology analysis","authors":"B. Syambabu, V. D. Ambeth Kumar, V. D. Ashok Kumar","doi":"10.1007/s10470-026-02646-7","DOIUrl":"10.1007/s10470-026-02646-7","url":null,"abstract":"<div><p>One of the most deadly types of cancer that impact women worldwide is breast cancer (BC). Ultrasonography and mammography are two common ways to screen for breast cancer. One of the main shortcomings of existing methods is their incapacity to distinguish between benign and malignant cancer. It is a crucial diagnostic tool for BC diagnosis because the histopathology-based classification of breast cancer is based on histological images of BC. The article presents a novel deep learning approach for creating a multi-class BC classification model. The study’s dataset came from databases that are open to the public. Additionally, the histopathology images were subjected using Improved Anisotropic Filtering (IAF) in order to minimize noise. The model tumor region is segmented using a Modified Deep-View Fuzzy C-Means Clustering (MDV-FCMC) technique to increase its flexibility. Important features were then extracted using the Discrete Wavelet Hadamard Transform (DW-HT) and the Grey Level Co-occurrence Matrix (GLCM). The feature dimensionality problems must then be resolved. The method known as Enhanced Pufferfish Optimization (EPO) is used to choose the best features. To categorize the multi-class BC illness, the Channel-Spatial Attention based Convolutional Capsule Network (CSA-CCN) is presented based on these chosen features. Lastly, to improve the classifier model’s effectiveness, the Honey Badger Optimization (HBO) technique is used. With classification accuracy of 97.99%, precision of 96.43%, recall of 96.36%, and F1-score of 97.18%, the proposed method has shown encouraging results. It also effectively classifies the multi-class breast cancer disease from histological pictures.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148926951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and FPGA implementation of reversible vedic multipliy and accumulate unit for cryptography applications 用于密码学应用的可逆vedic乘积单元的设计与FPGA实现

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-04 DOI: 10.1007/s10470-026-02653-8

V. Thamizharasan, A. Nikhil, M. Vigneshwara, B. Mahesh Bala, S. Vasantha Kumar

{"title":"Design and FPGA implementation of reversible vedic multipliy and accumulate unit for cryptography applications","authors":"V. Thamizharasan, A. Nikhil, M. Vigneshwara, B. Mahesh Bala, S. Vasantha Kumar","doi":"10.1007/s10470-026-02653-8","DOIUrl":"10.1007/s10470-026-02653-8","url":null,"abstract":"<div><p>The Multiply and Accumulate (MAC) unit is a dynamic constituent in signal processing, cryptography and quantum computing, with low power and high speed is the necessary design. Conventional MAC units are implemented via irreversible logics that ultilizes high power resultant in information loss. To beat this limit, this paper contributes a Reversible Vedic Multiplier–Accumulator (RVMAC) that integrates the Vedic (Urdhva Tiryakbhyam) method with reversible logic to construct an energy-optimal arithmetic hardware. The unify Reversible Carry Save Adder (RCSA) is engage in the framework for partial product summation and accumulation, which provides less delay and high-speed functioning with less information loss. Designed in a ranked order from a 2-bit multiplier block, that scalable upto 4-bit, 16-bit, 32 bit so on, which enables optimal quantum cost, garbage outputs and constant inputs. The entire framework is designed and implemented in Xilinx Artix-7 FPGA. The synthesized report shows that speed of the proposed Reversible Vedic Multiplier–Accumulator (RVMAC) architecture is improved by 37.98%, 24.47%, 37.43%, 33.73% and 12.29% as compared to MAC using Wallace multiplier, Dadda multiplier, Vedic Multiplier, Compressor based multiplier and Booth multiplier respectively. Similarly, the power consumption of proposed RVMAC is improved by 7.92%, 5.429%, 4.12%, 7.11% and 1.415% as compared to MAC using Wallace multiplier, Dadda multiplier, Vedic Multiplier, Compressor based multiplier and Booth multiplier respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148926306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Single OTRA based multifunction inverse filter 基于单OTRA的多功能反滤波器

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-02 DOI: 10.1007/s10470-026-02621-2

Subhasish Banerjee, Pulak Mondal, Mourina Ghosh, Rajeev Kumar Ranjan

{"title":"Single OTRA based multifunction inverse filter","authors":"Subhasish Banerjee, Pulak Mondal, Mourina Ghosh, Rajeev Kumar Ranjan","doi":"10.1007/s10470-026-02621-2","DOIUrl":"10.1007/s10470-026-02621-2","url":null,"abstract":"<div><p>In recent years, the capacity of inverse filters (IFs) to reconstruct a distorted signal has led to an increase in their employment as a signal conditioning circuit in analogue signal processing. In this research, a novel method for operating an inverse filter of third order is presented. Using a single Operational Transresistance Amplifier (OTRA) and some passive components, the third order inverse low pass filter (ILPF), inverse high pass filter (IHPF), and inverse band pass filter (IBPF) have all been realised in this study. The suggested third order inverse filters outperform existing second order inverse filters reported in various literatures by 33.15% to 46.82% and third order inverse filters by 1.71% to 10.75% according to its frequency roll-off, which ranges from 53.26 dB/decade to 58.73 dB/decade. To ensure that the suggested configuration would function; SPICE simulation was run using a CMOS model of OTRA using 180 nm technology. In addition to the simulated results, a theoretical study of the inverse filters has been presented. Close concordance between theoretical and simulated results is observed. Additionally, SPICE is used for the noise analysis, temperature analysis, Monte Carlo analysis with a 5% variation in the values of the passive components, and THD analysis of the suggested filters. Analyses of sensitivity have also been conducted. To test the viability of the suggested design, hardware implementation was done using the AD844AN IC.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148871711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparative analysis of noise effects on triple, double, and single material gate step FinFET 三、双、单材料栅极场效应管噪声影响的比较分析

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-02 DOI: 10.1007/s10470-026-02642-x

Rinku Rani Das, Atanu Chowdhury, Apurba Chakraborty

{"title":"Comparative analysis of noise effects on triple, double, and single material gate step FinFET","authors":"Rinku Rani Das, Atanu Chowdhury, Apurba Chakraborty","doi":"10.1007/s10470-026-02642-x","DOIUrl":"10.1007/s10470-026-02642-x","url":null,"abstract":"<div><p>In this paper, different (diffusion, flicker, and generation recombination (G-R)) noises are studied and analyzed for triple material gate (TMG), double material gate (DMG) and single material gate (SMG) step FinFET devices and compared their performances in terms of ON current, OFF current, threshold voltage (V<sub>th</sub>), subthreshold swing (SS), and analog/RF performance. Using suitable gate material improves the SS, I<sub>ON,</sub> and I<sub>ON/OFF</sub> characteristics in the presence of noise. The drain current noise spectral density (S<sub>id</sub>) performance is measured and studied for all structures and compared to other existing devices. It is observed that the TMG step FinFET device has an improved S<sub>id</sub> value of 4.60*10<sup>–15</sup> A<sup>2</sup>/Hz performance in the presence of G-R noise. Moreover, this dissertation also reported that TMG step FinFET device with flicker noise is noticed to be significant to obtained peak values of analog/RF parameters such as transconductance (G<sub>m</sub>) of 11.74 mS, transconductance generation factor (TGF) 35.11 V<sup>−1</sup>, transconductance frequency product (TFP) of 290 THz/V, and cut-off frequency (F<sub>t</sub>) of 33.84 GHz respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148871709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and implementation of power management integrated circuit for next-generation SoCs with energy optimization and thermal protection in SCL-180 nm CMOS technology 基于scl - 180nm CMOS技术的下一代soc电源管理集成电路的设计与实现，具有能量优化和热保护功能

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-09-02 DOI: 10.1007/s10470-026-02649-4

Bapuji Banothu, Venkata Krishna Odugu, Harish Babu Gade

{"title":"Design and implementation of power management integrated circuit for next-generation SoCs with energy optimization and thermal protection in SCL-180 nm CMOS technology","authors":"Bapuji Banothu, Venkata Krishna Odugu, Harish Babu Gade","doi":"10.1007/s10470-026-02649-4","DOIUrl":"10.1007/s10470-026-02649-4","url":null,"abstract":"<div><p>The current study emphasises the schematic-level design and mixed-signal system-level validation of an innovative PMIC architecture developed using the Semiconductor Laboratory (SCL) 180 nm CMOS manufacturing technology. The suggested architecture incorporates a thorough multi-level approach to energy optimisation to address the particular constraints of engineering power blocks on a single chip for advanced SoCs. The architecture has a transistor-level Current-Mode Bandgap Reference (CMBGR), six channel Low Dropout Regulators (LDOs), and an incorporated thermal shutdown block. It also has behaviourally modelled Switched Mode Power Supplies (SMPS) that include Synchronous Buck and Boost regulators. The pre-layout schematic simulations show that the suggested CMBGR architecture gives a very stable 1.2 V reference with a temperature coefficient of 0.36 ppm/°C in an industrial temperature range from − 40 °C to 125 °C. The PSRR is 154 dB. The six LDO channels each give a regulated output of 1.8 V, with a dropout voltage of 500 mV and a PSRR of 66 dB. The synchronous Buck converters, whose designs were tested with verilog-A behavioural models, allow DVFS for the CPU core, several conventional DDR memory, and I/O voltage levels that can be changed. The built-in TSD block makes sure that the system shuts down safely at 150 °C.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"129 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148871712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a GDI-based low-power approximate multiplier for Gaussian image denoising using FinFET technology 基于gdi的低功耗近似乘法器的设计，用于使用FinFET技术去噪高斯图像

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-08-29 DOI: 10.1007/s10470-026-02640-z

Yakama Ravikiran Varma, J. Chinna Babu

{"title":"Design of a GDI-based low-power approximate multiplier for Gaussian image denoising using FinFET technology","authors":"Yakama Ravikiran Varma, J. Chinna Babu","doi":"10.1007/s10470-026-02640-z","DOIUrl":"10.1007/s10470-026-02640-z","url":null,"abstract":"<div><p>The increasing development of portable and power-sensitive devices has raised the need for high-performance and energy-efficient circuits, especially in image processing applications that deal with huge datasets and require a substantial amount of resources. CMOS technology makes conventional digital multipliers and adders, which are made for precise calculations, more compact, but they still often have large leakage currents and high power consumption. FinFET technology tackles many of these issues by reducing leakage power and providing greater control over short-channel effects. Even FinFET-based accurate arithmetic units struggle to strike a balance between computational accuracy and energy efficacy in applications that allow for some error tolerance. This article focuses on designing a low-power approximate multiplier based on Gate Diffusion Input (GDI) compressors (LAMGDIC) FinFET technology, specifically to tackle image denoising. The approximate design uses XNOR-GDI compressors, which allow the implementation of controlled approximations by simplifying certain bit positions to gain an advantage in power decrease at the expense of some accuracy when performing the computations. This approach reduces transistor count, switching activity, and leakage power, which are crucial for low-energy operation. The proposed multiplier has been integrated into a Gaussian kernel filter, a common image denoising technique, to demonstrate its effectiveness. The proposed method achieves 7.8125 × 10<sup>− 05</sup> of NMED, 0.0103 of MRED, 0.2300 <span>( mu W )</span> of power, 0.0480ns of delay, and 0.0110fJ of PDP. The LAMGDIC-based approximate multiplier in FinFET technology offers a better trade-off among accuracy and energy to be used for image denoising due to its reduced transistor count, low leakage, and better power, delay, and PDP.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148838407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electron radiation-induced device degradation in commercial SiC Power MOSFETs 商用SiC功率mosfet中电子辐射诱导的器件退化

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-08-29 DOI: 10.1007/s10470-026-02643-w

Tamana Baba, Fatihah Assyira bt Mohd Bakri, Abdullah Üzüm, Mehmet Turhal, Norazlina Saidin, Nurul Fadzlin Hasbullah

引用次数: 0