Analog Integrated Circuits and Signal Processing最新文献_第3页

An efficient wireless sensor node for autonomous sensing in the ISM band 一种用于ISM波段自主传感的高效无线传感器节点

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-08 DOI: 10.1007/s10470-025-02497-8

Naveed, Jeff Dix

{"title":"An efficient wireless sensor node for autonomous sensing in the ISM band","authors":"Naveed, Jeff Dix","doi":"10.1007/s10470-025-02497-8","DOIUrl":"10.1007/s10470-025-02497-8","url":null,"abstract":"<div>This paper presents a radio frequency powered wireless sensor node (WSN) implemented in 22-nm FD-SOI technology, designed for autonomous operation in the ISM band. The sensor node harvests energy from a dedicated 915 MHz radio frequency (RF) source and generates a 2.44 GHz carrier signal for data transmission. The proposed design integrates a high-efficiency RF rectifier utilizing ultra-low-power diode-based rectification and SOI MOSFET back-plate connections, enhancing energy conversion efficiency and sensitivity. A nanowatt-level power management unit (PMU) ensures stable operation with minimal power overhead. The wireless transmission module employs a DLL-based XOR frequency synthesizer with an improved duty cycle correction circuit, achieving low-power, high-precision RF carrier generation. Operating at an RF input power sensitivity as low as − 25 dBm, the WSN can function effectively up to 12 m from the power source. Experimental results demonstrate a peak power conversion efficiency (PCE) of 57% at − 14 dBm and 28% at − 25 dBm, with a maximum input tolerance of 0 dBm to prevent device breakdown. Using On–Off Keying (OOK) modulation, the transmitter outputs − 3.8 dBm power with 55% power efficiency via a switching power amplifier. The synthesizer and power amplifier consume 160 µW and 500 µW, respectively. Occupying a 0.17 mm2 active die area, this design offers an area-efficient, sustainable, and cost-effective solution for diverse remote sensing applications.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1.2–6.6 GHz Sub-sampling PLL with adaptive pulse width match achieving 216 fs rms jitter and − 71.90 dBc reference spurs 具有自适应脉宽匹配的1.2-6.6 GHz子采样锁相环，实现216 fs rms抖动和- 71.90 dBc参考杂散

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-08 DOI: 10.1007/s10470-025-02485-y

Xiang Cheng, Baolin Wei, Xueming Wei, Weilin Xu, Hongwei Yue

{"title":"A 1.2–6.6 GHz Sub-sampling PLL with adaptive pulse width match achieving 216 fs rms jitter and − 71.90 dBc reference spurs","authors":"Xiang Cheng, Baolin Wei, Xueming Wei, Weilin Xu, Hongwei Yue","doi":"10.1007/s10470-025-02485-y","DOIUrl":"10.1007/s10470-025-02485-y","url":null,"abstract":"<div>With the demands for different rates of serial data received and transmitted in a communication system, an adaptive bandwidth sub-sampling phase-locked loop (AB-SSPLL) was designed. To maintain the bandwidth of the AB-SSPLL varying with the reference clock frequency, a self-biasing adaptive pulse width matching technique was introduced to the proposed AB-SSPLL. It adaptively adjusts the gain of the sub-sampling charge pump to maintain a constant ratio of the loop bandwidth to the reference clock frequency. The proposed AB-SSPLL has the advantages of broad bandwidth and low jitter. The AB-SSPLL is designed using a 40 nm COMS process and has an area of 0.21 × 0.26 mm2. The simulation results show that the phase-locked loop tuning range is 1.2–6.6 GHz, the root mean square jitter of the output clock is 312.3 fs@1.2 GHz and 216.3 fs@6.6 GHz, and the reference spurious is -71.90 dBc@1.2 GHz and − 61.39 dBc@6.6 GHz, respectively, and the jitter performance of ring-VCO-based AB-SSPLL can be comparable to that of the LC-VCO-based PLL.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Power FIR filter pruning using secretary bird optimization for Hardware-Efficient signal processing 低功耗FIR滤波器剪枝利用秘书鸟优化硬件高效的信号处理

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-05 DOI: 10.1007/s10470-025-02490-1

G. Theivanathan, C. Murukesh

{"title":"Low-Power FIR filter pruning using secretary bird optimization for Hardware-Efficient signal processing","authors":"G. Theivanathan, C. Murukesh","doi":"10.1007/s10470-025-02490-1","DOIUrl":"10.1007/s10470-025-02490-1","url":null,"abstract":"<div>This paper proposes an efficient Finite Impulse Response (FIR) filter design using a novel pruning technique optimized with the Secretary Bird Optimization (SBO) algorithm. The key novelty lies in the introduction of a customized multi-objective cost function that integrates coefficient significance, power consumption, delay, and area, enabling hardware-aware pruning decisions. Unlike standard SBO applications, the algorithm is adapted for FIR filter design by dynamically balancing exploration and exploitation phases through a feedback coefficient mechanism. The proposed method effectively identifies and eliminates less significant filter components to reduce complexity without compromising performance. Implementation results demonstrate substantial improvements: up to 30.5% reduction in power, 35% reduction in delay, 21.1% decrease in area, and up to 63.4% reduction in area-delay product across different filter tap sizes. These results validate the proposed approach as a scalable and energy-efficient solution for digital signal processing applications, particularly suitable for low-power VLSI systems.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144990495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Heterojunction (SiGe/Si) triple metal dual gate extended source tunnel FET for improved DC, noise and linearity performance 异质结（SiGe/Si）三金属双栅极扩展源隧道场效应管，改善了直流、噪声和线性性能

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-04 DOI: 10.1007/s10470-025-02492-z

Sheetal Singh, Subodh Wairya

{"title":"Heterojunction (SiGe/Si) triple metal dual gate extended source tunnel FET for improved DC, noise and linearity performance","authors":"Sheetal Singh, Subodh Wairya","doi":"10.1007/s10470-025-02492-z","DOIUrl":"10.1007/s10470-025-02492-z","url":null,"abstract":"<div>In this paper, a 2-D model of a hetero-triple metal dual gate extended source tunnel FET (TMDG-ES-TFET) is analyzed. The device features a heterojunction (HJ) designed by silicon germanium (SiGe) and Si materials in the source-channel junction and a hetero-dielectric gate stack (GS) using dielectric as silicon dioxide (SiO2) and hafnium dioxide (HfO2). In this research, the DC characteristics, linearity, and noise performance have been investigated. In structure the entire source region over the oxide layer has been overlapped by three distinct metals with various work functions. The paper has also investigated the impact of increasing source width (80 nm and 120 nm) over the channel. The SiGe is used as a source thereby improving the ION/IOFF value and threshold voltage (Vth). The structure has a greater ION/IOFF reflected as 9.1 × 1012, a lower sub-threshold value of 41 mV/decade, and a lower Vth of 0.58 V. A standardized SILVACO technology computer aided design (TCAD) is used for the simulation. Additionally, the linearity analysis was performed as a figure of merit (FOM) for a device under investigation, taking into account various parameters like 1db compression point, 2nd and 3rd -order voltage intercept points (VIP2 and VIP3), the 3rd -order intermodulation distortion point (IMD3), and the third order intermodulation intercept point (IIP3).</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144990494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance analysis of SiGe source based heterojunction TFET biosensor for improved sensitivity 基于SiGe源的异质结TFET生物传感器的性能分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-01 DOI: 10.1007/s10470-025-02479-w

Irfan Ahmad Pindoo, Sanjeet Kumar Sinha, Sweta Chander

{"title":"Performance analysis of SiGe source based heterojunction TFET biosensor for improved sensitivity","authors":"Irfan Ahmad Pindoo, Sanjeet Kumar Sinha, Sweta Chander","doi":"10.1007/s10470-025-02479-w","DOIUrl":"10.1007/s10470-025-02479-w","url":null,"abstract":"<div>This work presents a novel SiGe-source-based heterojunction tunnel field-effect transistor (TFET) biosensor that incorporates a nanogap dielectric cavity beneath the gate and a hetero-dielectric BOX (HDBOX) structure for ultra-sensitive, label-free detection of both neutral and charged biomolecules. The proposed device architecture leverages a low-bandgap SiGe source to enhance band-to-band tunneling (BTBT) efficiency and utilizes dielectric modulation in the nanogap cavity to enable electrostatic coupling with immobilized biomolecules. The sensor exploits distinct detection mechanisms—dielectric constant variation for neutral biomolecules and combined dielectric and charge-field modulation for charged species—thereby achieving a comprehensive detection capability. Extensive TCAD simulations, calibrated against experimental TFET data, were conducted using Kane’s BTBT model, Lombardi mobility, Fermi–Dirac statistics, and SRH recombination, under room temperature conditions. The device demonstrates a high ON/OFF current ratio of 1.947 × 108, a steep subthreshold slope of 28.57 mV/decade, and a maximum current-based sensitivity (SID) of 1.548 × 108 for a dielectric modulation range of κ = 1 to 26. Compared to state-of-the-art DM-TFET and PNPN-TFET biosensors, the proposed design exhibits significantly improved sensitivity, lower off-state leakage (~ 10–14 A), and reduced process complexity. While this study is simulation-based, the device structure employs CMOS-compatible materials and fabrication techniques, paving the way for future experimental validation. These results position the HDBOX TFET biosensor as a promising candidate for real-time, low-power, and label-free biomedical diagnostics.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144926954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

65.35 nW three-stage charge pump circuit based on swapped body biasing approach 基于交换体偏置方法的65.35 nW三级电荷泵电路

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-09-01 DOI: 10.1007/s10470-025-02483-0

Ricky Rajora, Kulbhushan Sharma

引用次数: 0

Impact of the external gate resistance on the power CoolMOS transistor transient switching dynamics 外栅极电阻对功率型CoolMOS晶体管瞬态开关动力学的影响

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-28 DOI: 10.1007/s10470-025-02487-w

Sara Laafar, Najib Boumaaz, Abdelhadi Elbacha, Badredine Lamuadni, Asmaa Maali, Abdallah Soulmani

引用次数: 0

A novel FPGA-based hybrid cryptographic architecture integrating hummingbird and PRESENT ciphers with signal processing techniques for enhanced security in resource-constrained IoT devices 一种新型的基于fpga的混合加密架构，将蜂鸟和PRESENT密码与信号处理技术集成在一起，以增强资源受限物联网设备的安全性

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-28 DOI: 10.1007/s10470-025-02484-z

V. Parthiban, J. Raja

{"title":"A novel FPGA-based hybrid cryptographic architecture integrating hummingbird and PRESENT ciphers with signal processing techniques for enhanced security in resource-constrained IoT devices","authors":"V. Parthiban, J. Raja","doi":"10.1007/s10470-025-02484-z","DOIUrl":"10.1007/s10470-025-02484-z","url":null,"abstract":"<div>This paper presents a novel hybrid cryptographic framework combining the Hummingbird and PRESENT ciphers, optimized for FPGA implementation to secure resource-constrained IoT devices. The design addresses the critical need for lightweight, energy-efficient encryption that supports real-time data protection in environments with limited computational power and strict energy budgets. By integrating signal processing algorithms, the framework optimizes data flow, reduces latency, and enables efficient encryption and decryption operations. Leveraging FPGA’s parallelism and customizable hardware, the architecture achieves high throughput and low power consumption. The system’s performance is evaluated through key metrics including encryption speed, energy usage, and resilience against cryptanalytic attacks. Experimental results demonstrate a 25% reduction in latency and notable energy savings compared to existing solutions, without compromising security. The proposed framework is compact, adaptable, and suitable for deployment in diverse IoT applications where resource efficiency and strong security are essential. This work provides a practical and innovative approach to enhancing cryptographic protocols for next-generation IoT devices, meeting the dual objectives of robust protection and efficient hardware implementation.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An analog ReLu-based decision tree circuit architecture for biomedical applications 一种生物医学应用的基于模拟relu的决策树电路结构

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-28 DOI: 10.1007/s10470-025-02481-2

Vassilis Alimisis, Vasileios Moustakas, Konstantinos Cheliotis, Anna Mylona, Paul P. Sotiriadis

{"title":"An analog ReLu-based decision tree circuit architecture for biomedical applications","authors":"Vassilis Alimisis, Vasileios Moustakas, Konstantinos Cheliotis, Anna Mylona, Paul P. Sotiriadis","doi":"10.1007/s10470-025-02481-2","DOIUrl":"10.1007/s10470-025-02481-2","url":null,"abstract":"<div>This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956 nW and operates on low supply rails of 0.6 V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding (91.30%). The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90 nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02481-2.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultra-Low Power and High-Speed Design Analysis of 1-Bit 20T-HyDGFA using a Dual-Gate Domino Inverter 1位20T-HyDGFA超低功耗高速设计分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-22 DOI: 10.1007/s10470-025-02470-5

Ramsha Suhail, Pragya Srivastava, Richa Yadav, K. Pradnya, Ridhima Choudhary, Priya Singh, Prachi Yadav

{"title":"Ultra-Low Power and High-Speed Design Analysis of 1-Bit 20T-HyDGFA using a Dual-Gate Domino Inverter","authors":"Ramsha Suhail, Pragya Srivastava, Richa Yadav, K. Pradnya, Ridhima Choudhary, Priya Singh, Prachi Yadav","doi":"10.1007/s10470-025-02470-5","DOIUrl":"10.1007/s10470-025-02470-5","url":null,"abstract":"<div>In the age of fast digital communication, the use of portable devices is significantly increasing. Given their compact size, it is essential for these devices to fulfill the technological requirements of reduced power consumption, minimal area, and high speed. The 1-bit full adder cell is a critical functional unit in the computational industry. This paper presents a new hybrid methodology for designing 20 transistor full adder (FA) based on Double Gate MOSFET (20T-HyDGFA). The proposed circuit is designed to optimize the balance between propagation delay (Td) and power consumption (PWR), therefore enhancing efficiency in the IC sector. This study compares the proposed circuit with existing FA circuits and measures numerous performance metrics, including Td, PWR, Power Delay Product (PDP), Energy Delay Product (EDP), Energy-Delay² Product (ED2P), and noise margin. Operated at a supply voltage (VDD) of 0.5 V, the proposed design exhibits a notably low PWR of 0.98nW (1.18x), with a remarkably short Td of 19.30ps (20.63x), accompanied by a substantial PDP of 0.02 aJ (24.22x), EDP of 0.36 aJ-ns (500.22x) and ED2P of 6.21 aJ-ps2 (1150x) as simulated on HSPICE software at a 16 nm technology node. A detailed, Monte Carlo Simulation is conducted for the proposed FA circuit to validate the obtained results and then compared with the existing best state-of-the-art FA circuits. Furthermore, this paper introduces an application, 4-Bit Ripple Carry Adder (RCA), using the proposed 20T-HyDGFA Circuit (4-HyDGRCA). The physical layout design is facilitated by the enhanced results, which occupy an optimized area of 9.3µm2 and 41.9 µm2 for the proposed circuit and proposed application circuit, respectively.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0