Analog Integrated Circuits and Signal Processing最新文献_第3页

Improvement of conversion cycle and estimation of capacitor mismatch in hybrid analog-to-digital converters using flash and successive approximation register 利用闪存和逐次逼近寄存器改进模数混合转换器的转换周期和估计电容失配

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-11 DOI: 10.1007/s10470-025-02471-4

Ryukichi Hirai, Ryo Kishida, Tatsuji Matsuura, Akira Hyogo

{"title":"Improvement of conversion cycle and estimation of capacitor mismatch in hybrid analog-to-digital converters using flash and successive approximation register","authors":"Ryukichi Hirai, Ryo Kishida, Tatsuji Matsuura, Akira Hyogo","doi":"10.1007/s10470-025-02471-4","DOIUrl":"10.1007/s10470-025-02471-4","url":null,"abstract":"<div><p>This paper presents hybrid 8-bit analog-to-digital converter (ADC) architectures that consists of flash ADC and successive approximation register (SAR) ADC. We have proposed the hybrid flash-SAR ADC consisting of 4-bit flash ADC and 3-trit radix-3 SAR ADC to improve conversion speed. It is called flash-radix-3-SAR ADC. The proposed ADC consists of the 3-bit flash ADC, 1-trit radix-3 SAR ADC and 4-bit two-bit/cycle SAR ADC to reduce the number of bit in the flash ADC. It is called flash-hybrid-SAR ADC. The proposed flash-hybrid-SAR ADC can reduce by half the number of resistors and comparators in the flash ADC from the conventional 8-bit hybrid flash-radix-3-SAR ADC with the same sampling rate at 142.8 MS/s. The proposed circuit is validated through transient simulations and capacitor mismatch analysis. The results confirm 8-bit resolution with DNL (Differential non-linearity) and INL (Integral non-linearity) within ±1.0 LSB and ±0.5 LSB, respectively. The circuits also maintain stable performance under ±0.5% capacitor mismatch conditions.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02471-4.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144814412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cyclic memory: a low-latency, single-buffer technique for FMCW LiDAR interleaving/de-interleaving 循环存储器：用于FMCW激光雷达交错/去交错的低延迟单缓冲区技术

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-11 DOI: 10.1007/s10470-025-02476-z

O. S. Hafez, O. A. Abouelfetouh, Y. O. Mohamed, M. N. Hasaneen, O. H. Fathy, Y. H. Hassan, M. M. Mahroos, R. A. Elomda, M. M. Ghouneem

{"title":"Cyclic memory: a low-latency, single-buffer technique for FMCW LiDAR interleaving/de-interleaving","authors":"O. S. Hafez, O. A. Abouelfetouh, Y. O. Mohamed, M. N. Hasaneen, O. H. Fathy, Y. H. Hassan, M. M. Mahroos, R. A. Elomda, M. M. Ghouneem","doi":"10.1007/s10470-025-02476-z","DOIUrl":"10.1007/s10470-025-02476-z","url":null,"abstract":"<div><p>Pipelined systems have long proven their efficiency in high-throughput data processing by enabling concurrent execution of sequential tasks. However, a recurring challenge in such systems is the mismatch between order of data generation and consumption across pipeline stages. This problem imposes a critical constraint: the system must collect new data block while simultaneously reorganizing previously acquired data block–all without interrupting pipeline throughput. A ping-pong buffer allows a system to do so by doubling buffering memory size. This idea increases memory data throughput by not halting the pipeline operation. This paper presents a memory read/write algorithm called “Cyclic Memory” as an alternative to the ping-pong buffering algorithm for the data interleaving/de-interleaving process. Unlike the ping-pong buffering algorithm, the cyclic memory algorithm does not require double buffering. This means that cyclic memory cuts memory requirements in half, uses less area, and consumes less power. This paper will discuss the derivation of the algorithm as well as its implementation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144814410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A cross-coupled wideband low-phase-noise VCO in 130 nm CMOS using a linear I-MOS varactor 采用线性I-MOS变容管的130 nm CMOS交叉耦合宽带低相位噪声压控振荡器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-11 DOI: 10.1007/s10470-025-02472-3

Samad Jamali, Mehdi Ehsanian

引用次数: 0

Efficient address generator architectures for IEEE 802.16e WiMAX deinterleaver based on SPAM approach 基于SPAM方法的IEEE 802.16e WiMAX脱交织器的高效地址生成器体系结构

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-08-11 DOI: 10.1007/s10470-025-02477-y

Vivek Karthick Perumal, Ramesh Jayabalan, Thiruvenkadam Krishnan, Dhanasekaran Selvaraj

{"title":"Efficient address generator architectures for IEEE 802.16e WiMAX deinterleaver based on SPAM approach","authors":"Vivek Karthick Perumal, Ramesh Jayabalan, Thiruvenkadam Krishnan, Dhanasekaran Selvaraj","doi":"10.1007/s10470-025-02477-y","DOIUrl":"10.1007/s10470-025-02477-y","url":null,"abstract":"<div><p>This paper presents a VLSI implementation of a Synchronous Pipelined Array Multiplier (SPAM)-based address generation architecture designed for a WiMAX deinterleaver. The proposed design enhances throughput and reduces latency by adding parallelism within the array multiplier, specifically designed for efficient WiMAX deinterleaver. The architecture maintains synchronization with WiMAX operations and focuses on low power consumption, making it compatible for integration into energy-efficient systems. Simulation results demonstrate superior performance in terms of speed, power efficiency, and throughput, highlighting the architecture's suitability for high-performance WiMAX systems, particularly in wireless broadband communication. The proposed SPAM-based address generator is 58% and 18% faster than LUT-based and MUX-based systems, respectively. It also achieves 45% and 15% lower power consumption, respectively. Implemented in 45 nm CMOS technology, the proposed multiplier better performs the LUT-based architecture in Power-Delay Product (PDP) and Area-Delay Product (ADP) by 71% and 37%, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144814409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance improvement in asynchronous binary search ADC using bootstrapped sample and hold circuit & 2-stage ladder network 采用自举采样保持电路和两级阶梯网络的异步二进制搜索ADC的性能改进

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-27 DOI: 10.1007/s10470-025-02419-8

Anurag Pandey, Kashi Bandla, Dipankar Pal, Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami

{"title":"Performance improvement in asynchronous binary search ADC using bootstrapped sample and hold circuit & 2-stage ladder network","authors":"Anurag Pandey, Kashi Bandla, Dipankar Pal,  Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami","doi":"10.1007/s10470-025-02419-8","DOIUrl":"10.1007/s10470-025-02419-8","url":null,"abstract":"<div><p>This paper presents a design of an 8-bit asynchronous, binary search analog-to-digital converter (ADC) using an asynchronously generated clock signal and inbuilt Bootstrapped sample and hold circuit by utilizing a 2-stage ladder for generation of reference voltages. The proposed design utilizes an anti-aliasing filter and Bootstrapped sample and hold circuit for charge cancellation with only N comparators, <span>(2^{(N-3)})</span> multiplexers, and a switching network. The ADC achieves an SNR of 47.4 dB, an ENOB of 7.7 bits, <span>(text {f}_{in})</span> of 200 KHz, <span>(text {f}_{s})</span> of 125 MSPS, and dissipates 13 mW of power when operated on 1.8 V supply rail. The proposed design had resulted in saving 10<span>(%)</span> of chip area with respect to a recent candidate SAR ADC and more than 50<span>(%)</span> of chip area with respect to flash ADC. The proposed design also showed 61.7<span>(%)</span> improvement in speed with respect to existing SAR architectures due to switching networks. Pre and post-layout simulation results showed a conversion time of approximately 5.2 ns and 6.5 ns respectively, while Monte Carlo simulation and process corner analysis showed good results with less spread. Further, the static characteristics that have been plotted for resistor mismatch showed linearity approximation in the nominal range. The design has the merit of being that choice for radio frequency identification applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02419-8.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144140163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high speed-low power compressor with novel structure for reducing the complexity of wallace multipliers 为降低华莱士乘法器的复杂度，设计了一种结构新颖的高速低功率压缩机

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-27 DOI: 10.1007/s10470-025-02435-8

J Suresh Babu, G. Saravana Kumar

{"title":"A high speed-low power compressor with novel structure for reducing the complexity of wallace multipliers","authors":"J Suresh Babu, G. Saravana Kumar","doi":"10.1007/s10470-025-02435-8","DOIUrl":"10.1007/s10470-025-02435-8","url":null,"abstract":"<div><p>Nowadays power, delay in addition to the area has to turn out to be the attribute features of any VLSI circuit. Usually, the delay of usual multipliers is high due to the number of computations, consequently; the overall speed of circuits become less, and increases power consumption. The performance of Digital Signal Processing (DSP) processors is frequently dependent on the Multiplier and Accumulator (MAC) unit, and three parameters determine it, namely power, area and speed. However, the performance of the conventional MAC is not good when the number of bits increases and also using several multiplication factors increases the power consumption. So, to reduce the compressor size for working with a higher level of bits in lower power and low area consumption, this paper proposes a new architecture for an effective MAC unit. In the proposed architecture, the Peres logic gates are applied in the third compression stage for reducing the power compression and delay. The outcomes demonstrate that the suggested design has high speed and low MAC unit area consumption. Furthermore, the increase in the compressor size is not affecting the system operations. The proposed architecture can be applied for future DSP system to get efficient performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144140165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of electrical parameters in extended source epitaxial layer DG-TFET including interface trap charges and temperatures 扩展源外延层DG-TFET的电学参数研究，包括界面陷阱电荷和温度

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-26 DOI: 10.1007/s10470-025-02428-7

Rajesh Saha, Shridev Devji, Shanidul Hoque, Brinda Bhowmick, Srimanta Baishya

{"title":"Investigation of electrical parameters in extended source epitaxial layer DG-TFET including interface trap charges and temperatures","authors":"Rajesh Saha, Shridev Devji, Shanidul Hoque, Brinda Bhowmick, Srimanta Baishya","doi":"10.1007/s10470-025-02428-7","DOIUrl":"10.1007/s10470-025-02428-7","url":null,"abstract":"<div><p>In this work, we have highlighted the electrical parameters of extended source epitaxial layer double gate TFET (ESETL-DGTFET) for the wide variation in temperatures and interface trap charge density. The DC, RF/analog, and linearity behaviour are reported for variation in positive interface trap charge (PITC)/ negative interface trap charge (NITC) along with wide temperature variations (250–400) K using TCAD simulator. It is seen that PITC improved the electrical parameters like current ratio, cut-off frequency, linearity behaviour, whereas, NITC degrades the same. The degradation in OFF state current at low gate bias with increased temperature is due SRH rate is exponentially dependent on temperature, whereas, band to band tunnelling (BTBT) rate is weak dependence of temperature leads to negligible variation in drain current at high gate bias. With increased temperature, the current ratio degrades and delay improved for both PITC and NITC. The temperature sensitivity is improved in presence of PITC compared to NITC.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144135466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A subthreshold CMOS voltage reference with low temperature coefficient, low power and high PSRR 具有低温系数、低功耗和高PSRR的亚阈值CMOS电压基准

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02421-0

Shubing Wan, Hua Wu, Jiawei Cheng, Xianguo Cao

引用次数: 0

A novel architecture for high-performance PWM class-D audio amplifier 一种新型的高性能PWM d类音频放大器结构

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02422-z

Ahmad Karimi, Abdalhossein Rezai, Mohammad Mahdi Hajhashemkhani, Javad Sadeghi Azizkhani

引用次数: 0

Majority voting for low power and low complexity preamble detection by hybrid memristor-CMOS architecture 基于记忆电阻器- cmos混合结构的低功耗低复杂度前置检测

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-05-21 DOI: 10.1007/s10470-025-02413-0

Ehsan Kalanaki, Behzad Ebrahimi, Mohammad Ali Pourmina

{"title":"Majority voting for low power and low complexity preamble detection by hybrid memristor-CMOS architecture","authors":"Ehsan Kalanaki, Behzad Ebrahimi, Mohammad Ali Pourmina","doi":"10.1007/s10470-025-02413-0","DOIUrl":"10.1007/s10470-025-02413-0","url":null,"abstract":"<div><p>In modern embedded systems, efficient and low-power communication is essential, especially as these systems increasingly handle concurrent wireless protocols. Preamble detection is a critical step in synchronizing received signals after demodulation, yet traditional methods—such as correlation and Hamming distance techniques—suffer from high power consumption and computational complexity. To address these challenges, this paper proposes a novel majority voting-based pattern recognition method that enhances detection accuracy while reducing energy consumption. By leveraging majority voting, our approach mitigates noise effects and improves signal robustness, enabling more efficient preamble detection across varying signal-to-noise ratios (SNRs). The proposed method is implemented in both CMOS-based and hybrid memristor-CMOS architectures, where the hybrid design incorporates dedicated complementary circuits to further optimize power efficiency and reduce silicon area utilization. Unlike conventional CMOS-only implementations, our hybrid approach reduces redundant computations and enhances energy efficiency, making it well-suited for resource-constrained applications. Performance evaluation demonstrates significant improvements over existing techniques, highlighting the potential of memristor-CMOS hybrid technology in low-power, high-speed communication systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144108493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0