Analog Integrated Circuits and Signal Processing最新文献

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An ultra-low power fully CMOS sub-bandgap reference in weak inversion 弱反相超低功率全 CMOS 亚带隙基准器件
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-15 DOI: 10.1007/s10470-024-02289-6
Reza Mohammadi Nowruzabadi, Javad Mostofi Sharq, Emad Ebrahimi
{"title":"An ultra-low power fully CMOS sub-bandgap reference in weak inversion","authors":"Reza Mohammadi Nowruzabadi,&nbsp;Javad Mostofi Sharq,&nbsp;Emad Ebrahimi","doi":"10.1007/s10470-024-02289-6","DOIUrl":"10.1007/s10470-024-02289-6","url":null,"abstract":"<div><p>This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 2-3","pages":"173 - 182"},"PeriodicalIF":1.2,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141647923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Secure and reliable communication using memristor-based chaotic circuit 利用基于忆阻器的混沌电路实现安全可靠的通信
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-13 DOI: 10.1007/s10470-024-02278-9
Usha Kumari, Rekha Yadav
{"title":"Secure and reliable communication using memristor-based chaotic circuit","authors":"Usha Kumari,&nbsp;Rekha Yadav","doi":"10.1007/s10470-024-02278-9","DOIUrl":"10.1007/s10470-024-02278-9","url":null,"abstract":"<div><p>This research paper demonstrates behavior of memristor emulator circuit at various input frequencies. It is a critical circuit having a vast potential for constructing digital and analog circuits, FM-to-AM converters, filters, cellular neural networks, sensors, analog circuits, and chaotic oscillators are all designed with memristor circuits. It has some unique properties such as nonlinear behaviour, analog signal processing, adaptive and reconfigurable system, memory and state retention and also high density and low power consumption. These properties build the communication system more reliable secure and more efficient. To enhance the design of the memristor model, implementation doing using analog multiplier and operational transconductance amplifier with a constant transcoductance gain is employed. In addition to the input supply voltage frequency (f) and amplitude (Vm), the operational transconductance amplifier provides a control parameter known as the transconductance (gm). Modifications in amplitude have an impact on memory resistance, and variations in biassing voltage influence transconductance (gm) of OTA. The research shows memristor-based chaotic circuit use for secure transmission system. The operational frequency that exhibits the maximum value is 10 kilohertz, accompanied by a power dissipation of 24.1 microwatts with noise <span>(51.9text{ nV}/{text{Hz}}^{1/2})</span> at room temperature. This study employs a circuit electronic design automation (EDA) tool to demonstrate the behavior of a memristor circuit under varying input conditions.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 2-3","pages":"155 - 171"},"PeriodicalIF":1.2,"publicationDate":"2024-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141611960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quad ports flexible MIMO antenna with connected ground and high isolation for UWB applications 用于 UWB 应用的四端口柔性 MIMO 天线,具有连接地线和高隔离度功能
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-09 DOI: 10.1007/s10470-024-02280-1
Heba Aboelleil, Ashraf A. M. Khalaf, Ahmed A. Ibrahim
{"title":"Quad ports flexible MIMO antenna with connected ground and high isolation for UWB applications","authors":"Heba Aboelleil,&nbsp;Ashraf A. M. Khalaf,&nbsp;Ahmed A. Ibrahim","doi":"10.1007/s10470-024-02280-1","DOIUrl":"10.1007/s10470-024-02280-1","url":null,"abstract":"<div><p>This study proposes a flexible MIMO antenna with improved isolation and connected ground designed on a flexible substrate that makes it compatible with various shapes and surfaces, including curved, irregular, or non-planar structures. The suggested single unit consists of a slotted rectangular radiator on the front layer with a partial ground connected to a circular stub on the other side. As well it is created on a flexible substrate (Rogers RO3003) that has a dielectric constant (ε<sub>r</sub>) of 3 and a thickness of 1.52 mm. The Four copies of the single unit with orthogonal orientation are added to improve the system performance. The antenna units are connected through their ground to introduce the connected ground antenna. The size of the proposed design is compact (50 × 50 × 1.524 mm<sup>3)</sup>. The simulating and testing results demonstrate that the antenna operates within a frequency range of 3–12 GHz and achieves a high isolation of ≥ 17 dB over most frequency range. The MIMO parameters and the radiation patterns are analyzed to evaluate the performance of the MIMO antenna. Finally, the four elements of the flexible antenna are fabricated and tested under flat and bending conditions. The simulation and testing results demonstrate that the suggested design exhibits excellent performance, such as broad bandwidth, high isolation, simple structure, and decreased correlation coefficient, which suggest it for the UWB applications and its flexibility allows it for integration into a wide range of devices, such as wearable technology, Internet of Things (IoT) devices, and curved surfaces of vehicles or aircraft.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"59 - 70"},"PeriodicalIF":1.2,"publicationDate":"2024-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and design of a GHz bandwidth adaptive bias circuit for an mmW Doherty amplifier 分析和设计用于毫米波 Doherty 放大器的 GHz 带宽自适应偏置电路
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-07 DOI: 10.1007/s10470-024-02288-7
Christian Elgaard, Henrik Sjöland
{"title":"Analysis and design of a GHz bandwidth adaptive bias circuit for an mmW Doherty amplifier","authors":"Christian Elgaard,&nbsp;Henrik Sjöland","doi":"10.1007/s10470-024-02288-7","DOIUrl":"10.1007/s10470-024-02288-7","url":null,"abstract":"<div><p>This paper derives theoretical results for adaptive bias in Doherty amplifiers and presents the design and measurements of an integrated adaptive bias circuit tailored for high peak-to-average high bandwidth signals. Fundamental equations for output power, impedance, and efficiency of the complete Doherty amplifier are derived. Even with ideal transistor models, the Doherty amplifier is fundamentally nonlinear due to saturation of the main amplifier and class-C nonlinearity of the auxiliary. Increasing the transconductance of the auxiliary amplifier mitigates the distortion. Adaptive bias offers the possibility to control the output current characteristic of the auxiliary amplifier. This means that adaptive bias linearises and mitigates the need for an oversized auxiliary amplifier. Both methods, transconductance scaling and adaptive bias, are analysed and compared as well as having a band limited adaptive bias signal. The design of a multiple GHz bandwidth adaptive bias circuit is presented. To verify the circuit design and the theoretical predictions, an mmW Doherty amplifier in 22 nm CMOS-FD-SOI, utilizing the presented adaptive bias circuit, is measured and compared with and without adaptive bias. Comparison is conducted both using continuous-wave and modulated high bandwidth signals. Measured results confirm the predicted improvements by the adaptive bias as derived by the theoretical analysis.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"39 - 58"},"PeriodicalIF":1.2,"publicationDate":"2024-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02288-7.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power frequency-programmable stimulation circuit for small rodent pacemaker 用于小型啮齿动物心脏起搏器的低功率频率可编程刺激电路
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-06 DOI: 10.1007/s10470-024-02282-z
Fanny Pan, Émilie Avignon-Meseldzija, AlBaraa Elhabab, Alban Todesco, Olaf Mercier, Delphine Mika, David Boulate, Frédéric Perros, Anthony Kolar
{"title":"A low power frequency-programmable stimulation circuit for small rodent pacemaker","authors":"Fanny Pan,&nbsp;Émilie Avignon-Meseldzija,&nbsp;AlBaraa Elhabab,&nbsp;Alban Todesco,&nbsp;Olaf Mercier,&nbsp;Delphine Mika,&nbsp;David Boulate,&nbsp;Frédéric Perros,&nbsp;Anthony Kolar","doi":"10.1007/s10470-024-02282-z","DOIUrl":"10.1007/s10470-024-02282-z","url":null,"abstract":"<div><p>This article presents the design of an integrated, frequency-programmable stimulation circuit dedicated to small rodents for the study of pulmonary arterial hypertension. A complete architecture of the stimulation circuit is proposed, based on in vivo tests that have led to the stimulation waveform specification. The circuit is designed using XFAB 0.18 µm technology. The adopted design methodology allows to reduce the power consumption of command blocks to the minimum. Post-layout simulation results shows that the pacing rate can be tuned from 450 to 600 beats per minute (bpm). The total power consumption of the stimulation circuit is 196.1 µW, with 186 µW directly consumed by the voltage multipliers, H-Bridge and pacemaker load, 10.1 µW by the kilohertz-range VCO driver, and only 8.4 nW by the ultra-low power command generator.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"125 - 139"},"PeriodicalIF":1.2,"publicationDate":"2024-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and simulation of a low-power, universal & multi-mode filter for the commercial FM band in 20-nm CNFETs 使用 20 纳米 CNFET 为商用调频频段设计和模拟低功耗、通用和多模滤波器
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-06 DOI: 10.1007/s10470-024-02287-8
S. Mohammadali Zanjani, Pouya Toghian
{"title":"Design and simulation of a low-power, universal & multi-mode filter for the commercial FM band in 20-nm CNFETs","authors":"S. Mohammadali Zanjani,&nbsp;Pouya Toghian","doi":"10.1007/s10470-024-02287-8","DOIUrl":"10.1007/s10470-024-02287-8","url":null,"abstract":"<div><p>This paper presents a new biquad filter based on carbon nanotube field-effect transistor (CNFET) technology. Implementing various filter modes (high-pass, low-pass, band-pass, and band-stop) in four operating modes (voltage, current, transconductance, and transresistance) with a unified circuit structure is the fundamental feature of the proposed filter. The proposed universal filter is intended for commercial radio communications in the FM band to reduce power consumption and chip area occupation. The proposed circuit can adjust a wide frequency range and thus cover multiple radio channels with minimum noise and distortion on the signal. The proposed filter in 20 nm technology has been simulated using advanced design system (ADS) software to investigate the effects of high-frequency effects. The minimum power consumption is 360 nW, with a supply voltage of 0.9 V, with the ability to independently adjust the center frequency (22 MHz &lt; f<sub>0</sub> &lt; 120 MHz) and filter quality factor (0.6 &lt; Q &lt; 23) and the use of grounded capacitors to absorb parasitic effects are among the advantages of the proposed circuit. The proposed Gm-C circuit has the highest figure of merit (FOM) value of 318.5. Moreover, its resistance to process variations, power supply, and temperature changes demonstrates the appropriate performance of the proposed filter.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"9 - 20"},"PeriodicalIF":1.2,"publicationDate":"2024-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of novel full-wave rectifier using second generation current conveyor (CCII) 利用第二代电流传输器 (CCII) 实现新型全波整流器
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-05 DOI: 10.1007/s10470-024-02279-8
Amit Agrawal, Amit Rai, Kulwant Singh, Ankita Bhatt, Ashish Shrivastava, Shubham Tiwari, Bidyut Mahato
{"title":"Implementation of novel full-wave rectifier using second generation current conveyor (CCII)","authors":"Amit Agrawal,&nbsp;Amit Rai,&nbsp;Kulwant Singh,&nbsp;Ankita Bhatt,&nbsp;Ashish Shrivastava,&nbsp;Shubham Tiwari,&nbsp;Bidyut Mahato","doi":"10.1007/s10470-024-02279-8","DOIUrl":"10.1007/s10470-024-02279-8","url":null,"abstract":"<div><p>This paper presents a unique full-wave rectifier designed with the help of second generation current conveyor (CCII) which is a promising building block to design the analog circuits. The proposed circuit is designed &amp; simulated on OrCAD/PSpice using key ICAD844 as CCII, manufactured by Analog Devices corporation. The simulated results are extracted using EDA tool for the input of different frequencies till 1 MHz. The excellent output waveforms verify the proposed circuit with the characteristics of full-wave rectifier. The hardware prototype is implemented &amp; tested on printed circuit board using laboratory setup to validate the proposed concept. The resultant output signal is undistorted, fully rectified and maintained with sinusoidal shape for the input signal having frequency of 1.022 MHz. The metal oxide semiconductor structure with the small signal analysis of proposed circuit is also discussed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"21 - 30"},"PeriodicalIF":1.2,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A multiplier-less meminductor emulator with experimental results and neuromorphic application 无乘法器忆阻器仿真器及其实验结果和神经形态应用
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-04 DOI: 10.1007/s10470-024-02286-9
B. Suresha, Chandra Shankar, S. B. Rudraswamy
{"title":"A multiplier-less meminductor emulator with experimental results and neuromorphic application","authors":"B. Suresha,&nbsp;Chandra Shankar,&nbsp;S. B. Rudraswamy","doi":"10.1007/s10470-024-02286-9","DOIUrl":"10.1007/s10470-024-02286-9","url":null,"abstract":"<div><p>This research article presents a meminductor emulator without multiplier using double output second generation current conveyor (DO-CCII) and operational trans-conductance amplifiers (OTA) and minimum numbers of passive elements. The mathematical expression of meminductor is obtained and verified through various simulation i.e., hysteresis analysis, non-volatile analysis and process corner analysis. Also, presented post-layout simulation of silicon components (DO-CCII and OTA). Application of meminductor emulator as Amoeba behaviour is also incorporated in the Neuromorphic circuit. Furthermore, an experimental setup was also build using the off the shelf ICs AD844AN (for DO-CCII) and CA3080EZ (for OTA) to examine the experimental results. The proposed meminductor emulator is simulated in Cadence Virtuoso tool using standard CMOS 90 nm technology.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"109 - 123"},"PeriodicalIF":1.2,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Active block EX-CCII based electrical circuit for practical impedance data of OSCC 基于有源块 EX-CCII 的电路,用于 OSCC 的实际阻抗数据
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-02 DOI: 10.1007/s10470-024-02273-0
Bidhanshel Singh Athokpam, Ashish Ranjan, Sumita Banerjee, Vivek Bhatt, Mamata Maisnam, Saikat Mukherjee
{"title":"Active block EX-CCII based electrical circuit for practical impedance data of OSCC","authors":"Bidhanshel Singh Athokpam,&nbsp;Ashish Ranjan,&nbsp;Sumita Banerjee,&nbsp;Vivek Bhatt,&nbsp;Mamata Maisnam,&nbsp;Saikat Mukherjee","doi":"10.1007/s10470-024-02273-0","DOIUrl":"10.1007/s10470-024-02273-0","url":null,"abstract":"<div><p>Oral Squamous Cell Carcinoma (OSCC) is the most common oral cancer, and its behavior can be analyzed using bio-impedance. A single dispersion Cole model is designed using active block Extra X Current Conveyor (EX-CCII), which generates the existing practical oral OSCC bio-impedance data. An experimental result of cancer bio-impedance in the 20 Hz to 5 MHz range is well modeled with an active block EX-CCII resistors (R <span>(_{infty })</span> and R<sub>1</sub>) and fractional capacitor (C<sub>α</sub>). The proposed design can serve as a step forward for designing a purposeful method for analyzing the behavior of oral cancer impedance without any practical data. The functionality of the proposed electrical circuit for OSCC is well verified through PSPICE simulation using both 0.25 μm CMOS TSMC Technology parameters and the macro model of EX-CCII. Simulation results agree well with experimental bio-impedance data.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"31 - 38"},"PeriodicalIF":1.2,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141522599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An offset calibration scheme for on-chip thermal profiling with differential temperature sensors 利用差分温度传感器进行片上热剖析的偏移校准方案
IF 1.2 4区 工程技术
Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-02 DOI: 10.1007/s10470-024-02285-w
Mengting Yan, Marvin Onabajo
{"title":"An offset calibration scheme for on-chip thermal profiling with differential temperature sensors","authors":"Mengting Yan,&nbsp;Marvin Onabajo","doi":"10.1007/s10470-024-02285-w","DOIUrl":"10.1007/s10470-024-02285-w","url":null,"abstract":"<div><p>This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage offset due to device mismatches and on-chip temperature gradients. The calibration circuits were designed in a standard 65 nm CMOS process for simulation. Results indicate that an input-referred offset with a mean of 0.2 μV can be achieved after calibration, through which the standard deviation is greatly reduced from <i>σ</i> = 880.3 to <i>σ</i> = 5086 μV. Furthermore, the proposed analog offset calibration scheme has negligible impact on the sensitivity of the complete temperature sensor circuit, as shown by Monte Carlo and process-temperature corner simulation results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"83 - 91"},"PeriodicalIF":1.2,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02285-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141522598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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