{"title":"Exploring analog VLSI architectures for linear regulators and high-speed receivers: a comprehensive SLR and emerging innovations","authors":"Suresh Nagula, Sreehari Rao Patri, Ekta Goel","doi":"10.1007/s10470-025-02486-x","DOIUrl":"10.1007/s10470-025-02486-x","url":null,"abstract":"<div><p>This paper thoroughly examines the current research on analog VLSI designs, with an emphasis on linear regulators and high-speed receivers. The main goal is to examine and evaluate design methodologies that increase power supply rejection ratio (PSRR), optimize power consumption, and enhance bandwidth for high-speed receivers. The evaluation also emphasizes new advancements in digital-assisted analog designs and adaptive equalization methods that reduce signal distortion. Experimental findings illustrate the efficacy of the suggested frameworks in enhancing performance across diverse applications in communication and power control systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02486-x.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145062158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Amirehsan Shahraki, Mohammad Taherzadeh, Shoeib Rahmatollahi , Frederic Nabki
{"title":"A clock-less coherent ultrawideband detector for active-reflector-based ranging with high interference rejection","authors":"Amirehsan Shahraki, Mohammad Taherzadeh, Shoeib Rahmatollahi , Frederic Nabki","doi":"10.1007/s10470-025-02504-y","DOIUrl":"10.1007/s10470-025-02504-y","url":null,"abstract":"<div><p>This paper introduces a clock-less coherent ultrawideband (UWB) detector tailored for active-reflector-based ranging systems, specifically engineered for robust performance in high-interference environments. Conventional impulse-radio UWB (IR-UWB) ranging systems often face challenges with various interference sources, which can degrade their precision. Non-coherent detectors, while offering design simplicity, typically exhibit lower sensitivity and greater susceptibility to interference. Conversely, existing coherent detectors, though inherently more robust, often introduce complexities related to precise clock synchronization and overall system cost. This research addresses these limitations by evolving a previously developed non-coherent two-way ranging system through the design and implementation of a novel coherent UWB detector. The proposed architecture enhances interference resilience by employing binary phase shift keying (BPSK) combined with pulse position modulation (PPM) for sync word encoding, a more robust alternative to on-off keying (OOK) based methods. A critical innovation lies in the sync word detector circuit, which features a configurable 4-bit sync word, tunable delay lines, and dual comparators, enabling high selectivity for the intended UWB signal. Fabricated using 65 nm CMOS technology, the proposed detector maintains comparable timing accuracy to its non-coherent predecessor while demonstrating markedly superior rejection capabilities against single-tone interference (STI), narrowband interference (NBI), and co-channel UWB interference. These empirical results underscore the detector’s suitability for demanding applications that require dependable ranging performance amidst pervasive radio frequency interference.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145062156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ahmad Parsa, Pejman Rezaei, Ali AmneElahi, Amin Khatami, Zahra Mousavirazi
{"title":"Efficient transition from SMA to ESIW for planar slot array antennas in wireless systems","authors":"Ahmad Parsa, Pejman Rezaei, Ali AmneElahi, Amin Khatami, Zahra Mousavirazi","doi":"10.1007/s10470-025-02498-7","DOIUrl":"10.1007/s10470-025-02498-7","url":null,"abstract":"<div><p>In this manuscript, a planar slot array antenna is designed to operate at 10 GHz using empty substrate integrated waveguide (ESIW) technology. ESIW is an advanced form of substrate integrated waveguide (SIW) in which the dielectric material between the metal layers is removed and replaced with air to significantly reduce dielectric losses and improve radiation efficiency. The proposed structure is implemented on a standard PCB and consists of three main parts: (1) a coaxial (SMA) to SIW transition, (2) a tapered SIW-to-ESIW transition section, and (3) an eight-element ESIW-based slot array radiator. By eliminating most of the dielectric material, the ESIW-based design achieves enhanced radiation efficiency and lower insertion loss compared to conventional SIW slot arrays. The overall physical dimensions are 22 × 221 × 4.4 mm³, and the antenna achieves a fractional bandwidth of 3.85%, with a radiation efficiency of approximately 94% and a realized gain of 15.6 dB at the center frequency. The performance of the antenna was evaluated using full-wave simulations in CST, and the results show excellent agreement with experimental measurements.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145037139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Sivaraman, H. Naresh Kumar, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram
{"title":"Towards robust true random number generation: addressing vulnerabilities in dual entropy source design","authors":"R. Sivaraman, H. Naresh Kumar, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram","doi":"10.1007/s10470-025-02488-9","DOIUrl":"10.1007/s10470-025-02488-9","url":null,"abstract":"<div><p>Recently, Chen et al. introduced a dynamic dual entropy source-assisted True Random Number Generator (TRNG) implemented on a Field Programmable Gate Array (FPGA). They asserted that their design achieved superior true randomness and higher throughput. This paper comprehensively analyses Chen et al.‘s TRNG [1], identifying potential vulnerabilities. Chen et al. employed a Multiplexer Ring Oscillator (MRO) as the entropy source for generating true random numbers. This MRO leverages dual entropy sources—metastability and clock jitter—to create true randomness. By exploiting the weaknesses inherent in the MRO, we critically examine the results and validation of Chen et al.‘s TRNG. Despite the TRNG’s minimal hardware footprint on the AMD-Xilinx Artix-7 FPGA—utilizing only 10 number of LUTs, 2 number of DFFs, and 1 unit of MUX—and its impressive bit generation rate of 300 Mbps, it fails to produce adequate randomness. This inadequacy is evident when evaluated against standard metrics such as Shannon Entropy, Autocorrelation, and NIST SP 800 − 22. To address these deficiencies, we propose enhancing Chen et al.‘s TRNG, aimed at improving randomness without altering the entropy source, through lightweight post-processing. This approach yielded an 85.71% improvement in randomness after four rounds of post-processing. However, this enhancement significantly reduces throughput by a factor of ½. In conclusion, while the TRNG by Chen et al. demonstrates promising features, it necessitates a robust entropy source with a multi-ring structure rather than the dual-ring MRO for optimal performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jatismar Saha, Manosh Protim Gogoi, Bijit Choudhuri, Rajesh Saha
{"title":"Investigating the effects of interface trap charges and temperature on n-type step tunneling path TFET","authors":"Jatismar Saha, Manosh Protim Gogoi, Bijit Choudhuri, Rajesh Saha","doi":"10.1007/s10470-025-02505-x","DOIUrl":"10.1007/s10470-025-02505-x","url":null,"abstract":"<div><p>This work presents the design and analysis of a Step Tunneling Path (STP) TFET, aimed at enhancing tunneling control and making it suitable for low power applications. The device performance is evaluated under varying interface trap charge (ITC) densities ranging from 10¹² cm⁻² to 3 × 10¹² cm⁻² and temperature conditions from 300 K to 500 K. The DC analysis investigates the influence of positive and negative ITCs on transfer characteristics, energy band diagram shifts at ambipolar states, BTBT rate, and threshold voltage. Additionally, the effects of ITC concentration on AC parameters such as gate capacitance, transconductance, and cut-off frequency are examined. The study also includes a comprehensive evaluation of DC and RF/analog performance over the specified temperature range. The findings provide valuable insights into optimizing STP TFET performance and reliability for low-power electronic applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient wireless sensor node for autonomous sensing in the ISM band","authors":"Naveed, Jeff Dix","doi":"10.1007/s10470-025-02497-8","DOIUrl":"10.1007/s10470-025-02497-8","url":null,"abstract":"<div><p>This paper presents a radio frequency powered wireless sensor node (WSN) implemented in 22-nm FD-SOI technology, designed for autonomous operation in the ISM band. The sensor node harvests energy from a dedicated 915 MHz radio frequency (RF) source and generates a 2.44 GHz carrier signal for data transmission. The proposed design integrates a high-efficiency RF rectifier utilizing ultra-low-power diode-based rectification and SOI MOSFET back-plate connections, enhancing energy conversion efficiency and sensitivity. A nanowatt-level power management unit (PMU) ensures stable operation with minimal power overhead. The wireless transmission module employs a DLL-based XOR frequency synthesizer with an improved duty cycle correction circuit, achieving low-power, high-precision RF carrier generation. Operating at an RF input power sensitivity as low as − 25 dBm, the WSN can function effectively up to 12 m from the power source. Experimental results demonstrate a peak power conversion efficiency (PCE) of 57% at − 14 dBm and 28% at − 25 dBm, with a maximum input tolerance of 0 dBm to prevent device breakdown. Using On–Off Keying (OOK) modulation, the transmitter outputs − 3.8 dBm power with 55% power efficiency via a switching power amplifier. The synthesizer and power amplifier consume 160 µW and 500 µW, respectively. Occupying a 0.17 mm<sup>2</sup> active die area, this design offers an area-efficient, sustainable, and cost-effective solution for diverse remote sensing applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1.2–6.6 GHz Sub-sampling PLL with adaptive pulse width match achieving 216 fs rms jitter and − 71.90 dBc reference spurs","authors":"Xiang Cheng, Baolin Wei, Xueming Wei, Weilin Xu, Hongwei Yue","doi":"10.1007/s10470-025-02485-y","DOIUrl":"10.1007/s10470-025-02485-y","url":null,"abstract":"<div><p>With the demands for different rates of serial data received and transmitted in a communication system, an adaptive bandwidth sub-sampling phase-locked loop (AB-SSPLL) was designed. To maintain the bandwidth of the AB-SSPLL varying with the reference clock frequency, a self-biasing adaptive pulse width matching technique was introduced to the proposed AB-SSPLL. It adaptively adjusts the gain of the sub-sampling charge pump to maintain a constant ratio of the loop bandwidth to the reference clock frequency. The proposed AB-SSPLL has the advantages of broad bandwidth and low jitter. The AB-SSPLL is designed using a 40 nm COMS process and has an area of 0.21 × 0.26 mm<sup>2</sup>. The simulation results show that the phase-locked loop tuning range is 1.2–6.6 GHz, the root mean square jitter of the output clock is 312.3 fs@1.2 GHz and 216.3 fs@6.6 GHz, and the reference spurious is -71.90 dBc@1.2 GHz and − 61.39 dBc@6.6 GHz, respectively, and the jitter performance of ring-VCO-based AB-SSPLL can be comparable to that of the LC-VCO-based PLL.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-Power FIR filter pruning using secretary bird optimization for Hardware-Efficient signal processing","authors":"G. Theivanathan, C. Murukesh","doi":"10.1007/s10470-025-02490-1","DOIUrl":"10.1007/s10470-025-02490-1","url":null,"abstract":"<div><p>This paper proposes an efficient Finite Impulse Response (FIR) filter design using a novel pruning technique optimized with the Secretary Bird Optimization (SBO) algorithm. The key novelty lies in the introduction of a customized multi-objective cost function that integrates coefficient significance, power consumption, delay, and area, enabling hardware-aware pruning decisions. Unlike standard SBO applications, the algorithm is adapted for FIR filter design by dynamically balancing exploration and exploitation phases through a feedback coefficient mechanism. The proposed method effectively identifies and eliminates less significant filter components to reduce complexity without compromising performance. Implementation results demonstrate substantial improvements: up to 30.5% reduction in power, 35% reduction in delay, 21.1% decrease in area, and up to 63.4% reduction in area-delay product across different filter tap sizes. These results validate the proposed approach as a scalable and energy-efficient solution for digital signal processing applications, particularly suitable for low-power VLSI systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144990495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Heterojunction (SiGe/Si) triple metal dual gate extended source tunnel FET for improved DC, noise and linearity performance","authors":"Sheetal Singh, Subodh Wairya","doi":"10.1007/s10470-025-02492-z","DOIUrl":"10.1007/s10470-025-02492-z","url":null,"abstract":"<div><p>In this paper, a 2-D model of a hetero-triple metal dual gate extended source tunnel FET (TMDG-ES-TFET) is analyzed. The device features a heterojunction (HJ) designed by silicon germanium (SiGe) and Si materials in the source-channel junction and a hetero-dielectric gate stack (GS) using dielectric as silicon dioxide (SiO<sub>2</sub>) and hafnium dioxide (HfO<sub>2</sub>). In this research, the DC characteristics, linearity, and noise performance have been investigated. In structure the entire source region over the oxide layer has been overlapped by three distinct metals with various work functions. The paper has also investigated the impact of increasing source width (80 nm and 120 nm) over the channel. The SiGe is used as a source thereby improving the I<sub>ON</sub>/I<sub>OFF</sub> value and threshold voltage (V<sub>th</sub>). The structure has a greater I<sub>ON</sub>/I<sub>OFF</sub> reflected as 9.1 × 10<sup>12</sup>, a lower sub-threshold value of 41 mV/decade, and a lower V<sub>th</sub> of 0.58 V. A standardized SILVACO technology computer aided design (TCAD) is used for the simulation. Additionally, the linearity analysis was performed as a figure of merit (FOM) for a device under investigation, taking into account various parameters like 1db compression point, 2nd and 3rd -order voltage intercept points (VIP<sub>2</sub> and VIP<sub>3</sub>), the 3rd -order intermodulation distortion point (IMD<sub>3</sub>), and the third order intermodulation intercept point (IIP<sub>3</sub>).</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144990494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Irfan Ahmad Pindoo, Sanjeet Kumar Sinha, Sweta Chander
{"title":"Performance analysis of SiGe source based heterojunction TFET biosensor for improved sensitivity","authors":"Irfan Ahmad Pindoo, Sanjeet Kumar Sinha, Sweta Chander","doi":"10.1007/s10470-025-02479-w","DOIUrl":"10.1007/s10470-025-02479-w","url":null,"abstract":"<div><p>This work presents a novel SiGe-source-based heterojunction tunnel field-effect transistor (TFET) biosensor that incorporates a nanogap dielectric cavity beneath the gate and a hetero-dielectric BOX (HDBOX) structure for ultra-sensitive, label-free detection of both neutral and charged biomolecules. The proposed device architecture leverages a low-bandgap SiGe source to enhance band-to-band tunneling (BTBT) efficiency and utilizes dielectric modulation in the nanogap cavity to enable electrostatic coupling with immobilized biomolecules. The sensor exploits distinct detection mechanisms—dielectric constant variation for neutral biomolecules and combined dielectric and charge-field modulation for charged species—thereby achieving a comprehensive detection capability. Extensive TCAD simulations, calibrated against experimental TFET data, were conducted using Kane’s BTBT model, Lombardi mobility, Fermi–Dirac statistics, and SRH recombination, under room temperature conditions. The device demonstrates a high ON/OFF current ratio of 1.947 × 10<sup>8</sup>, a steep subthreshold slope of 28.57 mV/decade, and a maximum current-based sensitivity (SID) of 1.548 × 10<sup>8</sup> for a dielectric modulation range of κ = 1 to 26. Compared to state-of-the-art DM-TFET and PNPN-TFET biosensors, the proposed design exhibits significantly improved sensitivity, lower off-state leakage (~ 10<sup>–14</sup> A), and reduced process complexity. While this study is simulation-based, the device structure employs CMOS-compatible materials and fabrication techniques, paving the way for future experimental validation. These results position the HDBOX TFET biosensor as a promising candidate for real-time, low-power, and label-free biomedical diagnostics.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144926954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}