Analog Integrated Circuits and Signal Processing最新文献_第3页

A novel low power high speed 14T-TSPC-DomDFF design and analysis in CMOS 16nm technology

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-18 DOI: 10.1007/s10470-025-02371-7

Ramsha Suhail, Pragya Srivastava, Richa Yadav, Nandini Baliyan, Rewa Chaudhary

{"title":"A novel low power high speed 14T-TSPC-DomDFF design and analysis in CMOS 16nm technology","authors":"Ramsha Suhail, Pragya Srivastava, Richa Yadav, Nandini Baliyan, Rewa Chaudhary","doi":"10.1007/s10470-025-02371-7","DOIUrl":"10.1007/s10470-025-02371-7","url":null,"abstract":"<div><p>Utilised in a range of applications such as registers, counters, and state machines, the D Flip-Flop (DFF) is a flexible device that has undergone development over time with innovative design approaches to enhance power efficiency. True Single Phase Clock (TSPC) logic has constantly been a preferred option in high-speed applications. This work introduces an enhanced 14 Transistor TSPC-based positive edge-triggered Domino DFF (TSPC DomDFF) at 16 nm with a Clock-to-Q (CQD) latency of 55.4ps, improved power consumption of 96.8nW, and salient Power Delay Product (PDP) and Energy Delay Product (EDP) as 5.36aJ and 0.297aJ-ns, respectively, at an operating voltage of 0.9 V. It showcases the performance of a high speed and power efficient design with 32%, 77%, 85%, 94% improvement in PDP with respect to MTSPC, 26TSPC, 18T HFF, and MSDFF respectively. The results are validated through detailed robust analysis. Furthermore, the proposed 14T TSPC DomDFF is implemented to construct a 4-bit Serial-in-Serial-out (SISO) Shift Register (4-SISO SR) at operating frequency of 5 GHz. The improved results enabled the physical layout design to be accommodated within an optimized area of 3.7µm<sup>2</sup> for the proposed circuit and 15.4µm<sup>2</sup> for the proposed application.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel low-power, high-speed carry look ahead adder utilizing 11-T hybrid full adder module based 4:2 compressor unit for low-power applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-18 DOI: 10.1007/s10470-025-02361-9

Nimai Halder, Biswarup Mukherjee

引用次数: 0

Design of high-speed and 6-bit flash ADC module for non-contact vital sign signal processing in biomedical application

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-18 DOI: 10.1007/s10470-025-02376-2

Pushparaj Pal, Banoth Krishna, Amod Kumar, Sandeep Singh Gill, Garima Saini

{"title":"Design of high-speed and 6-bit flash ADC module for non-contact vital sign signal processing in biomedical application","authors":"Pushparaj Pal, Banoth Krishna, Amod Kumar, Sandeep Singh Gill, Garima Saini","doi":"10.1007/s10470-025-02376-2","DOIUrl":"10.1007/s10470-025-02376-2","url":null,"abstract":"<div><p>The signal processing is the primary factor for improving the accuracy of bio signals in electronic devices with respect to speed and resolution. The ADC is often called the heart of the electronics processing system. Without the ADC module, the device cannot proceed to further processing stages and becomes non-functional. In biomedical applications, healthcare service providers remotely monitor patients using non-contact vital sign detection and signal monitoring through CW Doppler radar of 2.45 GHz. The system collects tiny signals remotely, with HR signals of (0.2–0.5)Hz and RR signals of (0.3–0.7)Hz. Recovering these signals from the received data, containing clutters and noise, is a challenging task that requires a high-speed, high-resolution, and accurate-based system. The SAR-ADC has existing problems with high speed and bit resolution, system performance, and accuracy, which are overcome in the flash ADC with reduced hardware. The received signal is further processed using the DAQ system. The system uses a 6-bit 1GS/s flash ADC for enhanced system performance. Simulation results show an INL of -0.49/+0.76 LSB and DNL of -0.65/+0.59 LSB, respectively. At -0.3 dBFS and a 1 kHz sinusoidal signal, the SNDR is 47dB (6.4 ENOB). The system operates at power level of 96.08uW with a supply voltage of 1.6 V. The implementation is carried out using simulation tools such as Cadence Virtuoso, and MATLAB platforms.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Single event transient (SET) for a novel step-truncated SELBOX FinFET device

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-18 DOI: 10.1007/s10470-025-02367-3

Baojun Liu, Jing Zhu

引用次数: 0

An ultra-fast settling and low area bit synchronizer architecture

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-18 DOI: 10.1007/s10470-025-02364-6

Amitava Ghosh, Anindya Sundar Dhar

{"title":"An ultra-fast settling and low area bit synchronizer architecture","authors":"Amitava Ghosh, Anindya Sundar Dhar","doi":"10.1007/s10470-025-02364-6","DOIUrl":"10.1007/s10470-025-02364-6","url":null,"abstract":"<div><p>The paper presents the architecture design of a bit synchronizer suited for wireless sensor node applications. It detects a 0–1 transition sent from transmitter that subsequently triggers a counter clocked by a reference. The counter counts a certain number of reference cycles and generates a strobe signal that is used to sample the demodulated waveform at the maximum signal to noise ratio (SNR) instant. Because of the position of the maximum SNR point, there is a latency in the strobe signal. This latency can be measured off-chip and on-chip. Off-chip solution entails observing a repetitive 0–1 pattern sent from the transmitter, and the reference clock post fabrication in an oscilloscope in test lab and writing the latency in terms of reference cycle counts into the chip. On-chip solution uses samplers to sample the demodulated waveform at multiple instants and finds the time where the maximum sampled value occurs. Algorithm was designed first from which the architecture was generated. For the off-chip method, circuit design followed by layout was also performed. The bit synchronizer requires just two bits (for on-chip solution three bits are required) to align with the optimum sampling instant which is very fast compared to existing literature and hence has ultra-fast settling capability. The circuit requires 2364 transistors and the area occupied is 0.069mm<sup>2</sup>. Power consumption is also low being 7.26 µW while bit error ratio less than 10<sup>−3</sup> was achieved for different parameter settings. The receiver design has been targeted for implant telemetry in the 402-405 MHz frequency band.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of 2 × 1 MIMO antenna with inverted E-shaped unit cell for high isolation

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-18 DOI: 10.1007/s10470-025-02373-5

B. Elizabeth Caroline, K. Sagadevan, J. Vidhya, K. Mangaiyarkarasi

引用次数: 0

A compact frequency reconfigurable MIMO antenna with high isolation for Wi-Fi and fixed satellite applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-06 DOI: 10.1007/s10470-025-02358-4

B. Ramamohan, M. Siva Ganga Prasad

引用次数: 0

Voltage mode quadrature sinusoidal oscillators employing inverting current feedback operational amplifier 采用反相电流反馈运算放大器的电压模式正弦波振荡器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-06 DOI: 10.1007/s10470-025-02356-6

Tajinder Singh Arora

引用次数: 0

A novel chaotic system with 2-D grid multi-scroll chaotic attractors through quasi-sine function

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-05 DOI: 10.1007/s10470-025-02345-9

Pengfei Ding, Zixuan Wang, Ke Li, Le Yang

{"title":"A novel chaotic system with 2-D grid multi-scroll chaotic attractors through quasi-sine function","authors":"Pengfei Ding, Zixuan Wang, Ke Li, Le Yang","doi":"10.1007/s10470-025-02345-9","DOIUrl":"10.1007/s10470-025-02345-9","url":null,"abstract":"<div><p>With regard to chaotic system with multi-scroll chaotic attractors in multiple directions, the circuit complexity and the size of electronic components of its circuit implementation raise with the increase of the direction and quantity of scrolls. For reducing the complexity of circuit implementation of multi-scroll chaotic attractors, we came up a novel chaotic system with two-directional (2-D) grid multi-scroll chaotic attractors, and its nonlinear term is a quasi-sine function (QSF), which is multiplication of a gate function and a sine function. The circuit implementation of QSF is much simpler compared to other nonlinear functions used in existing chaotic systems. The dynamical properties of Lyapunov exponents, equilibrium points, phase portraits and bifurcation diagrams were discussed. Based on the analyses of dynamical characteristics, the electronic circuits of the novel chaotic system through Multisim software, and the circuit simulation results have good consistency with the numerical ones. Especially, the effectiveness and feasibility of the chaotic system are confirmed through hardware circuits, and its circuit complexity is not affected by the quantity of scrolls, which is easily regulated through changing the width of the gate function used in the QSF.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design, development and performance of video processor electronics for ocean imaging payload in EOS-06 satellite

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02348-6

Ashok Kumar, Ravi Kumar, Pradeep Soni, Vishnu D. Patel, Ashish Mishra

{"title":"Design, development and performance of video processor electronics for ocean imaging payload in EOS-06 satellite","authors":"Ashok Kumar, Ravi Kumar, Pradeep Soni, Vishnu D. Patel, Ashish Mishra","doi":"10.1007/s10470-025-02348-6","DOIUrl":"10.1007/s10470-025-02348-6","url":null,"abstract":"<div><p>Knowledge of ocean colour information is vital for locating of Potential fishing zone (PFZ). For oceanographic studies, Indian space research organization (ISRO) has launched one Ocean color monitor (OCM-3) payload onboard EOS-08 satellite. OCM-3 has 13 fine spectral bands for better delineation of ocean features with SNR requirements of ≈ 1000 (@ sea reference radiance). Video processor (VP) electronics is the critical circuit for precisely digitizing the multi-port analog signal received from the detectors while maintaining low noise. The design, development and performance of video processor electronics for OCM-3 payload is compiled in this paper. Thirteen separate electronic chains are developed catering to each spectral band. Detector video is processed with 12-bit digitization by 8-port video processor. To obtain higher SNR and lesser electrical coupling, circuit and layout are optimized. The electrical performance is showcased with an SNR of around 4000 and coupling (both intra-and inter-port) confined to less than 0.1%. The developed video processor PCB has a power dissipation of less than 1W and measures only 150 × 110 mm. Acquired onboard images illustrates SNR performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0