Analog Integrated Circuits and Signal Processing最新文献_第3页

FPGA-enabled lossless ECG signal compression system using an integer adaptive compressor 使用整数自适应压缩器的 FPGA 无损心电信号压缩系统

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-03-22 DOI: 10.1007/s10470-024-02269-w

Palagiri Veera Reddy, V. V. Satyanarayana Tallapragada

{"title":"FPGA-enabled lossless ECG signal compression system using an integer adaptive compressor","authors":"Palagiri Veera Reddy, V. V. Satyanarayana Tallapragada","doi":"10.1007/s10470-024-02269-w","DOIUrl":"10.1007/s10470-024-02269-w","url":null,"abstract":"<div><p>The most common non-invasive diagnostic model is the Electrocardiogram (ECG), which records the heart’s electrical activity over time and is used to diagnose various heart conditions. Due to the requirements of a typical eHealth system, it is necessary to compress ECG signals for long-term data recording and remote transmission. Moreover, cardiovascular diseases (CVDs) have been considered the most long-lasting disorders in recent years. The transmission of information from the patient to the distant hospital is necessary because rapid analysis and treatment are essential for the condition to be cured. Also, the data must be in the form of lossless and high-predictability data. So, the goal of this study was to create a two-stage lossless Integer Adaptive Predictor (IAP) compressor that could be implemented on a Field Programmable Gate Array (FPGA) without introducing any data loss during the compression process. Before compression, the ECG signals are denoised using a Fast Normalized Least Mean Square (FNLMS) algorithm-based adaptive filter, which removes the undesirable noise presented in the signal. Here, the adaptive filter is designed based on the hybrid systolic folding structure and compressor-based multiplier architecture to minimize the power, delay and area consumption of the filter while performing the signal-denoising process. Xilinx and MATLAB are used to run simulations using the MIT-BIH Arrhythmia and PTB diagnostic databases. Several performance parameters are used to assess the proposed design’s efficacy, and the results are compared to those of similar current designs. Consequently, the proposed compressor achieves a 45.23% compression ratio (CR) on MIT-BIH and a 10.87% average CR on the PTB diagnostic database, which demonstrates that the compression proficiency of the proposed design is high.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140196285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Model and design of an efficient controller for microgrid connected HRES system with integrated DC–DC converters: ATLA-GBDT approach 为带集成直流-直流转换器的微电网连接 HRES 系统建立模型并设计高效控制器：ATLA-GBDT 方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-03-12 DOI: 10.1007/s10470-023-02218-z

Kamaraju Vechalapu, Chintapalli V. V. S. Bhaskara Reddy

{"title":"Model and design of an efficient controller for microgrid connected HRES system with integrated DC–DC converters: ATLA-GBDT approach","authors":"Kamaraju Vechalapu, Chintapalli V. V. S. Bhaskara Reddy","doi":"10.1007/s10470-023-02218-z","DOIUrl":"10.1007/s10470-023-02218-z","url":null,"abstract":"<div><p>A controller is modelled and designed to optimize the power transfer in microgrid-connected hybrid renewable energy systems using an integrated DC/DC converter. To maximize the converter's output power and minimize the switching losses of the converter, a model is developed by including a simplified high conversion ratio converter, a maximal power point tracker, and an optimal controller with an effective control strategy. The proposed control system is a combination of the Artificial Transgender Longicorn Algorithm (ATLA) and the Gradient Boosting Decision Tree (GBDT) algorithm, named the ATLA-GBDT method. In the suggested technique, the ATLA is used as an assessment method to build up accurate control signals for the system and to improve the control signals database for offline use while considering the power exchange between the source and load. In addition, for training a GBDT system online, the data set received from the sensor is used to develop a control system for faster response. In addition, the goal function is defined by the system data, which is subject to equality and inequality constraints. Various constraints considered in the problem formulation are the output of renewable energy sources, power requirements, and the state of charge of storage components. The proposed control system is simulated using the MATLAB/Simulink platform, and the implementation is compared with the existing techniques. Various performance metrics like accuracy, specificity, recall and precision, RMSE, MAPE, and MBE of the proposed method and existing methods in the literature are presented.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140128563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An improved blind Gaussian source separation approach based on generalized Jaccard similarity 基于广义雅卡德相似性的改进型高斯盲源分离方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-03-05 DOI: 10.1007/s10470-024-02264-1

Xudan Fu, Jimin Ye, Jianwei E

{"title":"An improved blind Gaussian source separation approach based on generalized Jaccard similarity","authors":"Xudan Fu, Jimin Ye, Jianwei E","doi":"10.1007/s10470-024-02264-1","DOIUrl":"10.1007/s10470-024-02264-1","url":null,"abstract":"<div><p>Blind source separation (BSS) consists of recovering the independent source signals from their linear mixtures with unknown mixing channel. The existing BSS approaches rely on the fundamental assumption: the number of Gaussian source signals is no more than one, this limited the use of BSS seriously. To overcome this problem and the weakness of cosine index in measuring the dynamic similarity of signals, this study proposes the fuzzy statistical behavior of local extremum based on generalized Jaccard similarity as the measure of signal’s similarity to implement the separation of source signals. In particular, the imperialist competition algorithm is introduced to minimize the cost function which jointly considers the stationarity factor describing the dynamical similarity of each source signal separately and the independency factor describing the dynamical similarity between source signals. Simulation experiments on synthetic nonlinear chaotic Gaussian data and ECG signals verify the effectiveness of the improved BSS approach and the relatively small cross-talking error and root mean square error indicate that the approach improves the accuracy of signal separation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140035952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An optimization approach control of EV solar charging system with step-up DC–DC converter 电动汽车太阳能充电系统与升压型 DC-DC 转换器的优化控制方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-28 DOI: 10.1007/s10470-024-02253-4

R. J. Venkatesh, R. Priya, P. Hemachandu, Chinthalacheruvu Venkata Krishna Reddy

{"title":"An optimization approach control of EV solar charging system with step-up DC–DC converter","authors":"R. J. Venkatesh, R. Priya, P. Hemachandu, Chinthalacheruvu Venkata Krishna Reddy","doi":"10.1007/s10470-024-02253-4","DOIUrl":"10.1007/s10470-024-02253-4","url":null,"abstract":"<div><p>An optimization technique for the control of a photovoltaic (PV)-fed electric vehicle (EV) solar charging station with a high gain of step-up dc-to-dc converter. An optimization approach is the Namib beetle optimization (NBOA) approach. This approach is used to control the EV solar charging station. Also, the principles of a switched capacitor and a coupled inductor are integrated into the interleaved structure of the NBOA converter to produce low-current, high-efficiency, and high-voltage gain. However, the major contribution is to minimize the total harmonic distortion (THD) and to control the EV solar Charging Station. The bi-directional DC-to-DC converter in an energy-storage-system has the advantages of high efficiency and fast response speed. By then, the NBOA technique is done in MATLAB software, and the performance is evaluated with the existing techniques. The NBOA system has low THD and high efficiency, which is compared with the existing ant-lion optimizer, wild horse optimizer, and salp-swarm algorithm, methods. From the analysis, the NBOA method provides a better outcome than the existing one.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140008639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of a low phase noise, wide tunable CMOS based low power VCO with active inductor 设计和分析基于有源电感器的低相位噪声、宽可调 CMOS 低功率 VCO

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-28 DOI: 10.1007/s10470-024-02266-z

Isha Kadyan, Manoj Kumar

引用次数: 0

Correction: A floating memristor emulator for analog and digital applications with experimental results 更正：用于模拟和数字应用的浮动忆阻器仿真器及实验结果

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-27 DOI: 10.1007/s10470-024-02268-x

B. Suresha, Chandra Shankar, S. B. Rudraswamy

引用次数: 0

Novel high-gain narrowband antenna based on ENZ SIW structure and shorting pin 基于 ENZ SIW 结构和短路引脚的新型高增益窄带天线

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-26 DOI: 10.1007/s10470-024-02267-y

Rajesh Kumar Dash, Sadhana Kumari, Balamati Choudhury

引用次数: 0

A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system 使用自适应神经模糊推理系统的 5G 毫米波应用新型宽带、小尺寸和高增益贴片天线阵列

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-25 DOI: 10.1007/s10470-023-02245-w

Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou

{"title":"A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system","authors":"Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou","doi":"10.1007/s10470-023-02245-w","DOIUrl":"10.1007/s10470-023-02245-w","url":null,"abstract":"<div><p>In this paper a wide-band, small size and high gain modified patch antenna array and a single element antenna for fifth Generation (5G) millimetre-wave (mm-wave) applications have been presented. The designing of single element antenna and array antenna is based on the Adaptive Neuro-Fuzzy Inference systems (ANFIS). The ANFIS technique is used to estimate the dimensions of the single element as well as the spacing between patch antenna elements in antenna array. The single element’s operating frequency is 28 GHz, While the array antenna covers the frequency band from 23.6 to 29.2 GHz, resonating at 25 and 28 GHz. The antenna array was designed and simulated using the Rogers RT duroid 5880 Substrate, which has a dielectric constant of 2.2, a loss tangent <span>(tan ( delta ))</span> of 0.0009, and thickness of 0.508 mm. The proposed single element patch antenna has a size of 4<span>(times 4.8)</span> <span>(times)</span>0.508 <span>({text{mm}}^{3})</span> with wideband range from 23 to 38.6 GHz (15.6 GHz) with a gain of 4.17 dB. Based on these properties, the single element is expanded into a six-element array with a compact size of 13.2<span>(times)</span>23.8<span>(times)</span> 0.508 <span>({text{mm}}^{3})</span> in order to enhance the gain and to make the antenna radiation pattern directional. The designed antenna array has a wide-band from 23.6 to 29.2GHz (5.6 GHz) and a high gain of 11 dB, making it as strong candidate for future mm-wave applications.\u0000</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02245-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139980196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scalable intelligent median filter core with adaptive impulse detector 具有自适应脉冲检测器的可扩展智能中值滤波器内核

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-25 DOI: 10.1007/s10470-024-02261-4

Nanduri Sambamurthy, Maddu Kamaraju

{"title":"Scalable intelligent median filter core with adaptive impulse detector","authors":"Nanduri Sambamurthy, Maddu Kamaraju","doi":"10.1007/s10470-024-02261-4","DOIUrl":"10.1007/s10470-024-02261-4","url":null,"abstract":"<div><p>This paper introduces a reconfigurable AI-enabled scalable median filter with an adaptive impulse detector designed for FPGA-based real-time imaging systems. Its primary objective is to address the degradation of image quality caused by mixed impulsive noise during real-time image transmission and reception. Existing median filters often struggle to provide real-time image processing results that meet high standards in terms of both accuracy and speed. This approach effectively suppresses noise in real-time images while preserving essential edge details, which are crucial for the performance of real-time imaging systems. The algorithm introduces a novel technique of replacing noisy pixels with the processed central value within the image filtering window. This ensures fidelity to the original pixel, which is vital for applications such as image filter cores. To handle high noise densities in real-time systems, the methodology employs a scalable sorting approach for median filtering and an impulse detector, ensuring robust noise reduction without excessive computational complexity. The AI-enabled scalable median filter system achieves a significant reduction in dynamic power consumption, realizing an impressive 46% decrease in power consumption and an 82% reduction in area compared to the existing system. This is particularly beneficial for addressing resource and power-aware constraints in real-time systems. Comprehensive performance evaluation, including metrics such as PSNR, MSE, IEF, and SSIM, demonstrates the efficacy of the filter in enhancing image quality, a critical factor for the success of real-time imaging systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications 用于 FMCW 应用的 80-84.8 GHz PLL，带自动跟踪米勒分频器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-24 DOI: 10.1007/s10470-024-02258-z

Popong Effendrik, Wei-Zen Chen

{"title":"An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications","authors":"Popong Effendrik, Wei-Zen Chen","doi":"10.1007/s10470-024-02258-z","DOIUrl":"10.1007/s10470-024-02258-z","url":null,"abstract":"<div><p>To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FM<sub>error</sub>/BW<sub>chirp</sub> and RMS-FM<sub>error</sub>/(BW<sub>chirp</sub> × f<sub>c</sub> × T<sub>c</sub>) with value of 0.013% and 0.77e−12<b>,</b> respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2024-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02258-z.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0