Analog Integrated Circuits and Signal Processing最新文献_第4页

Lightweight implementation of AES for resource constrained environment

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-04 DOI: 10.1007/s10470-025-02343-x

R. Parthasarathy, P. Saravanan, S. Rajesh Srivatsav, C. M. Manisha

{"title":"Lightweight implementation of AES for resource constrained environment","authors":"R. Parthasarathy, P. Saravanan, S. Rajesh Srivatsav, C. M. Manisha","doi":"10.1007/s10470-025-02343-x","DOIUrl":"10.1007/s10470-025-02343-x","url":null,"abstract":"<div><p>In order to enhance the data confidentiality and integrity in resource-constrained environments, an optimized hardware implementation of the Advanced Encryption Standard is proposed. An iterative architecture common for both AES-128 encryption and decryption, involving minimum hardware resources, is developed. The sub bytes and inverse sub bytes operations are realized using composite field arithmetic S-box and its inverse, respectively. The matrix constants of the inverse mixcolumns operation of decryption are expressed involving matrix constants of the mixcolumns operation of encryption. Hence, a common equation for both encryption and decryption is derived. Depending upon the requirement, encryption or decryption will be implemented with the minimum resources with appropriate control signals. The proposed work is implemented in both FPGA devices and ASIC platforms. The area occupied by the proposed architecture is 205 slices in the Virtex-5 FPGA device. The area estimate of the proposed design using 180nm technology SCL libraries is only 5644 GE, which highlights the design as a compact implementation of the AES-128 cipher and an optimal choice to ensure the safety of IoT devices.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-28 DOI: 10.1007/s10470-025-02352-w

R. Sivaraman, Srinidhi Magesh, S. Amruthavarshini, Manuj Aggarwal, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram

{"title":"Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF","authors":"R. Sivaraman, Srinidhi Magesh, S. Amruthavarshini, Manuj Aggarwal, D. Muralidharan, R. Muthaiah, V. S. Shankar Sriram","doi":"10.1007/s10470-025-02352-w","DOIUrl":"10.1007/s10470-025-02352-w","url":null,"abstract":"<div><p>Random Number Generators (RNGs) are pivotal in cryptographic applications, safeguarding the security and confidentiality of sensitive data through the generation of unpredictable cryptographic keys. Static Random Access Memory (SRAM)-based Physical Unclonable Functions (PUFs) offer a low-overhead alternative for generating randomness in Hybrid Random Number generator (HRNG) architectures, leveraging minimal hardware resources while maintaining robust performance. The proposed work presents a novel HRNG design that leverages an SRAM-based PUF as the entropy source. The extracted SRAM data undergoes a robust post-processing scheme involving a specialized one-way hash function, enhancing the randomness and unpredictability of the generated sequences. The HRNG architecture is implemented on Intel Cyclone IV E FPGA, which utilized 779 logic elements to achieve a throughput of 102.421 Mbps while consuming 148.02 mW of power dissipation to produce 2<sup>23</sup> bits. The performance was rigorously evaluated through NIST SP 800–22 test batteries that has 99.9% of pass rate, entropy analysis ensuring equidistribution, hamming distance, and correlation assessments. Compared to the state-of-the-art RNGs such as memristor chaos, metastable circuits, chaotic oscillators, the proposed method shows its efficacy in eliminating large hardware dependency while yielding robust randomness. Operating at 50 MHz, the proposed HRNG achieves a competitive balance between performance and power consumption, with a throughput that surpasses many existing implementations.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Glitch free transmission gate based linear and nonlinear PFD architectures for fast and low reference-spur PLL

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-28 DOI: 10.1007/s10470-025-02354-8

N. R. Sivaraaj, K. K. Abdul Majeed

{"title":"Glitch free transmission gate based linear and nonlinear PFD architectures for fast and low reference-spur PLL","authors":"N. R. Sivaraaj, K. K. Abdul Majeed","doi":"10.1007/s10470-025-02354-8","DOIUrl":"10.1007/s10470-025-02354-8","url":null,"abstract":"<div><p>This paper presents a Linear Phase Frequency Detector architecture (LPFD) and a Non-Linear Phase Frequency Detector (NLPFD) architecture. The proposed linear and nonlinear PFDs are free from the dead zone, blind zone, and glitches while maintaining a 360-degree detection range. The proposed Transmission Gate Voltage Divider Linear Phase Frequency Detector (TGVD-LPFD) is the best choice to provide better phase noise and reference spur for the PLL. However, the proposed transmission gate non-linear phase frequency detector (TG-NLPFD) is a better choice to have a faster locking PLL while maintaining all other better parameters. Phase-locked loop (PLL) has been implemented in a 180 nm CMOS process using these proposed linear and nonlinear PFD architectures and obtained a PLL with 2.72 GHz output frequency. A PLL built with a linear PFD has been found to offer a reference spur of <span>(-)</span>77.3 dBc and a lock time of 2.5 µs, which has been verified by modeling the PLL in the sdomain. The PLL built using non-linear PFD has been found to offer a reference spur of <span>(-)</span>74.5 dBc and a lock time of 2.3 µs, which has been verified by modeling the PLL in the state space analysis.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reducing delay and resistance of GNR based interconnect using insertion of buffers

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02346-8

Subrata Das, Debesh Kumar Das, Soumya Pandit

{"title":"Reducing delay and resistance of GNR based interconnect using insertion of buffers","authors":"Subrata Das, Debesh Kumar Das, Soumya Pandit","doi":"10.1007/s10470-025-02346-8","DOIUrl":"10.1007/s10470-025-02346-8","url":null,"abstract":"<div><p>As devices get extremely miniaturized at deep sub-micron design levels, the interconnections between logic blocks significantly influence the overall delay, power dissipation, and area of the system. Surface and grain-boundary scattering, high mobility degradation, higher leakage power, and considerable dopant variation as a result of continuous scaling all contribute to a rise in interconnect resistivity. Due to the superior electrical, mechanical, and thermal properties of graphene nanoribbon (GNR) material, GNR-interconnects may be viable substitutes for copper in future interconnects. Unlike traditional copper-interconnect, the routing in GNR-intrconnect is different. Recently routing with GNR-interconnect have been studied in different literatures with the objectives to reduce interconnect delay and resistance. In order to cope with the system of high speed and less area, interconnect-delay and resistance are needed to be further optimized. In this paper we discuss the issue of insertion of buffers in GNR-interconnect and show that proper insertion of buffers in GNR-interconnect may decrease both interconnect delay and resistance significantly. Whereas in traditional copper-interconnect only delay is reduced by insertion of buffers. We also discuss that the signal and power integrity as well as the stability also improve with the insertion of buffers. We propose an algorithm for proper insertion of buffers to decrease both of them. Elmore delay model is used to compute the delay of GNR interconnects. We observe the minimum 30% and 40% reduction in the interconnect resistance and the interconnect delay respectively in all test cases. The computational worst case time complexity of the algorithm proposed in this manuscript is <span>({mathcal {O}}({n^3}))</span>, where n is the number of terminals in the routing.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integration of metamaterials for quintuple band-notched ultra-wideband antennas

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02355-7

Sapna Arora, Sharad Sharma, Rohit Anand, Anupma Gupta, Ramesh Kumar, Ahmed Jamal Abdullah Al-Gburi

{"title":"Integration of metamaterials for quintuple band-notched ultra-wideband antennas","authors":"Sapna Arora, Sharad Sharma, Rohit Anand, Anupma Gupta, Ramesh Kumar, Ahmed Jamal Abdullah Al-Gburi","doi":"10.1007/s10470-025-02355-7","DOIUrl":"10.1007/s10470-025-02355-7","url":null,"abstract":"<div><p>This paper presents an elliptical monopole antenna integrated with metamaterial structures to achieve band-notched characteristics. Five narrowband spectrums are notched to mitigate interference in the ultra-wideband (UWB) spectrum. Satellite communication in the C-band (3.7 to 4.2 GHz) and the wireless local area network (WLAN) band (5.15 to 5.35 GHz) are suppressed by etching dual elliptical split-ring resonators (ESRRs) into the monopole radiator. A 2-via dual-slot electromagnetic band-gap (EBG) structure is designed on the left side of the feed line, which results in the rejection of the INSAT band (4.5 to 4.7 GHz) and the upper WLAN band (5.725 to 5.825 GHz). Additionally, the ITU band (7.95 to 8.55 GHz) is rejected by implementing a step-impedance resonator (SIR) on the right side of the feed line. The proposed antenna achieves a 10 dB impedance bandwidth of 8.5 GHz, covering the frequency range from 2.5 to 11.0 GHz, with miniaturized dimensions of 0.317λ × 0.317λ × 0.007λ. A mathematical model is employed to explain the behavior of the notched frequencies and is validated through the simulated surface current distribution. Across the entire passband, a consistent gain of 3 dB is achieved. The proposed structure is well-suited for UWB communication applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Action detection of objects devices using deep learning in IoT applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02350-y

Sabir Rustemli, Ahmed Yaseen Bishree Alani, Gökhan Şahin, Wilfried van Sark

{"title":"Action detection of objects devices using deep learning in IoT applications","authors":"Sabir Rustemli, Ahmed Yaseen Bishree Alani, Gökhan Şahin, Wilfried van Sark","doi":"10.1007/s10470-025-02350-y","DOIUrl":"10.1007/s10470-025-02350-y","url":null,"abstract":"<div><p>Internet of Things (IoT) technology is the communication and communication of smart technological devices with each other. However, with the development of the Internet of Things (IoT), the number of smart applications and interconnected devices is increasing day by day. Deep Learning (DL) method has become necessary to process the large amount of raw data collected and to further improve intelligence and application capabilities. It is seen that the majority of researchers focus on action detection. Standard Deep Learning techniques are difficult to use in IoT devices as Deep Learning applications require high CPU, RAM and storage. In this study, an action detection technique has been developed directly on the edge device by enabling the use of deep learning techniques in IoT devices. This technique, as a representation of neural networks, divides it into on-board computers. Visual action detection is one of the critical components of a smart city. High processing capacity and storage requirements severely limit comprehensive and precise monitoring within the IoT and edge computing framework. The structure proposed in this paper suggests the deployment of micro deep learning algorithms to the latest IoT and embedded devices, including the utilisation of minimal computing resources such as processor, power and memory, with a contribution to IoT and embedded device activities in action detection. The systematic analysis shows that many IoT devices can be applied to the proposed optimisation design. The proposed model is much smaller in size than existing models.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02350-y.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power factor correction in SMPS with optimized converter: a hybrid optimization approach

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02328-w

A. Anbazhagan, R. RamaPrabha

{"title":"Power factor correction in SMPS with optimized converter: a hybrid optimization approach","authors":"A. Anbazhagan, R. RamaPrabha","doi":"10.1007/s10470-025-02328-w","DOIUrl":"10.1007/s10470-025-02328-w","url":null,"abstract":"<div><p>In this research work, a novel hybrid optimization model based on an optimized Mahafzah controller is introduced for power factor correction (PFC). The precision, speed, and stability are improved by the overlapping dc–dc SEPIC converter. Additionally, the control settings of the Mahafzah controller will be adjusted using the new hybrid optimization model to improve the system's response time. Additionally, the control parameters of the Mahafzah controller are adjusted using the new hybrid optimization model to improve the system's response time. The proposed hybrid technique is the hybrid methodology of Artificial Gorilla Troops Optimizer (GTO) and Tree Seed Algorithm (TSA) and hence it is named as GTO–TSA technique. Finally, the proposed system's performance characteristics are examined and contrasted with those of traditional optimization algorithms. At that point, the performance of the suggested technique has been tested in the MATLAB program and is in contrast with that of other methods already in use. The proposed method outperforms existing algorithms across a wide range of input voltages, with a power factor ranging from 0.98 to 0.995 and %THD (Total harmonic distortion) with lower values ranging from 1.6 to 1.15. Similarly, when the load resistance is varied, the proposed method has the highest power factor of 0.981–0.999 and the lowest %THD of 18.0 to 1.2 compared to other algorithms.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A power traces based hardware trojan detection using deep artificial neural network

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-21 DOI: 10.1007/s10470-025-02351-x

Priyadharshini Mohanraj, Saravanan Paramasivam, Prashanth Sathyamoorthy

引用次数: 0

Wave active filter: a state-of-the-art review with odd and even order filter implementation

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-19 DOI: 10.1007/s10470-025-02340-0

Prerna Rana, Ashish Ranjan

{"title":"Wave active filter: a state-of-the-art review with odd and even order filter implementation","authors":"Prerna Rana, Ashish Ranjan","doi":"10.1007/s10470-025-02340-0","DOIUrl":"10.1007/s10470-025-02340-0","url":null,"abstract":"<div><p>This scientific literature survey aims to provide a detailed overview of Wave Active Filter (WAF), including sequential growth of the higher-order filter design using voltage mode and current mode design. This survey paper elaborates on a step-by-step procedure for the wave variable approach for filter design with mathematical analysis. In addition, this work specifically focuses on developing WAF designs using different active blocks. Higher-order WAF designs using modern active blocks are well recorded in this survey paper for better visualization. In literature, third-order and fourth-order WAF implementations are mainly enriched. Hence, an OTA-based WAF is designed for lower- to higher-order filters, demonstrating their efficacy for multifunctional applications such as Wave Active Low Pass Filter (WALPF), Wave Active High Pass Filter (WAHPF), and Wave Active Bandpass Filter (WABPF) using OTA. Besides the theoretical foundations, simulation, and experimental test results are also performed to validate the workability of the OTA-based WAF. The frequency responses of WALPF, WAHPF, and WABPF are demonstrated for the second to sixth orders. The functionality of the OTA-based WAF is verified through frequency spectrum analysis and Monte Carlo simulations. This paper ultimately offers an extensive review of the WAF design process, including mathematical analysis and practical realizations. It provides insights into WAF theory, its benefits, limitations, and potential for future advancements in high-order filters.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02340-0.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Crescent shaped novel 4 × 4 port MIMO design with defected ground structure for multiband sub 6 GHz applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-19 DOI: 10.1007/s10470-025-02306-2

P. Sushma Chowdary, Sampad Kumar Panda, V. Praveen Naidu

{"title":"Crescent shaped novel 4 × 4 port MIMO design with defected ground structure for multiband sub 6 GHz applications","authors":"P. Sushma Chowdary, Sampad Kumar Panda, V. Praveen Naidu","doi":"10.1007/s10470-025-02306-2","DOIUrl":"10.1007/s10470-025-02306-2","url":null,"abstract":"<div><p>A Quad port MIMO antenna resonating at sub-6 GHz 5G band is designed by utilising FR4 epoxy material having a dielectric constant of 4.4 and thickness of 1.6 mm. Four identical crescent shaped radiating elements fed by utilising a microstrip feed line are designed by utilising the finite element method based high frequency structure simulator. The antenna parameters are characterised by utilising sets of real measurements to validate the antenna design and modelling. Chemical etching has been utilised for fabricating the quad port antenna on a FR4 substrate. Vector network analyser has been used for measuring the scattering and transmission coefficients. As well as, an anechoic chamber has been used for measuring the far field radiations and the gain of the antenna under test. The basic antenna is a part of the quad-port structure consists of a crescent shaped circular patch with a defected ground structure and are fed individually. MIMO ability is obtained by arranging 4 identical antenna elements in a successive rotational means for obtaining good polarization diversity. The connected ground between the antenna elements is obtained by subtracting 4 circular slots from the ground plane by maintaining a common ground plane. None of the slots touches each other thus ensuring the common reference while maintaining the inter isolation better than 15 dB. The antenna demonstrated maximum gain and efficiency of 4.59dBi and 90%, respectively besides attaining a 10-dB impedance bandwidth of 2–6.2 GHz and ECC < 0.01. Finally, the quad-port compact MIMO antenna is designed, simulated, fabricated and tested, it shows that the antenna is useful for n1, n40, n41, n77, n78 and n79 5G bands. This bandwidth makes the antenna useful for Sub-6 GHz 5G wireless applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0