Analog Integrated Circuits and Signal Processing最新文献

{"title":"Neural-network-based digital calibration for high-speed pipelined ADCs","authors":"Qi Zhang,&nbsp;Chaoming Liu,&nbsp;Hui Jin,&nbsp;Tieliang Zhang,&nbsp;Mingxue Huo","doi":"10.1007/s10470-026-02639-6","DOIUrl":"10.1007/s10470-026-02639-6","url":null,"abstract":"<div><p>The dynamic performance of high-speed pipelined analog-to-digital converters (ADCs) is jointly affected by gain error, offset error, static nonlinearity, periodic code-domain disturbances, and weak memory effects. Conventional digital calibration methods usually rely on explicit parametric error models. When multiple error sources are coupled with the input frequency and amplitude, model construction and parameter tuning become significantly more difficult. To address this issue, this paper presents a structured neural-network-based digital calibration method for pipelined ADCs. The proposed method first separates ADC distortion into analog-front-end degradation that cannot be recovered by the digital back end and deterministic code-domain distortion that can be calibrated. The neural-network training target is then defined as a residual mapping from the raw output code stream to a reference code stream. A frequency-banded lookup table (LUT) is used for static coarse correction, and a condition-aware one-dimensional convolutional neural network (1D-CNN) regresses the remaining local code residual. The network input consists of a 31-sample local code window and six global operating-condition features. The training procedure adopts a two-stage strategy, including coarse training with a behavioral model followed by fine training with measured chip data, together with condition-group-based data partitioning, a frequency-weighted SmoothL1 loss, and residual smoothness regularization. Experimental results on a 14-bit, 1-GS/s pipelined ADC show that, under a representative test condition, the calibrated SNDR increases from 53.96 dB to 72.95 dB and the SFDR increases from 59.07 dB to 90.23 dB. Across a multi-frequency sweep, the average SNDR and SFDR improvements are 19.15 dB and 27.14 dB, respectively. These results demonstrate that defining the learning target according to the error structure and decomposing the calibration responsibility can effectively improve the dynamic performance of pipelined ADCs while retaining substantial calibration gains under limited training-condition coverage.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148837446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low-power CMOS VCO with 3–13.7 GHz tuning and –89.6 dB/Hz phase noise using current-starved negative skew topology","authors":"Chokkakula Ganesh,&nbsp;Asisa Kumar Panigrahy,&nbsp;Rambabu Kusuma,&nbsp;D. Sudha,&nbsp;Aruru Sai Kumar,&nbsp;Shridhar B. Devamane","doi":"10.1007/s10470-026-02620-3","DOIUrl":"10.1007/s10470-026-02620-3","url":null,"abstract":"<div><p>This work proposes a high-performance Current-Starved Negative-Skewed Voltage-Controlled Oscillator (CSNS-VCO) with design optimization targeted at wideband frequency synthesis in advanced CMOS technologies. Classic ring-oscillator VCOs suffer from limited delay controllability, weak voltage-to-frequency gain, and reduced oscillation amplitude under nanoscale supply and device variations. The proposed topology utilizes a hybrid delay-cell architecture that integrates current-starved inverting stages with a negative-skewed feedback path to augment the effective transconductance and reduce transition time. By redistributing the charging and discharging currents through controlled skewing along with multi-node current starvation, the design achieves higher sensitivity of delay modulation compared to conventional inverter-based and current-starved VCOs. The proposed CSNS-VCO was fabricated in CMOS and allows a control voltage between 0.6 V and 7.5 V, thus giving the span of frequency tuning between 3 GHz and 13.7 GHz. This represents an 80% increase in tuning range and a 52% improvement in maximum oscillation frequency as compared to conventional architectures. The oscillator exhibits phase-noise performance of –89.612 dB/Hz, power consumption of 171.043 μW, and propagation delay of 13.75 ns, hence yielding an attractive trade-off among tuning bandwidth, energy efficiency, and spectral purity. Due to its compact topology, wide tuning dynamic, and robustness under process and voltage variations, the proposed CSNS-VCO is a likely candidate for integration in PLLs, adaptive clock generators, RF front-ends, and multi-standard wireless communication systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive system of wide-band antennas for IoT applications based on renewable energy","authors":"Rania Hamdy Elabd,&nbsp;Amir Kamal Salama,&nbsp;Ahmed Jamal Abdullah Al-Gburi","doi":"10.1007/s10470-026-02638-7","DOIUrl":"10.1007/s10470-026-02638-7","url":null,"abstract":"<div><p>To ensure convenient access to application data in Internet of Things (IoT) systems, seamless integration with wireless communication technologies is essential. This research proposes two broadband microstrip antennas—one for transmission and the other for reception—operating in the 2.4 GHz Industrial, Scientific, and Medical (ISM) band for IoT applications. The transmitting antenna, with dimensions of 42 × 42 × 1.6 mm³, features a U-shaped radiating structure fed by a microstrip transmission line. To reduce the antenna size and control the bandwidth (BW), a semicircular defective ground structure (DGS) was etched beneath the radiating patch. Furthermore, a T-shaped stub was incorporated at the centre of the U-shaped radiating element to achieve wideband operation. The receiving antenna measures 45 × 38 × 1.75 mm³ and consists of a circular ring with eight smaller circular rings distributed on its surface. In addition, a positive-sign-shaped structure with a central circular hole was introduced to further enhance the bandwidth. The antenna employs a circular ring-based fractal configuration, while the positive-sign structure, connected to the partial ground plane, reduces the capacitive reactance and further broadens the operating bandwidth. At 2.4 GHz, the transmitting and receiving antennas achieve radiation efficiencies of 90% and 95%, respectively, with corresponding gains of 2.5 dBi and 4.5 dBi. The transmitted and received power at 2.4 GHz was measured and compared with that of a conventional dipole antenna to evaluate the proposed antennas’ performance and suitability for IoT applications. To promote an environmentally friendly and energy-efficient solution, the antenna system was powered by a solar panel. It was integrated with a 2.4 GHz radio-frequency (RF) module and IoT sensors to validate its practical performance. Experimental results demonstrate that the proposed antenna system provides a compact size, broad fractional bandwidth, and reliable performance, making it a promising candidate for IoT applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel design of high throughput power efficient multiply accumulate unit","authors":"M Jayasanthi,&nbsp;R Kalaivani,&nbsp;Kilvani Palanisamy Sampoornam,&nbsp;Vijay Nath","doi":"10.1007/s10470-026-02629-8","DOIUrl":"10.1007/s10470-026-02629-8","url":null,"abstract":"<div><p>The demand for high-performance hardware accelerators is growing, which are widely used nowadays for implementation of Deep Learning methods like that of Convolutional Neural Networks (ConvNet / CNN) on reconfigurable devices. The Multiply-Accumulate (MAC) units are the warhorses behind the remarkable speed and efficiency of convolution operations. Double MAC approach combines two units of MAC operations into a single Digital Signal Processing module of a reconfigurable Field Programmable Gate Arrays (FPGA), thereby increasing the throughput of Convolutional Neural Network accelerators. By dynamically adjusting the precision of MAC operations to 4-bit, 8-bit, and 16- bit fixed and floating-point representations, MAC units can be optimized for efficient resource utilization and power consumption. In this paper, a Double multiply-accumulate unit, dynamically changing precision with 8-bit and 16-bit, is proposed. By leveraging the inherent parallelism and pipelining capabilities of Field Programmable Gate Arrays (FPGA), Double multiply-accumulate approach optimizes the utilization of hardware resources while minimizing the power consumption. The flexible precision scaling in the proposed work proves advantageous in convolution layers, where greater precision is required for final classification and smaller precision in initial stage. Simulation, Synthesis and FPGA Implementation of the proposed Double MAC unit with dynamic precision scaling have been done and it is found successful. The proposed Double MAC approach has showed twofold improvement in throughput and 15% improvement in power consumption. These techniques are highly useful for fast data processing in wireless communication.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards an energy efficient and Robust Bilayer architectures of QCA based adders, subtractors and hybrid circuits","authors":"Javeed Iqbal Reshi,&nbsp;Farooq A Khanday,&nbsp;M. Tariq Banday,&nbsp;Salma Yaqoob","doi":"10.1007/s10470-026-02637-8","DOIUrl":"10.1007/s10470-026-02637-8","url":null,"abstract":"<div><p>Quantum-dot Cellular Automata (QCA) is considered one of the most promising post-CMOS nanotechnologies to realize ultra-dense, low-power, and high-speed digital logic. The XOR gate is one of the basic logic modules in QCA-based circuits. It has a major effect on the performance of adders, subtractors, and hybrid combinational logic circuits. However, conventional XOR structures suffer from high cell overhead, long routing resources, and high propagation delay. To overcome these limitations, we propose a compact and efficient bi-layer XOR gate design. The proposed design is simple and highly efficient. This ultra-minimal three-input XOR gate comprises of nine cells in the first layer and one cell in the second layer, achieving a compact form factor while substantially reducing routing complexity. Using this three input XOR, we further design space optimized adder, subtractor and adder-subtractor organizations, offering improved layout compactness over the nearest prior-art designs. All circuits employ a bilayer configuration, avoiding signal crossing and preserving signal integrity. The functional verification (with QCADesigner 2.0.3 software) shows that all types of logical functions in their XOR, adder, subtractor, and hybrid versions are respected. The suggested layout achieves an 8.33% improvement in cell population in comparison with the best prior designs. The evaluation of energy performance shows that the proposed designs outperform the leading existing architectures by 13.55%, 14.55% and 48.02%. The proposed circuits exhibit high defect tolerance, allowing reliable operation in presence of faults. The proposed architectures demonstrate robust thermal stability and maintain reliable operation over a wide range of operating temperatures. The designs preserve strong polarization and stable signal propagation despite thermal variations, ensuring consistent logic functionality.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and simulation of a mixed-signal separation technology based on PSPICE for TI","authors":"XianDe Huang","doi":"10.1007/s10470-026-02626-x","DOIUrl":"10.1007/s10470-026-02626-x","url":null,"abstract":"<div><p>This paper presents the design and simulation of an analog signal separation technology. The circuit features a novel architecture with independently adjustable center frequencies. Simulation results demonstrate that such device has better effect than that of the similar signal separation system and is easy to be designed. This technology targets signal separation under conditions that the frequency range, waveform, amplitude and quantity of signals are specified. The main research contributions include the following: (1) Time–Frequency Analysis of Mixed Signals: A waveform identification scheme is developed by analyzing the characteristics of mixed signal C in the time–frequency domain. Precise algorithms and logical processing ensure the accuracy and reliability of the analysis results. (2) Signal Recovery and Synchronization: An effective signal separation and recovery mechanism are designed to ensure precise reconstruction of the separated signals. Simultaneously, a synchronized display function is implemented to match the original signal in frequency with zero drift, enabling intuitive signal comparison and analysis. (3) Flexible System lmplementation: A configurable system architecture is proposed to accommodate diverse waveforms and frequencies. Optimized algorithms and hardware resource allocation ensure efficient processing of various signals, delivering stable and reliable performance. The designed signal separation device fully meets the requirements for signal separation: input and output signals are separable, synchronized in frequency, and free from drift.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced spectrum sensing and management in 6G cognitive radio using quantum reinforcement learning and magnificent frigate serval optimization","authors":"Suriya Murugan,&nbsp;T. R. Lekhaa,&nbsp;K. Swetha,&nbsp;A. Roshini","doi":"10.1007/s10470-026-02633-y","DOIUrl":"10.1007/s10470-026-02633-y","url":null,"abstract":"<div><p>With the rapid advancement of Sixth Generation (6G) wireless communication systems, spectrum sensing is performed in Cognitive Radio Networks (CRN) to reliably identify spectrum holes in cognitive radios. In spectrum sensing, the idle frequency bands of the primary user are determined, and the secondary user is allowed the licensed spectrum without giving any interference to the primary user. Recently, various techniques have been used to utilize the underutilized spectrum bands fully for the prevention of essential radio demands from being denied. However, these techniques failed to increase the sensing performance by reducing power consumption. This paper presents a Quantum Reinforcement Learning_Magnificent Frigate Serval Optimization Algorithm (Quantum RL_MagFSOA) for spectrum sensing and management in 6G CRN. Here, the 6G cellular network with a dual-layer authentication procedure is considered. The Magnificent Frigate Serval Optimization Algorithm (MagFSOA) is designed for Master Blockchain Controller (MBC) selection. Then, sufficient spectrum access is obtained by spectrum sensing using Quantum Reinforcement Learning (Quantum RL) and predicting channel state information using Long Short-Term Memory-Multilayer Perceptron (LSTM-MLP). Following this, secure routing is performed using MagFSOA based on different parameters. Further, the Quantum RL_MagFSOA attained prediction accuracy, error rate, and power consumption of 95.469%, 4.531%, and 80.064 Watts.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PVT-robust dynamic comparator calibration using time-domain offset extraction and hardware-compiled perceptron inference","authors":"Angel Garg,&nbsp;Abhishek Sheoran,&nbsp;Anil Singh","doi":"10.1007/s10470-026-02636-9","DOIUrl":"10.1007/s10470-026-02636-9","url":null,"abstract":"<div><p>In this work, a single-pass, hardware-compiled foreground offset calibration architecture for StrongARM dynamic comparators, targeting sub-10 mV input-referred offset at typical operating corners and bounded below 18 mV across the full process, voltage, and temperature (PVT) envelope, in 180 nm CMOS, is presented. The proposed method combines a custom single-layer perceptron, an on-chip time-to-digital converter (TDC), and a digitally controlled capacitor array for calibration. During the initial calibration phase, the comparator offset is measured as a timing deviation at the zero-crossing instant using the on-chip TDC; this timing value is then fed to the neural network, which predicts the optimal capacitor configuration in a single inference pass. The perceptron is synthesized to fixed integer weights with no hidden layer, eliminating iterative finite-state-machine (FSM) search, floating-point computation, and memory elements. By employing time-domain offset measurement and automatically generated capacitor settings, the proposed method eliminates time-consuming manual tuning and achieves precise foreground offset compensation without impacting normal conversion speed. Monte Carlo analysis at the TT corner (1.8 V, 27<span>(^{circ })</span>C, <span>(N=250)</span>) demonstrates that the 3<span>(sigma)</span> envelope of the mismatch-induced input-referred offset distribution is reduced from approximately 39 mV pre-calibration to 7 mV post-calibration, corresponding to an 82% reduction in distribution spread; the pre-calibration sample mean (<span>(mu _{textrm{MC}}approx 10)</span> mV) is consistent with the nominal TT result of Table 10. Across full PVT sweep, post-calibration offset remains below 18 mV in worst-case conditions. Reported area numbers are pre-layout estimates from synthesized cell-level areas; the total estimated circuit area is 447 <span>(mu)</span>m<span>(^2)</span>, with neural inference logic occupying 35 <span>(mu)</span>m<span>(^2)</span> (8%) and consuming 12 <span>(mu)</span>W, making the architecture suitable for high-speed, high-resolution mixed-signal systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and performance analysis of Ka band LNA for continuous wave cloud radar receiver application","authors":"K. Suganthi,&nbsp;S. Kayalvizhi,&nbsp;A. V. M. Manikandan,&nbsp;S. Malarvizhi","doi":"10.1007/s10470-026-02616-z","DOIUrl":"10.1007/s10470-026-02616-z","url":null,"abstract":"<div><p>This Paper discusses the design circuit of Ka-band LNA CMOS Cascode Resistive Shunt Feedback (CCRSF) for the frequency range 26 GHz—28 GHz. Design steps, small-scale equivalent models and analytical expressions are derived. The design verification for operation in K_a band for the cloud RADAR receiver application is presented. For the proposed circuit, a simulation was carried out and compared with theoretical values. Narrowband LNAs offer low power consumption and low noise performance [14]. Wideband LNAs are suitable for larger bandwidths and signals with a large amount of noise. Wideband LNA designs are preferable for Ultra-Wideband (UWB), Cognitive Radio (CR), and Software-Defined Radio (SDR) communication system applications. A cascode configuration is employed with a resistive shunt-feedback topology, as this provides wide bandwidth, high gain, wideband input matching with minimum return loss, and low NF, thereby improving receiver sensitivity. By combining the cascode configuration with the resistive shunt feedback technique, a CCRSF LNA tunable to 28 GHz (mmW) was designed. Comparison results demonstrate that the proposed LNA employs a CCRSF design suitable for a cloud RADAR receiver in the millimeter Wave (mmW) range. The reported gain value is 33.2 dB, NF of 4 dB, power of 22.3 mW, and captured area of 0.399 mm². The novelty lies in the design of LNA for Cloud CW RADAR operation at mmW frequency, with low noise figure, which is not reported earlier in other literature.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA Implementation and Performance Enhancement of FIR Filter with Hybrid FinFET-GDI logic based Carry Select Adder","authors":"T. Kalavathi Devi,&nbsp;S. Umadevi,&nbsp;M. Madhan Mohan,&nbsp;K. N. Baluprithviraj,&nbsp;A. Stephen Sagayaraj,&nbsp;P. Sakthivel","doi":"10.1007/s10470-026-02630-1","DOIUrl":"10.1007/s10470-026-02630-1","url":null,"abstract":"<div><p>Digital Signal Processing (DSP) plays a crucial role in applications ranging from communications to multimedia. Finite Impulse Response (FIR) filters are widely used in audio, biomedical, and other signal processing domains, making their efficient implementation highly important. This work proposes the design of a low-power FIR filter on a Field Programmable Gae Array (FPGA) platform using the Carry Select Adder (CSLA) architecture combined with hybrid FinFET-GDI (Gate Diffusion Input) logic. The CSLA, with its parallelism and efficient carry handling, offers significant advantages for low-power DSP circuits. By optimizing the addition operation within the FIR filter, notable power savings are achieved. The integration of hybrid FinFET-GDI technology further enhances power-performance efficiency while reducing computation time. FPGA implementation on a Zynq 7000 board, supported by simulations in Tanner tool with 45nm technology and verification in Xilinx Vivado, confirms these improvements. Results show a 15% reduction in adder power consumption and a 16% reduction in FIR filter computation time. This research work demonstrates the effectiveness of combining CSLA with FinFET-GDI logic for low-power FIR filter design, contributing to advanced DSP hardware optimization.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148719118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}