Analog Integrated Circuits and Signal Processing最新文献_第4页

Reducing delay and resistance of GNR based interconnect using insertion of buffers

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02346-8

Subrata Das, Debesh Kumar Das, Soumya Pandit

{"title":"Reducing delay and resistance of GNR based interconnect using insertion of buffers","authors":"Subrata Das, Debesh Kumar Das, Soumya Pandit","doi":"10.1007/s10470-025-02346-8","DOIUrl":"10.1007/s10470-025-02346-8","url":null,"abstract":"<div><p>As devices get extremely miniaturized at deep sub-micron design levels, the interconnections between logic blocks significantly influence the overall delay, power dissipation, and area of the system. Surface and grain-boundary scattering, high mobility degradation, higher leakage power, and considerable dopant variation as a result of continuous scaling all contribute to a rise in interconnect resistivity. Due to the superior electrical, mechanical, and thermal properties of graphene nanoribbon (GNR) material, GNR-interconnects may be viable substitutes for copper in future interconnects. Unlike traditional copper-interconnect, the routing in GNR-intrconnect is different. Recently routing with GNR-interconnect have been studied in different literatures with the objectives to reduce interconnect delay and resistance. In order to cope with the system of high speed and less area, interconnect-delay and resistance are needed to be further optimized. In this paper we discuss the issue of insertion of buffers in GNR-interconnect and show that proper insertion of buffers in GNR-interconnect may decrease both interconnect delay and resistance significantly. Whereas in traditional copper-interconnect only delay is reduced by insertion of buffers. We also discuss that the signal and power integrity as well as the stability also improve with the insertion of buffers. We propose an algorithm for proper insertion of buffers to decrease both of them. Elmore delay model is used to compute the delay of GNR interconnects. We observe the minimum 30% and 40% reduction in the interconnect resistance and the interconnect delay respectively in all test cases. The computational worst case time complexity of the algorithm proposed in this manuscript is <span>({mathcal {O}}({n^3}))</span>, where n is the number of terminals in the routing.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integration of metamaterials for quintuple band-notched ultra-wideband antennas

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02355-7

Sapna Arora, Sharad Sharma, Rohit Anand, Anupma Gupta, Ramesh Kumar, Ahmed Jamal Abdullah Al-Gburi

{"title":"Integration of metamaterials for quintuple band-notched ultra-wideband antennas","authors":"Sapna Arora, Sharad Sharma, Rohit Anand, Anupma Gupta, Ramesh Kumar, Ahmed Jamal Abdullah Al-Gburi","doi":"10.1007/s10470-025-02355-7","DOIUrl":"10.1007/s10470-025-02355-7","url":null,"abstract":"<div><p>This paper presents an elliptical monopole antenna integrated with metamaterial structures to achieve band-notched characteristics. Five narrowband spectrums are notched to mitigate interference in the ultra-wideband (UWB) spectrum. Satellite communication in the C-band (3.7 to 4.2 GHz) and the wireless local area network (WLAN) band (5.15 to 5.35 GHz) are suppressed by etching dual elliptical split-ring resonators (ESRRs) into the monopole radiator. A 2-via dual-slot electromagnetic band-gap (EBG) structure is designed on the left side of the feed line, which results in the rejection of the INSAT band (4.5 to 4.7 GHz) and the upper WLAN band (5.725 to 5.825 GHz). Additionally, the ITU band (7.95 to 8.55 GHz) is rejected by implementing a step-impedance resonator (SIR) on the right side of the feed line. The proposed antenna achieves a 10 dB impedance bandwidth of 8.5 GHz, covering the frequency range from 2.5 to 11.0 GHz, with miniaturized dimensions of 0.317λ × 0.317λ × 0.007λ. A mathematical model is employed to explain the behavior of the notched frequencies and is validated through the simulated surface current distribution. Across the entire passband, a consistent gain of 3 dB is achieved. The proposed structure is well-suited for UWB communication applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Action detection of objects devices using deep learning in IoT applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02350-y

Sabir Rustemli, Ahmed Yaseen Bishree Alani, Gökhan Şahin, Wilfried van Sark

{"title":"Action detection of objects devices using deep learning in IoT applications","authors":"Sabir Rustemli, Ahmed Yaseen Bishree Alani, Gökhan Şahin, Wilfried van Sark","doi":"10.1007/s10470-025-02350-y","DOIUrl":"10.1007/s10470-025-02350-y","url":null,"abstract":"<div><p>Internet of Things (IoT) technology is the communication and communication of smart technological devices with each other. However, with the development of the Internet of Things (IoT), the number of smart applications and interconnected devices is increasing day by day. Deep Learning (DL) method has become necessary to process the large amount of raw data collected and to further improve intelligence and application capabilities. It is seen that the majority of researchers focus on action detection. Standard Deep Learning techniques are difficult to use in IoT devices as Deep Learning applications require high CPU, RAM and storage. In this study, an action detection technique has been developed directly on the edge device by enabling the use of deep learning techniques in IoT devices. This technique, as a representation of neural networks, divides it into on-board computers. Visual action detection is one of the critical components of a smart city. High processing capacity and storage requirements severely limit comprehensive and precise monitoring within the IoT and edge computing framework. The structure proposed in this paper suggests the deployment of micro deep learning algorithms to the latest IoT and embedded devices, including the utilisation of minimal computing resources such as processor, power and memory, with a contribution to IoT and embedded device activities in action detection. The systematic analysis shows that many IoT devices can be applied to the proposed optimisation design. The proposed model is much smaller in size than existing models.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02350-y.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power factor correction in SMPS with optimized converter: a hybrid optimization approach

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-25 DOI: 10.1007/s10470-025-02328-w

A. Anbazhagan, R. RamaPrabha

{"title":"Power factor correction in SMPS with optimized converter: a hybrid optimization approach","authors":"A. Anbazhagan, R. RamaPrabha","doi":"10.1007/s10470-025-02328-w","DOIUrl":"10.1007/s10470-025-02328-w","url":null,"abstract":"<div><p>In this research work, a novel hybrid optimization model based on an optimized Mahafzah controller is introduced for power factor correction (PFC). The precision, speed, and stability are improved by the overlapping dc–dc SEPIC converter. Additionally, the control settings of the Mahafzah controller will be adjusted using the new hybrid optimization model to improve the system's response time. Additionally, the control parameters of the Mahafzah controller are adjusted using the new hybrid optimization model to improve the system's response time. The proposed hybrid technique is the hybrid methodology of Artificial Gorilla Troops Optimizer (GTO) and Tree Seed Algorithm (TSA) and hence it is named as GTO–TSA technique. Finally, the proposed system's performance characteristics are examined and contrasted with those of traditional optimization algorithms. At that point, the performance of the suggested technique has been tested in the MATLAB program and is in contrast with that of other methods already in use. The proposed method outperforms existing algorithms across a wide range of input voltages, with a power factor ranging from 0.98 to 0.995 and %THD (Total harmonic distortion) with lower values ranging from 1.6 to 1.15. Similarly, when the load resistance is varied, the proposed method has the highest power factor of 0.981–0.999 and the lowest %THD of 18.0 to 1.2 compared to other algorithms.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A power traces based hardware trojan detection using deep artificial neural network

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-21 DOI: 10.1007/s10470-025-02351-x

Priyadharshini Mohanraj, Saravanan Paramasivam, Prashanth Sathyamoorthy

引用次数: 0

Wave active filter: a state-of-the-art review with odd and even order filter implementation

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-19 DOI: 10.1007/s10470-025-02340-0

Prerna Rana, Ashish Ranjan

{"title":"Wave active filter: a state-of-the-art review with odd and even order filter implementation","authors":"Prerna Rana, Ashish Ranjan","doi":"10.1007/s10470-025-02340-0","DOIUrl":"10.1007/s10470-025-02340-0","url":null,"abstract":"<div><p>This scientific literature survey aims to provide a detailed overview of Wave Active Filter (WAF), including sequential growth of the higher-order filter design using voltage mode and current mode design. This survey paper elaborates on a step-by-step procedure for the wave variable approach for filter design with mathematical analysis. In addition, this work specifically focuses on developing WAF designs using different active blocks. Higher-order WAF designs using modern active blocks are well recorded in this survey paper for better visualization. In literature, third-order and fourth-order WAF implementations are mainly enriched. Hence, an OTA-based WAF is designed for lower- to higher-order filters, demonstrating their efficacy for multifunctional applications such as Wave Active Low Pass Filter (WALPF), Wave Active High Pass Filter (WAHPF), and Wave Active Bandpass Filter (WABPF) using OTA. Besides the theoretical foundations, simulation, and experimental test results are also performed to validate the workability of the OTA-based WAF. The frequency responses of WALPF, WAHPF, and WABPF are demonstrated for the second to sixth orders. The functionality of the OTA-based WAF is verified through frequency spectrum analysis and Monte Carlo simulations. This paper ultimately offers an extensive review of the WAF design process, including mathematical analysis and practical realizations. It provides insights into WAF theory, its benefits, limitations, and potential for future advancements in high-order filters.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02340-0.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Crescent shaped novel 4 × 4 port MIMO design with defected ground structure for multiband sub 6 GHz applications

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-19 DOI: 10.1007/s10470-025-02306-2

P. Sushma Chowdary, Sampad Kumar Panda, V. Praveen Naidu

{"title":"Crescent shaped novel 4 × 4 port MIMO design with defected ground structure for multiband sub 6 GHz applications","authors":"P. Sushma Chowdary, Sampad Kumar Panda, V. Praveen Naidu","doi":"10.1007/s10470-025-02306-2","DOIUrl":"10.1007/s10470-025-02306-2","url":null,"abstract":"<div><p>A Quad port MIMO antenna resonating at sub-6 GHz 5G band is designed by utilising FR4 epoxy material having a dielectric constant of 4.4 and thickness of 1.6 mm. Four identical crescent shaped radiating elements fed by utilising a microstrip feed line are designed by utilising the finite element method based high frequency structure simulator. The antenna parameters are characterised by utilising sets of real measurements to validate the antenna design and modelling. Chemical etching has been utilised for fabricating the quad port antenna on a FR4 substrate. Vector network analyser has been used for measuring the scattering and transmission coefficients. As well as, an anechoic chamber has been used for measuring the far field radiations and the gain of the antenna under test. The basic antenna is a part of the quad-port structure consists of a crescent shaped circular patch with a defected ground structure and are fed individually. MIMO ability is obtained by arranging 4 identical antenna elements in a successive rotational means for obtaining good polarization diversity. The connected ground between the antenna elements is obtained by subtracting 4 circular slots from the ground plane by maintaining a common ground plane. None of the slots touches each other thus ensuring the common reference while maintaining the inter isolation better than 15 dB. The antenna demonstrated maximum gain and efficiency of 4.59dBi and 90%, respectively besides attaining a 10-dB impedance bandwidth of 2–6.2 GHz and ECC < 0.01. Finally, the quad-port compact MIMO antenna is designed, simulated, fabricated and tested, it shows that the antenna is useful for n1, n40, n41, n77, n78 and n79 5G bands. This bandwidth makes the antenna useful for Sub-6 GHz 5G wireless applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dynamic energy consumption using multiobjective genetic algorithm based FFT for implantable cardiac pacemakers

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-15 DOI: 10.1007/s10470-025-02342-y

S. Nagakumararaj, S. Baskar

{"title":"Dynamic energy consumption using multiobjective genetic algorithm based FFT for implantable cardiac pacemakers","authors":"S. Nagakumararaj, S. Baskar","doi":"10.1007/s10470-025-02342-y","DOIUrl":"10.1007/s10470-025-02342-y","url":null,"abstract":"<div><p>The development of miniature electronic devices that are implanted directly in heart is made possible by advancements in enrichment of high-density power electronic technologies. It include pacing devices to maintain normal heart rates, long-term rhythm analysis tools for detecting arrhythmias in cases of unexplained syncope, and heart failure tools that allow for real-time monitoring of cardiac pressures to identify and warn against early fluid overload. This paper proposes, Improved Notch Filter to mitigate noise contained by the recorded electrocardiogram (ECG) signal. Fast Fourier Transform (FFT) spectrum analysis approach, which is critical in embedded biomedical applications is engaged to detect patterns. To achieve low power operation, FFT-based R-peak signal processing is typically computed by Application Specific Integrated Circuits in deeply integrated systems such as cardiac pacemakers. The entire operating life cycle of pacemaker adopts FFT based feature extraction and classification which in turn consumes a considerable part of energy. This insists on the need for power optimization in FFT algorithm and hence a meta-heuristic multi-objective Genetic Algorithm is incorporated with FFT for improving arithmetic computation efficiency. The proposed approach considers the inherent spatial properties of ECG signals for efficient generation of frequency spectrum by FFT and also the number of execution cycles gets reduced. The framework is examined using MATLAB and the generated results obtained reveal that, the suggested work enables improved battery life for the cardiac pacemaker with reduced dynamic power consumption.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143423048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid technique vienna rectifier based topology for FCS electric vehicle using AC–DC converter

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-15 DOI: 10.1007/s10470-025-02312-4

M. P. Mohandass, S. Manoharan

{"title":"Hybrid technique vienna rectifier based topology for FCS electric vehicle using AC–DC converter","authors":"M. P. Mohandass, S. Manoharan","doi":"10.1007/s10470-025-02312-4","DOIUrl":"10.1007/s10470-025-02312-4","url":null,"abstract":"<div><p>This manuscript presents a novel approach for a fast electric vehicle (EV) charging station, employing AC to DC converter and Vienna rectifier (VR) based topology. The proposed EJS-RDF technique integrates an enhanced Jellyfish Search (EJS) and random decision forest (RDF), which offers a unique control strategy. Notably, a unidirectional boost converter replaces traditional diode-bridge rectifiers, enhancing power factor, reducing harmonics, and regulating DC voltage. Buck-type converters provide wide control range and Power Factor Control (PFC). By leveraging EJS technology, the switching voltage is reduced based on the output voltage range. Initial factors, including duty cycle, current, and voltage, are considered, with the random decision forest optimizing the duty cycle for an optimal outcome. The ultra-fast charging station (CS) incorporates an intermediate storage battery to improve the pulsations of power and serves as energy storage for renewables, thereby increasing system efficiency. The proposed EJS-RDF technique outperforms other optimization algorithms, achieving a Total Harmonic Distortion (THD) of 3.50% and 3.80% in G2V and V2G modes, respectively, surpassing Wild Horse Optimization (WHO), Side-Blotched Lizard Algorithm (SBLA), and Sequential Minimal Optimization (SMO) with THD values of 6.75%, 6.79%, 8.34%, 9.32%, 10.62%, and 15.75% in both operational modes, showcasing superior performance. The manuscript concludes with implementation in MATLAB/Simulink, aligning with journal requirements for acronym consistency. This article's significance lies in its innovative hybrid strategy, addressing power quality issues and optimizing control parameters for efficient and reliable EV charging.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143423047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resources using multi-input DC-DC converter topology for optimal utilization of a novel step-up interconnected enhanced technique renewable energy

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-02-15 DOI: 10.1007/s10470-025-02320-4

R. Senthil Kumar, C. S. Subash kumar, M. Lakshmanan, M. P. E. Rajamani

{"title":"Resources using multi-input DC-DC converter topology for optimal utilization of a novel step-up interconnected enhanced technique renewable energy","authors":"R. Senthil Kumar, C. S. Subash kumar, M. Lakshmanan, M. P. E. Rajamani","doi":"10.1007/s10470-025-02320-4","DOIUrl":"10.1007/s10470-025-02320-4","url":null,"abstract":"<div><p>This manuscript proposes an enhanced method for interconnected Renewable Energy Sources (RESs) to microgrid (MG) using a step-up multi-input DC to DC converter topology. The utilized interconnected sources are batteries, wind turbines, photovoltaic (PV). The proposed technique is Firebug Swarm Optimization. FSO gets inspired by the firebugs’ reproductive swarming movement. FSO’s swarming behavior is improved by employing two operators, crossover and mutation. It is hence known as the Enhanced FSO (EnFSO) approach. The proposed converter provides improved converter efficiency, fewer switching losses and efficient utilization of RESs. The proposed EnFSO method is utilized to determine the exact gain parameter of a proportional integral controller in the view of error value as reactive power and active power. The proposed method mitigates the error and manages the power flow in an optimum way. Battery is one of energy source utilized to compensate and permit the renewable power system units to continue running in output power of stable and steady. The proposed strategy is used in MATLAB or the Simulink tool and compared with other current approaches.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143423112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0