Analog Integrated Circuits and Signal Processing最新文献_第4页

A 2-way interleaving 3-tap analog feedforward equalization for high-speed analog multiplexing 用于高速模拟多路复用的2路交叉3分路模拟前馈均衡

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-23 DOI: 10.1007/s10470-025-02387-z

Thomas Gorzka, Mark Ingels, Xin Wang, Joris Van Kerrebrouck, Nishant Singh, Guy Torfs, Johan Bauwelinck, Jan Craninckx, Piet Wambacq

引用次数: 0

Optimised elliptic curve cryptography architecture for improved V2x communication 优化椭圆曲线加密架构，改进V2x通信

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-23 DOI: 10.1007/s10470-025-02378-0

S. Vijayakumar, M. Mathivanan, M. Sathiya, A. Kamaraj

{"title":"Optimised elliptic curve cryptography architecture for improved V2x communication","authors":"S. Vijayakumar, M. Mathivanan, M. Sathiya, A. Kamaraj","doi":"10.1007/s10470-025-02378-0","DOIUrl":"10.1007/s10470-025-02378-0","url":null,"abstract":"<div><p>Today’s world, communication devices installed in roadside, pedestrians, and all moving entities can able to communicate with each other, through the vehicular to anything communication called as V2X. These communications have to taken in to account security and privacy issues also. The aim of this research work is to provide secured cryptographic techniques to help the vehicles in obtaining necessary keys and information from Roadside Units (RSU), the data network, or from other vehicles while also ensuring a highest security in different ways of vehicular communication (V2I, V2V, and V2N). One of the many cryptographic methods that provide the solution to the objective is Elliptic Curve Cryptography (ECC). The fundamental operations of ECC such as point multiplication and point addition are carried out for 256-bits; also the proposed ECC processor follows the Koblitz curve secp256k1. “Divide and Conquer” is being followed in Karatsuba algorithm to increase speed of multiplication process. The incorporation of Pipelining also increases the speed of the multiplication on the ECC processor with additional area overhead. The novel Karatsuba ECC processor operates at a clock frequency of 238.40 MHz, computing point multiplication of 256-bit in 0.937 ms, throughput of 273.21kbps and area is 8.42 k slices in a FPGA Virtex-7. Integrating Pipelining in the proposed system increases the clock frequency up to 7.97%. Because of it, the time consumption is reduced by 9.90% and throughput is increased by 10.99%. This novel ECC processor performs well compared to the existing methods in terms of area-delay product, operating frequency, throughput and area.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143865507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SEC-DED-Hsiao code protection for SRAM memories used in space applications 用于空间应用的SRAM存储器的sec - d - xiao代码保护

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02391-3

Ghenam Dahmane, Benabdellah Yagoubi

引用次数: 0

A compact flexible dual band coplanar waveguide fed antenna for 5 G applications 用于 5 G 应用的紧凑型灵活双频共面波导馈电天线

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02393-1

Abhilash S. Vasu, T. K. Sreeja

引用次数: 0

Comparison of the polarity reversal effect of memristor and memristor fuse in 2D cellular nonlinear network 二维元胞非线性网络中忆阻器和忆阻熔断器极性反转效果的比较

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02395-z

Aliyu Isah

{"title":"Comparison of the polarity reversal effect of memristor and memristor fuse in 2D cellular nonlinear network","authors":"Aliyu Isah","doi":"10.1007/s10470-025-02395-z","DOIUrl":"10.1007/s10470-025-02395-z","url":null,"abstract":"<div><p>Memristor sparks interest in neuromorphic and bioinspired systems owing to its dynamic conductance, which resembles chemical synapse. However, the conductivity of a memristor depends strongly on the amount and direction of the flowing charge through it, and it is primarily due to its intrinsic asymmetry. This phenomenon becomes disadvantageous and a massive hindrance to consider memristors in some biomimetic networks, such as memristive grid networks, where sensitivity of direction is important. This drawback can be avoided by using memristor fuse which is formed by connecting two identical memristors anti-serially. To effectively compare the polarity reversal effect of these circuit elements, a network of 2 RC cells in the form of passive neurons coupled by a memristor and then a memristor fuse is considered, thereby allowing to observe and compare the interaction of these circuit elements bidirectionally. The system is studied analytically and the result is visualized in the phase plane. The comparison is done by observing the evolution patterns of the trajectories with respect to the direction of flow of the charge through these circuit elements. In terms of functionality as demonstrated in this paper, the memristor fuse shows a promising symmetry with respect to the quantity and direction of the flowing charge through it.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Off-the shelf components-based inverse memristor emulator and its application in bandwidth extension of memristor emulator 基于现成元件的逆忆阻器仿真器及其在忆阻器带宽扩展中的应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02410-3

Praveen Kumar, Mayank Srivastava

{"title":"Off-the shelf components-based inverse memristor emulator and its application in bandwidth extension of memristor emulator","authors":"Praveen Kumar, Mayank Srivastava","doi":"10.1007/s10470-025-02410-3","DOIUrl":"10.1007/s10470-025-02410-3","url":null,"abstract":"<div><p>The article explores the application of a reverse memristor emulator utilizing easily accessible components. This emulator comprises two Operational Amplifiers (Op-amps), one Operational Transconductance Amplifier (OTA), and two passive elements. The utilization of Op-Amps and OTA renders the circuit effortlessly implementable with commercially accessible Integrated Circuits (ICs), presenting a notable advantage of the suggested architecture. Upon close examination of the proposed design, accounting for terminal parasitics and non-ideal gains, the observed behavior closely matches the ideal characteristics of the circuit. The emulator’s functionality underwent testing in the PSPICE simulation environment, considering the 0.18 μm technology. The credibility of the proposed circuit concept was further substantiated by employing widely available ICs like µA741 and LM13700, with the results extensively discussed. Furthermore, the article showcases an essential application of this emulator by enhancing the bandwidth of a low-frequency memristor emulator. At last, the experimental results are also demonstrated to validate the reported application.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Control of off-board bidirectional plug-in electric vehicle charger using a hybrid optimization approach 使用混合优化方法控制车外双向插电式电动汽车充电器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-22 DOI: 10.1007/s10470-025-02372-6

Manickam Vinoth Kumar, K. Dhayalini

{"title":"Control of off-board bidirectional plug-in electric vehicle charger using a hybrid optimization approach","authors":"Manickam Vinoth Kumar, K. Dhayalini","doi":"10.1007/s10470-025-02372-6","DOIUrl":"10.1007/s10470-025-02372-6","url":null,"abstract":"<div><p>In the modern era, Electric Vehicles (EVs) have gained immense consideration in developed nations due to diminished usage of fossil fuels as well as lessening the release of gases that cause global warming. Radiation of Greenhouse gases in the atmosphere can be diminished by the utilization of EVs. The charging component is essential for PEVs, as they require electricity from the power grid to charge their batteries. With the appropriate control, the existing charger’s converter architecture can offer additional functionalities. The expansion of Off-board fast-CS is the primary cause of the widespread utilization of EVs. The demand for load increases when the EV battery is charged from the grid. This study examines the application of a V2G-enabled bidirectional off-board EV battery charger using the HBIAO and AIChOa algorithm. The HBIAO algorithm inherits the characteristics and features of Honey Badger and Aquila Optimization Algorithm, while AIChOa algorithm inherits the features of Sooty Tern Optimization Algorithm and Chimp Optimization Algorithm (ChOA). The hybrid optimization algorithms assist in the achievement of global optimal solutions, neglecting the local optimal solutions. The proposed EV charger is modeled and simulated in MATLAB/Simulink, and the controller’s efficiency is validated. The simulation findings show that the system can function efficiently compared to various traditional methodologies. With different simulation and testing outcomes, quick dynamic reactions and excellent steady-state system performances can be demonstrated.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143861144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Grey wolf optimization (GWO) based efficient partitioning algorithm VLSI circuits for reducing the interconnections 基于灰狼优化（GWO）的VLSI电路高效划分算法，以减少互连

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-09 DOI: 10.1007/s10470-025-02334-y

R. Pavithra Guru, V. Vaithianathan

{"title":"Grey wolf optimization (GWO) based efficient partitioning algorithm VLSI circuits for reducing the interconnections","authors":"R. Pavithra Guru, V. Vaithianathan","doi":"10.1007/s10470-025-02334-y","DOIUrl":"10.1007/s10470-025-02334-y","url":null,"abstract":"<div><p>Many earlier partitioning studies used underlying partitioning methods to boost speed. As the problems grew in size and complexity, the partitioning technique application was insufficient to give outstanding results. Recent research has demonstrated the potential of multilevel techniques. A multilevel partitioning mechanism repeatedly divides the event until the size of the event is less than the specified limit, at which point it is un-coarsened using a partitioning refinement algorithm. A multi-faceted optimization problem was solved simultaneously in this study using the grey wolf optimization (GWO) technique. This work's methodology is based on information exchange and particle mobility inside a search space. In the partitioning phase of VLSI circuit optimization, multi-objective optimization challenges exist at the physical design level. The following sections present the results of multi-objective optimization of cut size delay and use the swarm technique (GWO). The GWO algorithm effectively solves the NP-hard problem, according to the conclusions of this research. Construct a concurrent multi-objective optimization issue and solve it using a programming technique. The circuit netlist files were utilized in the ISCAS’85 circuit benchmark suite to provide information on the circuit. This approach has much promise in VLSI circuit partitioning.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143809122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and design of an innovative 19.5 GHz active phase shifter architecture, implemented in a 0.13 μm BiCMOS SiGe:C process, for beamforming in 5G applications 分析和设计创新型 19.5 GHz 有源移相器架构，采用 0.13 μm BiCMOS SiGe:C 工艺实现，用于 5G 应用中的波束成形

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-07 DOI: 10.1007/s10470-025-02363-7

Nuraddeen Ado Muhammad, David Cordeau, Jean-Marie Paillot

{"title":"Analysis and design of an innovative 19.5 GHz active phase shifter architecture, implemented in a 0.13 μm BiCMOS SiGe:C process, for beamforming in 5G applications","authors":"Nuraddeen Ado Muhammad, David Cordeau, Jean-Marie Paillot","doi":"10.1007/s10470-025-02363-7","DOIUrl":"10.1007/s10470-025-02363-7","url":null,"abstract":"<div><p>This paper presents the design and implementation of a 19.5 GHz active phase shifter for beamforming. The proposed circuit is based on an original architecture using an Injection-Locked Voltage-Controlled Oscillator (ILVCO) associated with a polyphase filter and followed by a phase selection circuit. This phase shifter is synthesized using the phase selection circuit (PS) for coarse adjustment in the steps of 90° and the injection-locked VCO for a fine-tuning adjustment between ± 45°. According to the post-layout simulation results, the frequency tuning range of the VCO varies from 17.89 to 20.16 GHz in free-running mode. This behaviour allows to obtain a phase shift range of 360° with an injected signal having a power of -8.5 dBm and a frequency of 19.5 GHz. In these conditions, from a 1.3 V supply voltage, the full circuit draws a current of 20.47 mA and the mean output power is equal to − 15.58 dBm on 50 Ω load. The proposed circuit is implemented in a BiCMOS SiGe:C 0.13 μm process and the whole layout has an area of 1.51 mm<sup>2</sup> including all the pads.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143793109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA implementation of intelligent battery management unit (i-BMU) based on dynamic power distribution technique for electric vehicles 基于动态配电技术的电动汽车智能电池管理单元（i-BMU）的FPGA实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-05 DOI: 10.1007/s10470-025-02370-8

R. Daisy Merina, R. Saravana Ram, Lordwin Cecil Prabhaker Micheal

{"title":"FPGA implementation of intelligent battery management unit (i-BMU) based on dynamic power distribution technique for electric vehicles","authors":"R. Daisy Merina, R. Saravana Ram, Lordwin Cecil Prabhaker Micheal","doi":"10.1007/s10470-025-02370-8","DOIUrl":"10.1007/s10470-025-02370-8","url":null,"abstract":"<div><p>Electric Vehicle (EV) efficiency is highly dependent on optimal power management strategies. Conventional Static Power Distribution Techniques limit the vehicle’s range and energy efficiency due to their inability to adapt to dynamic driving conditions. This paper proposes an Intelligent Power Distribution Technique enabled by a Deep Neural Network-based battery management unit (BMU), implemented on an FPGA architecture. The MPSoC efficiently interfaces with multiple sensors, including Hall Effect sensors for speed and voltage measurement, a shunt-based current sensor, and a potentiometer for throttle position detection. Data collection was conducted in Chennai, India, where key parameters such as speed, throttle position, battery voltage, battery current, and GPS coordinates were recorded at 10-min intervals over 30 days. The performance evaluation of the FPGA implementation reveals optimized chip area utilization (97.25 mm<sup>2</sup>) and reduced power consumption (6.391 W) compared to conventional battery management systems. Additionally, an LSTM-based State of Charge (SoC) estimation model was developed, outperforming traditional Coulomb Counting and Kalman Filtering methods with an MAE of 0.0250 and RMSE of 0.0288. Dynamic power distribution techniques further optimized energy consumption across different driving cycles, leading to a notable improvement in EV mileage. Compared to static power allocation, the proposed intelligent power distribution technique achieved an increase of 7.8% (471.09 km) in urban driving, 12.21% (490.33 km) in highway conditions, and 10.8% (484.20 km) in downhill scenarios. Sensitivity analysis of speed and throttle position on battery voltage and current highlights crucial insights for efficient energy management. The proposed i-BMU enhances battery longevity, reduces power consumption, and improves overall EV efficiency, making it a promising solution for next-generation electric mobility.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143784151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0