Analog Integrated Circuits and Signal Processing最新文献_第4页

A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system 使用自适应神经模糊推理系统的 5G 毫米波应用新型宽带、小尺寸和高增益贴片天线阵列

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-25 DOI: 10.1007/s10470-023-02245-w

Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou

{"title":"A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system","authors":"Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou","doi":"10.1007/s10470-023-02245-w","DOIUrl":"10.1007/s10470-023-02245-w","url":null,"abstract":"<div><p>In this paper a wide-band, small size and high gain modified patch antenna array and a single element antenna for fifth Generation (5G) millimetre-wave (mm-wave) applications have been presented. The designing of single element antenna and array antenna is based on the Adaptive Neuro-Fuzzy Inference systems (ANFIS). The ANFIS technique is used to estimate the dimensions of the single element as well as the spacing between patch antenna elements in antenna array. The single element’s operating frequency is 28 GHz, While the array antenna covers the frequency band from 23.6 to 29.2 GHz, resonating at 25 and 28 GHz. The antenna array was designed and simulated using the Rogers RT duroid 5880 Substrate, which has a dielectric constant of 2.2, a loss tangent <span>(tan ( delta ))</span> of 0.0009, and thickness of 0.508 mm. The proposed single element patch antenna has a size of 4<span>(times 4.8)</span> <span>(times)</span>0.508 <span>({text{mm}}^{3})</span> with wideband range from 23 to 38.6 GHz (15.6 GHz) with a gain of 4.17 dB. Based on these properties, the single element is expanded into a six-element array with a compact size of 13.2<span>(times)</span>23.8<span>(times)</span> 0.508 <span>({text{mm}}^{3})</span> in order to enhance the gain and to make the antenna radiation pattern directional. The designed antenna array has a wide-band from 23.6 to 29.2GHz (5.6 GHz) and a high gain of 11 dB, making it as strong candidate for future mm-wave applications.\u0000</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"603 - 618"},"PeriodicalIF":1.2,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02245-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139980196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scalable intelligent median filter core with adaptive impulse detector 具有自适应脉冲检测器的可扩展智能中值滤波器内核

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-25 DOI: 10.1007/s10470-024-02261-4

Nanduri Sambamurthy, Maddu Kamaraju

{"title":"Scalable intelligent median filter core with adaptive impulse detector","authors":"Nanduri Sambamurthy, Maddu Kamaraju","doi":"10.1007/s10470-024-02261-4","DOIUrl":"10.1007/s10470-024-02261-4","url":null,"abstract":"<div><p>This paper introduces a reconfigurable AI-enabled scalable median filter with an adaptive impulse detector designed for FPGA-based real-time imaging systems. Its primary objective is to address the degradation of image quality caused by mixed impulsive noise during real-time image transmission and reception. Existing median filters often struggle to provide real-time image processing results that meet high standards in terms of both accuracy and speed. This approach effectively suppresses noise in real-time images while preserving essential edge details, which are crucial for the performance of real-time imaging systems. The algorithm introduces a novel technique of replacing noisy pixels with the processed central value within the image filtering window. This ensures fidelity to the original pixel, which is vital for applications such as image filter cores. To handle high noise densities in real-time systems, the methodology employs a scalable sorting approach for median filtering and an impulse detector, ensuring robust noise reduction without excessive computational complexity. The AI-enabled scalable median filter system achieves a significant reduction in dynamic power consumption, realizing an impressive 46% decrease in power consumption and an 82% reduction in area compared to the existing system. This is particularly beneficial for addressing resource and power-aware constraints in real-time systems. Comprehensive performance evaluation, including metrics such as PSNR, MSE, IEF, and SSIM, demonstrates the efficacy of the filter in enhancing image quality, a critical factor for the success of real-time imaging systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"425 - 435"},"PeriodicalIF":1.2,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications 用于 FMCW 应用的 80-84.8 GHz PLL，带自动跟踪米勒分频器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-24 DOI: 10.1007/s10470-024-02258-z

Popong Effendrik, Wei-Zen Chen

{"title":"An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications","authors":"Popong Effendrik, Wei-Zen Chen","doi":"10.1007/s10470-024-02258-z","DOIUrl":"10.1007/s10470-024-02258-z","url":null,"abstract":"<div><p>To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FM<sub>error</sub>/BW<sub>chirp</sub> and RMS-FM<sub>error</sub>/(BW<sub>chirp</sub> × f<sub>c</sub> × T<sub>c</sub>) with value of 0.013% and 0.77e−12<b>,</b> respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"523 - 537"},"PeriodicalIF":1.2,"publicationDate":"2024-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02258-z.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 4-D four-wing chaotic system with widely chaotic regions and multiple transient transitions 具有广泛混沌区和多重瞬态转换的四维四翼混沌系统

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-23 DOI: 10.1007/s10470-024-02260-5

Lingyun Li, Zhijun Chai, Yunxia Wang

引用次数: 0

Chip implementation of low-power high-efficient buck converter for battery-powered IOT applications 用于电池供电物联网应用的低功耗高效降压转换器的芯片实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-22 DOI: 10.1007/s10470-023-02204-5

Shih-Chang Hsia, Ming-Ju Hsieh

引用次数: 0

Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application 用于纳米互连应用的热感知电路模型和 MLGNR 性能分析

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-21 DOI: 10.1007/s10470-024-02254-3

Himanshu Sharma, Karmjit Singh Sandha

{"title":"Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application","authors":"Himanshu Sharma, Karmjit Singh Sandha","doi":"10.1007/s10470-024-02254-3","DOIUrl":"10.1007/s10470-024-02254-3","url":null,"abstract":"<div><p>This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"71 - 81"},"PeriodicalIF":1.2,"publicationDate":"2024-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139928283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integration of cascaded controllers for super-lift Luo converter with buck converter in solar photovoltaic and electric vehicle 太阳能光伏发电和电动汽车中超升罗转换器与降压转换器的级联控制器集成

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-20 DOI: 10.1007/s10470-024-02259-y

B. Ashok, Prawin Angel Michael

{"title":"Integration of cascaded controllers for super-lift Luo converter with buck converter in solar photovoltaic and electric vehicle","authors":"B. Ashok, Prawin Angel Michael","doi":"10.1007/s10470-024-02259-y","DOIUrl":"10.1007/s10470-024-02259-y","url":null,"abstract":"<div><p>Power electronic converters are utilized to regulate the charging voltage of electric vehicles (EV) batteries based on photovoltaic (PV), ensuring it falls within the desired range. Nevertheless, multi-port DC-DC converters have encountered challenges like bulky transformers and multiple switches, resulting in reduced reliability. To address these issues, this study presents super lift Luo and buck converter (SLBC) designed for the integration of PV and EV. The DC-DC converter presented in the work, integrated with SLBC, produces both step-up and step-down outputs from single input. The step-up output is achieved through the application of the super-lift method, enabling the elevation of voltage. This method allows for the generation of high-gain voltages using straightforward structures, eliminating the need for additional transformers or electric circuits for control and regulation. For fine tuning the duty cycle of the proposed converter, an efficient control scheme employing a cascaded structure of the TID (tilt integral derivative) with FOPID (fractional order proportional integral derivative with a filter), referred as the cascaded TID-FOPID controller is proposed. The tuning of the cascaded TID-FOPID controller parameters is accomplished using improved Harris Hawks optimization (IHHO). The analysis is carried out in the MATLAB platform and compared to various existing approaches. Analysed parameters include motor torque and speed, converter efficiency across duty cycles (0.1 to 0.6), frequency response, voltage gain comparative analysis among converters at a duty cycle of 0.6, voltage gain, voltage stress, and diode stress comparisons in the proposed converter. The efficiency attained by the proposed method reaches approximately 98%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"449 - 466"},"PeriodicalIF":1.2,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139920981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A floating meminductor emulator using modified differential voltage current conveyor transconductance amplifier and its application 使用改进型差分电压电流传输跨导放大器的浮动记忆电感仿真器及其应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-20 DOI: 10.1007/s10470-024-02257-0

Rupam Das, Shireesh Kumar Rai, Bhawna Aggarwal

{"title":"A floating meminductor emulator using modified differential voltage current conveyor transconductance amplifier and its application","authors":"Rupam Das, Shireesh Kumar Rai, Bhawna Aggarwal","doi":"10.1007/s10470-024-02257-0","DOIUrl":"10.1007/s10470-024-02257-0","url":null,"abstract":"<div><p>In this paper, a modified differential voltage current conveyor transconductance amplifier (MDVCCTA) based meminductor emulator has been proposed. The proposed meminductor is realized using one MDVCCTA, one resistor, and two grounded capacitors that leads to a very simple configuration. The emulator is working for a significant range of frequencies up to 80 MHz. The transient and non-volatility tests are found to be satisfactory. The corner and Monte Carlo analyses are done to verify the robustness of the proposed design. In addition, to assess the endurance of the recommended meminductor emulator, its workability with variations in supply voltage, temperature, and component values has been investigated. The pinched hysteresis loops that are fingerprints for the meminductor emulator are not deformed for any such variations. A comparison of suggested meminductor with those available in literature has been done based on several performance parameters. Two applications that demonstrate the viability of the suggested meminductor emulator have also been comprehended.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 3","pages":"475 - 496"},"PeriodicalIF":1.2,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139921000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC 为指数转换集成电路扩展信号动态范围并降低电源电压

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-19 DOI: 10.1007/s10470-023-02247-8

Naoya Nishiyama, Fumiya Matsui, Yuji Sano

{"title":"Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC","authors":"Naoya Nishiyama, Fumiya Matsui, Yuji Sano","doi":"10.1007/s10470-023-02247-8","DOIUrl":"10.1007/s10470-023-02247-8","url":null,"abstract":"<div><p>In order to compensate for the non-linearity of an electronic device, an exponentiation conversion circuit that can change the power exponent to any value has been proposed. The exponentiation conversion circuit multiplies the logarithmically converted input signal by a power exponent value to perform exponential conversion. As a result, we can obtain the power function characteristic of a power exponent value. This circuit is a small-scale circuit that utilizes the exponential characteristics of the MOSFET subthreshold region. In a conventional circuit, expansion of the signal dynamic range and reduction of the power supply voltage have been an issue. In this paper, it was confirmed by simulation that the signal dynamic range has expanded by optimizing the current density of MOSFETs. In addition, the linearity of the multiplying circuit was improved by feedback produced by the operational amplifier circuits. We proposed reducing its power supply voltage from 6.0 to 3.3 V by a new multiplying circuit that can eliminate the restriction of maximum voltage gain. Our circuit expands its signal dynamic range from 17.5 to 42.7 dB in condition of the power exponent value from 0.50 to 2.0.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 1","pages":"185 - 194"},"PeriodicalIF":1.2,"publicationDate":"2024-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02247-8.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139920953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental Investigation on the Side Mode Injection Locking of a Single-loop OEO under RF Signal Injection 射频信号注入下单环 OEO 侧模注入锁定的实验研究

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-18 DOI: 10.1007/s10470-024-02262-3

Jayjeet Sarkar, Abhijit Banerjee, Gefeson Mendes Pacheco, Nikhil Ranjan Das

引用次数: 0