优化椭圆曲线加密架构,改进V2x通信

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
S. Vijayakumar, M. Mathivanan, M. Sathiya, A. Kamaraj
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引用次数: 0

摘要

当今世界,安装在路边的通信设备、行人以及所有移动的实体都能够相互通信,通过车辆对任何事物的通信称为V2X。这些通信也必须考虑到安全和隐私问题。这项研究工作的目的是提供安全的加密技术,帮助车辆从路边单元(RSU)、数据网络或其他车辆获取必要的密钥和信息,同时确保不同车辆通信方式(V2I、V2V和V2N)的最高安全性。椭圆曲线密码学(ECC)是解决这一问题的众多密码学方法之一。ECC的基本运算如点乘法和点加法是在256位上进行的;所提出的ECC处理器也遵循Koblitz曲线secp256k1。为了提高乘法运算的速度,Karatsuba算法采用了“分治法”。流水线的结合还增加了ECC处理器上的乘法速度,增加了额外的面积开销。新型Karatsuba ECC处理器在FPGA Virtex-7上工作在238.40 MHz的时钟频率下,在0.937 ms内计算256位点乘法,吞吐量为273.21kbps,面积为8.42 k片。将流水线集成到系统中,时钟频率最高可达7.97%。因此,时间消耗减少了9.90%,吞吐量提高了10.99%。这种新型的ECC处理器在面积延迟积、工作频率、吞吐量和面积等方面都优于现有的方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimised elliptic curve cryptography architecture for improved V2x communication

Today’s world, communication devices installed in roadside, pedestrians, and all moving entities can able to communicate with each other, through the vehicular to anything communication called as V2X. These communications have to taken in to account security and privacy issues also. The aim of this research work is to provide secured cryptographic techniques to help the vehicles in obtaining necessary keys and information from Roadside Units (RSU), the data network, or from other vehicles while also ensuring a highest security in different ways of vehicular communication (V2I, V2V, and V2N). One of the many cryptographic methods that provide the solution to the objective is Elliptic Curve Cryptography (ECC). The fundamental operations of ECC such as point multiplication and point addition are carried out for 256-bits; also the proposed ECC processor follows the Koblitz curve secp256k1. “Divide and Conquer” is being followed in Karatsuba algorithm to increase speed of multiplication process. The incorporation of Pipelining also increases the speed of the multiplication on the ECC processor with additional area overhead. The novel Karatsuba ECC processor operates at a clock frequency of 238.40 MHz, computing point multiplication of 256-bit in 0.937 ms, throughput of 273.21kbps and area is 8.42 k slices in a FPGA Virtex-7. Integrating Pipelining in the proposed system increases the clock frequency up to 7.97%. Because of it, the time consumption is reduced by 9.90% and throughput is increased by 10.99%. This novel ECC processor performs well compared to the existing methods in terms of area-delay product, operating frequency, throughput and area.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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