Analog Integrated Circuits and Signal Processing最新文献

{"title":"Design and performance analysis of Ka band LNA for continuous wave cloud radar receiver application","authors":"K. Suganthi,&nbsp;S. Kayalvizhi,&nbsp;A. V. M. Manikandan,&nbsp;S. Malarvizhi","doi":"10.1007/s10470-026-02616-z","DOIUrl":"10.1007/s10470-026-02616-z","url":null,"abstract":"<div><p>This Paper discusses the design circuit of Ka-band LNA CMOS Cascode Resistive Shunt Feedback (CCRSF) for the frequency range 26 GHz—28 GHz. Design steps, small-scale equivalent models and analytical expressions are derived. The design verification for operation in K_a band for the cloud RADAR receiver application is presented. For the proposed circuit, a simulation was carried out and compared with theoretical values. Narrowband LNAs offer low power consumption and low noise performance [14]. Wideband LNAs are suitable for larger bandwidths and signals with a large amount of noise. Wideband LNA designs are preferable for Ultra-Wideband (UWB), Cognitive Radio (CR), and Software-Defined Radio (SDR) communication system applications. A cascode configuration is employed with a resistive shunt-feedback topology, as this provides wide bandwidth, high gain, wideband input matching with minimum return loss, and low NF, thereby improving receiver sensitivity. By combining the cascode configuration with the resistive shunt feedback technique, a CCRSF LNA tunable to 28 GHz (mmW) was designed. Comparison results demonstrate that the proposed LNA employs a CCRSF design suitable for a cloud RADAR receiver in the millimeter Wave (mmW) range. The reported gain value is 33.2 dB, NF of 4 dB, power of 22.3 mW, and captured area of 0.399 mm². The novelty lies in the design of LNA for Cloud CW RADAR operation at mmW frequency, with low noise figure, which is not reported earlier in other literature.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148782175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA Implementation and Performance Enhancement of FIR Filter with Hybrid FinFET-GDI logic based Carry Select Adder","authors":"T. Kalavathi Devi,&nbsp;S. Umadevi,&nbsp;M. Madhan Mohan,&nbsp;K. N. Baluprithviraj,&nbsp;A. Stephen Sagayaraj,&nbsp;P. Sakthivel","doi":"10.1007/s10470-026-02630-1","DOIUrl":"10.1007/s10470-026-02630-1","url":null,"abstract":"<div><p>Digital Signal Processing (DSP) plays a crucial role in applications ranging from communications to multimedia. Finite Impulse Response (FIR) filters are widely used in audio, biomedical, and other signal processing domains, making their efficient implementation highly important. This work proposes the design of a low-power FIR filter on a Field Programmable Gae Array (FPGA) platform using the Carry Select Adder (CSLA) architecture combined with hybrid FinFET-GDI (Gate Diffusion Input) logic. The CSLA, with its parallelism and efficient carry handling, offers significant advantages for low-power DSP circuits. By optimizing the addition operation within the FIR filter, notable power savings are achieved. The integration of hybrid FinFET-GDI technology further enhances power-performance efficiency while reducing computation time. FPGA implementation on a Zynq 7000 board, supported by simulations in Tanner tool with 45nm technology and verification in Xilinx Vivado, confirms these improvements. Results show a 15% reduction in adder power consumption and a 16% reduction in FIR filter computation time. This research work demonstrates the effectiveness of combining CSLA with FinFET-GDI logic for low-power FIR filter design, contributing to advanced DSP hardware optimization.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148719118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"VLSI and FPGA implementation of high-speed Vedic MAC architecture using Han Carlson adder","authors":"J. Banumathi,&nbsp;G. Karthy","doi":"10.1007/s10470-026-02622-1","DOIUrl":"10.1007/s10470-026-02622-1","url":null,"abstract":"<div><p>The capacity of processors to withstand the problems that arise from integrating CPU cores in a single IC is an ongoing requirement for digital signal processors (DSP). DSP is utilized for many processes such as convolution, transformation, correlation, and filtering. These processes entail multiplication, and successive additions impact the execution time and arrangement performance. Thus, multiplying and accumulating units (MAC) is essential in DSP. The MAC unit is focused on high-performance processes. Finally, DSP algorithms rely heavily on the MAC’s performance. The functionality of the proposed methods is tested using a Kintex, Artix, and Virtex Field Programmable Gate Array (FPGA) in Xilinx Vivado 2022.2 and ASIC 45 nm technology. Following a thorough investigation, we determined that the Urdhva-tiryagbhyam Vedic multiplication (UVM) technique with Pipelining(P) performed better than other multipliers. The present investigation describes the development of a high-speed MAC unit for arithmetic applications that use a high-speed pipelined Vedic multiplier (VM). The MAC unit’s VM and adder blocks are constructed using the Han Carlson adder (HCA). The proposed PUVMHCA provides considerable delay reductions of 43%, 62.14%, 70.02%, and 78.64% for various bit widths. The MAC-PUVMHCA design reduces delay by 63.55% and improves area by 19.25% for 32-bit FPGA implementations.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148719062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimized power management for fuel cells electrical vehicles using high step-up converter","authors":"K P Dinakaran,&nbsp;G D Anbarasi Jebaselvi,&nbsp;N Karthikeyan","doi":"10.1007/s10470-026-02631-0","DOIUrl":"10.1007/s10470-026-02631-0","url":null,"abstract":"<div><p>Large automotive firms encounter major challenges when integrating renewable energy sources like fuel cells to power electric vehicles (EVs). Traditional boost and quadratic converters often encounter challenges in providing adequate voltage gain at practical duty cycles. DC–DC converters play a vital role in harmonizing the energy levels of fuel cells and electric vehicles, highlighting the importance of examining the specifications of both systems. This study introduces a Hybrid Quadratic Boost Converter (HQBC) topology with two variants (Type-I and Type-II) designed for fuel-cell powertrains. The converter models are analytically formulated and validated using MATLAB for a 27 V, 40 A, 1000 W fuel cell input. Results show that HQBC-Type II achieves a voltage gain of 18.8 at a duty cycle of 0.7, outperforming the conventional quadratic converter and HQBC-Type I. The switch voltage stress remains significantly lower than the output voltage (about 160–180 V), improving device reliability, while current stress stays within safe operating limits. The converter delivers 290 V, 3.2 A at around 980 W with a peak efficiency of 98.2%, compared to 94–95% for traditional converters. These improvements confirm the suitability of the proposed HQBC for fuel-cell electric vehicle applications requiring high gain and high efficiency.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148751151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 48 ps resolution, timing chip constructed from two expandable 32-channel register-only TDCs","authors":"Hang Yu,&nbsp;Jinghe Yang,&nbsp;Yan Li,&nbsp;Binjie Ge,&nbsp;Jinpeng Shen,&nbsp;Liming Si,&nbsp;Siguang Ma","doi":"10.1007/s10470-026-02618-x","DOIUrl":"10.1007/s10470-026-02618-x","url":null,"abstract":"<div><p>Raman spectroscopy is a versatile, nondestructive, and label-free optical analysis technique. To effectively suppress the interference of fluorescence photons in gated-Raman spectroscopy applications, this work presents a novel timing chip featuring 48 ps resolution. The chip is constructed from two expandable 32-channel Time-to-Digital Converter (TDC) cores, resulting in a total of 64 channels. Each TDC core maintains a unified channel height of 30 μm, facilitating seamless integration with concurrent Single Photon Avalanche Diode (SPAD) technology. The proposed TDC architecture relies exclusively on standard digital gates—primarily D-type flip-flops for latching binary results, and therefore eliminates the need for delay-sensitive analog components when consisting the channel. This “register-only” design naturally ensures high uniformity across channels and offers significant flexibility for expansion; in the presented prototype, two identical core blocks are simply placed side-by-side to achieve the 64-channel configuration. The system's 48 ps resolution is determined by thirteen critical rising edges. Shared among all TDC channels, these critical edges are distributed via isolated, shielded paths to minimize noise coupling. The thirteen capacitance-interpolated delay elements, which generates the critical edges upon triggering, are physically isolated from the TDC channels and placed in close proximity to one another. This compact, independent placement further minimizes mismatch among various TDC channels. The measuring resolution of the proposed architecture is dynamically stabilized against Process, Voltage, and Temperature (PVT) variations by a two-stage nested Delay-Locked Loop (DLL). Fabricated using 180 nm CMOS technology, the prototype’s functionality has been fully validated. Under 1 MHz periodic input excitation, the chip demonstrates high energy efficiency with a power consumption of only 0.48 mW/channel at a 1.8 V supply voltage. Moreover, after a one-time calibration process, the system achieves excellent linearity. The measurement results indicate that Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are maintained under 0.7 LSB and 2.5 LSB across nearly all TDC channels (63/64), respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148751307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of low power 9 T SRAM cell with high-performance decoder circuit using pass-transistor logic","authors":"Sudheer Kumar Matam,&nbsp;Rajesh Kumar Nema","doi":"10.1007/s10470-026-02624-z","DOIUrl":"10.1007/s10470-026-02624-z","url":null,"abstract":"<div><p>Electronic devices continue to be an essential component of many medical devices. These devices need Static Random Access Memory (SRAM) with power-efficient capabilities to process the data since they take up the majority of the die space. In particular, wearable technology is creating new design problems for integrated circuits (ICs), where static power dissipation and great low stability are critical requirements. This research proposes a new low-power 9 T SRAM cell design that enhances leakage power dissipation while preserving cell stability for low-power applications. An Enhanced Recycling Folded-Fully Differential Cascode Amplifier (ERFF-DCA) is incorporated into the peripheral circuits of RAM design to improve read speed and reduce overall power consumption. ERFF-DCA improves the performance in SRAM by recycling current within the amplifier, using high-speed current mirrors for phase margin improvement, and associating cross-coupled local positive feedback to increase small and large constraints. Moreover, a Mixed-logic, Low-power, High-performance Decoder Circuit is employed to decrease leakage power and improve performance. The inclusion of a Pass-Transistor Logic Gate (PTLG) significantly enhances the stability of the memory by offering robust noise reduction and minimizing susceptibility to interferences. The proposed design’s efficiency is evaluated using the Cadence tool with 90 nm CMOS technology. The simulated outcomes are associated with current designs to verify the efficiency of the suggested design. The read and write power attained by the proposed model are 1.03E−05 nW and 1.01E−06 nW, which is expressively less than the current models.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148751111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-power analog integrated implementation of the learning vector quantization algorithm for interdisciplinary applications","authors":"Vassilis Alimisis,&nbsp;Emmanouil-Anastasios Serlis,&nbsp;Georgios Gennis,&nbsp;Paul P. Sotiriadis","doi":"10.1007/s10470-026-02635-w","DOIUrl":"10.1007/s10470-026-02635-w","url":null,"abstract":"<div><p>This study introduces a new, energy-efficient, fully analog integrated architecture of the Learning Vector Quantization algorithm. The design showcases its adeptness in effectively managing multiple input features, ensuring high precision, and minimizing power consumption. The main components of the algorithm are Gaussian function and argmax operator circuits. The operational concepts of the architecture are elaborated in detail and are applied to a power-efficient (<span>(1.28 mu W)</span>) configuration with a low voltage (0.6<i>V</i>) setup. This implementation is tailored for two distinct classification tasks: digit recognition and bearing fault condition monitoring. utilizing a 90nm CMOS process, employing the Cadence IC Suite for both the schematic and physical design stages. Comparative analysis of post-layout simulation results with an equivalent software based classifier affirms the accuracy of the modeling and design methodologies employed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-026-02635-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148751112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Ensemble-based unsupervised learning technique for identifying hardware trojan to enhance security and reliability","authors":"M. Priyatharishini,&nbsp;M. Nirmala Devi","doi":"10.1007/s10470-026-02623-0","DOIUrl":"10.1007/s10470-026-02623-0","url":null,"abstract":"<div><p>The adaptation of system-on-chip (SoC) in various communication systems, embedded systems, and automotive electronics fields has been explored, along with the advancement of integrated circuits (IC) fabrication. There are millions of SoC devices with underlying security threats named Hardware Trojan (HT), which impacts inadequate device authentication, leakage of secured information and modified functionality. This paper focuses on pre-silicon-based HT detection and machine learning (ML) techniques that automate feature data during training to identify HTs without the use of a golden chip. Existing pre-silicon learning approaches use a supervised model that is limited by the labelled feature set and requires a large amount of feature-related information during training. Therefore, an unsupervised model is proposed to tackle such a situation by training the unsupervised model with an unlabeled feature set to differentiate Trojan nets from normal nets. The proposed work uses the stacked sparse autoencoder (SSAE) to extract optimal features to train the ML model. The ensemble-based model is also attempted, which utilizes the balancing data from different classifiers to increase the detection accuracy. The unsupervised model obtains an average of 90.15% true positive rate (TPR) and 94.48% true negative rate (TNR) for the benchmark circuits. The simulation result of a proposed ensemble unsupervised model achieves 96.15% accuracy, demonstrating the effectiveness of optimal feature extraction for Trojan detection.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148750764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low power cmos digital variable gain amplifier design for multi band-OFDM UWB communication system","authors":"Samir Ben Salem,&nbsp;Houda Daoud,&nbsp;Sawssen Lahiani,&nbsp;Mourad Loulou","doi":"10.1007/s10470-026-02632-z","DOIUrl":"10.1007/s10470-026-02632-z","url":null,"abstract":"<div><p>This paper introduced the design of a novel Ultra-Wide Band (UWB) digital variable gain amplifier (DVGA) for a multi band-OFDM UWB communication system able to ensure a broad bandwidth for low power, low area regardless of the gain adjustment. The proposed DVGA takes advantage of the benefits provided by the bandwidth extension, on the one hand, and those offered by the digital control techniques, on the other. This allowed the amplifier to provide a large bandwidth at a low power consumption and ensure a flexible gain adjustment using a digital polarization current control block. The Heuristic and contour graph methods were used to optimize the proposed circuit performance and fix the control parameters range intended to satisfy the UWB specification requirements. The newly-designed circuit was simulated using the Advanced Design System (ADS) tool with a device-level description of the TSMC 0.18 μm CMOS process. The DVGA achieved 61.43dB gain control range, 356 MHz bandwidth, 11.5dBm third-order input-intercept point as a maximum gain and less than 19dB noise figure as a maximum gain which makes it convenient for UWB receivers. The overall power consumption of the proposed DVGA circuit is 0.47mW under ± 0.9 V power supply.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148750942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TRUNC-O-SRAM : modeling and simulation characteristics of TRUNCated p+ doped OTFT based 8 T SRAM for high speed, dual data and efficient detection of skin cancer from Images","authors":"Surbhi Bharti,&nbsp;Ashwni Kumar","doi":"10.1007/s10470-026-02634-x","DOIUrl":"10.1007/s10470-026-02634-x","url":null,"abstract":"<div><p>Portable skin-cancer screening wearables demand memory subsystems that are simultaneously energy-efficient, mechanically compliant, and quality-adaptive, requirements unmet by conventional rigid silicon SRAM. This work introduces TRUNC-O-SRAM, an all-p-type Organic Thin-Film Transistor (pOTFT) 8T Static Random-Access Memory (SRAM) designed for flexible substrate deployment, built on a Dual-Split Bottom-Gate Bottom-Contact (DS-BGBC) topology with p+ pentacene channel doping on a L<span>(a_{0.648})</span>N<span>(b_{(0.352)}O_y)</span> gate dielectric. Task-aware hierarchical word encoding stores higher-order luminance and lesion-critical bits in stable, read-decoupled 8T cells while selectively truncating lower-order bits, enabling PSNR/SSIM guided in memory precision scaling without perceptual degradation. At 0.5 <span>(V_{DD})</span> and 27 <span>(^{circ })</span>C, the 2-bit truncation configuration (<span>(y_i)</span> = 2) delivers 23–38% power and area savings over a conventional all-p 6T SRAM baseline, maintains PSNR <span>(ge)</span> 30 dB and SSIM = 0.91, and achieves 95.6% classification accuracy on the HAM10000 skin-lesion dataset – within 0.3 percentage points of lossless storage. Leakage power reaches 0.05 nW per cell, with 1.2 pJ/bit energy efficiency confirmed across 10,000-point Monte Carlo parametric variations. To our knowledge, TRUNC-O-SRAM is the first flexible OTFT SRAM primitive combining deterministic bit truncation with perceptual quality feedback for portable medical edge applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148750814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}