Analog Integrated Circuits and Signal Processing最新文献_第5页

Optimized circular RFID tag antenna achieving extended detection range on metallic surfaces 优化的圆形RFID标签天线在金属表面上实现了扩展的探测范围

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-05 DOI: 10.1007/s10470-025-02389-x

Amit Kumar Singh, A. K. Singh

引用次数: 0

VLSI architecture of a True Random Number Generator with hierarchical Von Neumann corrector and hybrid run length-Golomb coding for data compression 采用分层冯-诺依曼校正器和混合运行长度-戈仑编码的真随机数发生器的超大规模集成电路架构，用于数据压缩

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-04 DOI: 10.1007/s10470-025-02392-2

G. Manavaalan, S. Jayaram, S. Gunasekaran

{"title":"VLSI architecture of a True Random Number Generator with hierarchical Von Neumann corrector and hybrid run length-Golomb coding for data compression","authors":"G. Manavaalan, S. Jayaram, S. Gunasekaran","doi":"10.1007/s10470-025-02392-2","DOIUrl":"10.1007/s10470-025-02392-2","url":null,"abstract":"<div><p>High-quality random number generation is necessary to ensure safe communication by preventing predictable encryption key patterns. This study introduces a new True Random Number Generator (TRNG) architecture that uses an efficient post-processing pipeline in conjunction with an entropy source based on a Digital Clock Manager (DCM). The proposed TRNG compresses random sequences using a Hybrid Run Length-Golomb Coding (HRL-GC) technique, reducing power consumption and increasing efficiency, and employs a Hierarchical Von Neumann Corrector (HVNC) to successfully remove bias while maintaining entropy. In contrast to traditional TRNGs, which have limited throughput and high power consumption, the proposed paradigm offers significant improvements in hardware utilization and performance. The proposed TRNG’s FPGA-based implementation outperforms state-of-the-art systems with a 35.13% improvement in throughput and power consumption of only 0.016 W. These results establish the proposed TRNG as a highly efficient and scalable solution for cryptographic applications, hardware security, and secure communication protocols.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143778134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low-distortion bootstrapped switch for non-uniform sampling of biomedical signals 设计用于生物医学信号非均匀采样的低失真自举开关

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-02 DOI: 10.1007/s10470-025-02384-2

Sara Bagher Nasrabadi, Mehdi Dolatshahi, Sayed Mohammadali Zanjani, Hossein Pourghassem

引用次数: 0

A D-band down-conversion gilbert mixer based on electromagnetic coupling gain-boosted topology in 130 nm SiGe BiCMOS 基于 130 nm SiGe BiCMOS 电磁耦合增益增强拓扑结构的 D 波段下变频吉尔伯特混频器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-02 DOI: 10.1007/s10470-025-02379-z

Xianhu Luo, Weikang Zhou, Xu Cheng, Yunbo Rao, Changxuan Han, Jiangan Han, Liang Zhang, Binbin Cheng, Xianjing Deng

{"title":"A D-band down-conversion gilbert mixer based on electromagnetic coupling gain-boosted topology in 130 nm SiGe BiCMOS","authors":"Xianhu Luo, Weikang Zhou, Xu Cheng, Yunbo Rao, Changxuan Han, Jiangan Han, Liang Zhang, Binbin Cheng, Xianjing Deng","doi":"10.1007/s10470-025-02379-z","DOIUrl":"10.1007/s10470-025-02379-z","url":null,"abstract":"<div><p>This paper presents a D-band down-conversion Gilbert mixer based on electromagnetic coupling topology in 130 nm SiGe BiCMOS process. To improve the conversion gain (CG) and minimize the parasitic of transistors in the millimeter wave frequency band, an electromagnetic coupling gain-boosted topology is innovatively proposed between the switch stage and the transconductance stage. Moreover, a compact marchand balun-based matching network is employed at the RF and LO input terminals to achieve compact impedance matching cell and simultaneous single-end to differential signal cell. Finally, several optimization strategies for the gilbert mixer core’s layout architecture are proposed, which is very helpful for improving isolation and conversion gain (CG). The proposed down-conversion mixer demonstrated a measured RF 1-dB bandwidth varying from 106 to 131 GHz with an LO power of 2 dBm, and the peak conversion gain (CG) of − 3.2 dB at 120 GHz, the simulation result of noise figure of the single sideband, NFssb, is 22.47 dB. Besides, the simulated LO-to-RF isolation is more than 43 dB, and the mixer’s operating current is 13 mA@2.5 V, while occupying a total die area of 990 × 780 μm<sup>2</sup>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low voltage LDO powered by solar photovoltaic cell suitable for internet of things (IoT) devices 一种适用于物联网（IoT）设备的太阳能光伏电池低压LDO设计

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-04-02 DOI: 10.1007/s10470-025-02381-5

Subhranshu Sekhar Dash, Subinoy Roy, Kaushik Bhattacharyya

引用次数: 0

Design of 32 × 32 (1 KB) SRAM array using 10T SRAM cell for portable low power biomedical applications 采用10T SRAM单元设计用于便携式低功耗生物医学应用的32 × 32 (1 KB) SRAM阵列

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-27 DOI: 10.1007/s10470-025-02386-0

Appikatla Phani Kumar, Rohit Lorenzo

{"title":"Design of 32 × 32 (1 KB) SRAM array using 10T SRAM cell for portable low power biomedical applications","authors":"Appikatla Phani Kumar, Rohit Lorenzo","doi":"10.1007/s10470-025-02386-0","DOIUrl":"10.1007/s10470-025-02386-0","url":null,"abstract":"<div><p>Biomedical applications like body area networks (BAN) necessitate the construction of power optimized SRAMs to enhance the batteries life at BAN nodes. In this work, we have designed one-sided near threshold 10TSRAM array for low power portable biomedical applications. The proposed near threshold 10T SRAM (PNT10T SRAM) employs a cross-connected schmitt trigger (ST) inverter and normal inverter in its cell core. The separate path for reading is also employed to eliminate the reading disturbance. The write disturbance is removed in the PNT10T SRAM by removing the trail from VDD and ground. The writing ability is improved with the use of feedback-cutting approach. The standby power dissipation of the memory is mitigated with the use a tail transistor, virtual ground (VGND). The proposed design mitigates the half-select problem due to column-based transistor controlled by CCL. To evaluate the performance, the PNT10T SRAM is compared with C6T, ST11T, ST9T, TG9T, SE9T, and SLE10T SRAM cells using FinFET 18 nm technology at 0.6 V power supply. The PNT10T SRAM mitigates the read power, write power, and leakage power by 51.10%, 50.57%, and 78.97%. Furthermore, the read and write static noise margins improved by 54% and 39.5% respectively, compared to conventional6T (C6T) SRAM.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Privacy preserved two factor authentication system using spread spectrum watermarking of fingerprint and crypto code 基于指纹扩频水印和密码码的保密双因素认证系统

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-27 DOI: 10.1007/s10470-025-02369-1

Priyanka Priyadarshini, Kshiramani Naik

{"title":"Privacy preserved two factor authentication system using spread spectrum watermarking of fingerprint and crypto code","authors":"Priyanka Priyadarshini, Kshiramani Naik","doi":"10.1007/s10470-025-02369-1","DOIUrl":"10.1007/s10470-025-02369-1","url":null,"abstract":"<div><p>The two-factor authentication (2FA) method provides an additional layer of security to the user accounts and systems beyond a single authentication factor like a simple password. Nowadays, biometric-based authentication is widely adopted as it reduces impersonation fraud and account takeover attacks. Biometric data are relevant to the user’s personal information and can potentially be exploited by the attacker to compromise the user’s additional data. Hence, the protection of the biometric data is also vital, along with the secure authentication of the protected data. This proposed work, a 2FA mechanism is implemented using the Spread Spectrum Watermarking method. Instead of storing fingerprint biometric data in the database, it is embedded in the physical token/security token as invisible watermarking with the user’s image. The user’s unique ID (UID) is stored in the database and embedded as an invisible watermark in the physical or security token, the second factor. This physical or security token, commonly known as a ‘smart card, ‘is a portable device that stores the user’s authentication information and can be used for secure access to systems and services. It becomes a smart card once authentication factors and other user information are embedded. The user’s fingerprint is compared to the embedded fingerprint on the smart card for identification to access protected data. To further validate the user’s identity, the embedded UID is decrypted and matched against the stored UID in the database. A detailed simulation analysis demonstrates the enhanced outcomes of the proposed watermarking-based 2FA model. A comparative study of the results confirms the superiority of the proposed model over traditional biometric-based 2FA systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143717051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low-noise wideband fixed IF subharmonic mixer at W-band w波段低噪声宽带固定中频次谐波混频器的设计

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-27 DOI: 10.1007/s10470-025-02388-y

Sadhana Kumari, Naveen Kumar Maurya, Gaurav Varshney

{"title":"Design of a low-noise wideband fixed IF subharmonic mixer at W-band","authors":"Sadhana Kumari, Naveen Kumar Maurya, Gaurav Varshney","doi":"10.1007/s10470-025-02388-y","DOIUrl":"10.1007/s10470-025-02388-y","url":null,"abstract":"<div><p>This paper provides an idea for designing a highly efficient, second-order broadband fixed-IF subharmonic mixer. Attention is paid to the step-by-step design process with detailed fabrication methods. With the purpose to improve the accuracy of simulation, the diode model is separated into the passive (linear) and the active (nonlinear) model. HFSS is utilized for the linear simulation of the mixer model while ADS is utilized for the non-linear simulation of the mixer. A tapered RF probe at the RF port is utilized to achieve wideband performance. The circuit of the presented mixer is printed on the 75 μm Quartz substrate and mounted in a waveguide block using split block technology. Measured results indicate an admissible conversion loss (better than 10.2 dB) over the RF bandwidth from 84 to 105 GHz. A moderate local oscillator power (9 dBm) is needed for this operation. The proposed mixer circuit is verified by test data. The measured port isolation between LO and RF is at least 36 dB. The least measured value of DSB noise temperature and conversion loss is 845 K and 7.2 dB, respectively at 85.2 GHz. The proposed Anti-parallel diode pair (APDP) based diode mixer shows better LO–RF isolation and conversion loss over other W-band mixers reported to date.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA implementation of hybrid Namib beetle and battle royale optimization algorithm fostered linear phase finite impulse response filter design FPGA实现混合纳米甲虫和大逃杀优化算法，培养线性相位有限脉冲响应滤波器的设计

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-24 DOI: 10.1007/s10470-025-02385-1

P. Selvaprasanth, R. Karthick, P. Meenalochini, A. Manoj Prabaharan

{"title":"FPGA implementation of hybrid Namib beetle and battle royale optimization algorithm fostered linear phase finite impulse response filter design","authors":"P. Selvaprasanth, R. Karthick, P. Meenalochini, A. Manoj Prabaharan","doi":"10.1007/s10470-025-02385-1","DOIUrl":"10.1007/s10470-025-02385-1","url":null,"abstract":"<div><p>Nowadays, low complexity analysis is important for the better digital filter design. Although the linear phase finite impulse response (LPFIR) filter design requires less array complexity, existing methods are purely intended to attenuate both passband and stopband ripples. The main objective is to achieve a less complex design, which reduces deployment complexity and equipment cost. Therefore, in this manuscript, the FPGA Implementation of optimization-dependant LPFIR Filter design utilizing hybrid Namib beetle and battle royale optimization algorithm (HNBOA-LPFIR) is proposed. The proposed HNBOA-LPFIR filter design reduces waves of both pass bands and stop band. The transition bandwidth for deploying an LPFIR filter that follows the designated frequency reduces the sparsity. The superiority of filter design has the optimal outcome which conserves the exchange between the several specifications. The proposed HNBOA-LPFIR Filter design is simulated in Xilinx ISE14.7 (Virtex7) environment. The proposed HNBOA-LPFIR Filter methods are executed at FPGA and the efficiency of proposed HNBOA-LPFIR method is estimated with the help of performance metrics. The proposed HNBOA-LPFIR method provides 18.13%, 19.53%, 20.73% lower pass band ripples, 17.19%, 18.28%, 19.83% lower stop band ripple, 19.53%, 18.78%, 20.73% lower transition band when compared to the existing methods: Multi objective FIR filter design utilizing Salp swarm approach and its improved version (SSOA-FIR), Design and analysis of Linear Phase Finite Impulse Response filter utilizing Water Strider Optimization Approach at FPGA (WSOA-LPFIR), Optimal model of digital FIR filter based upon Grasshopper Optimization Approach (GHOA-DFIR) respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

QCA based programmable logic block for implementation of digital circuits in multilayer framework 基于QCA的可编程逻辑块在多层框架中实现数字电路

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-03-24 DOI: 10.1007/s10470-025-02375-3

Rupali Singh, Pankaj Singh

{"title":"QCA based programmable logic block for implementation of digital circuits in multilayer framework","authors":"Rupali Singh, Pankaj Singh","doi":"10.1007/s10470-025-02375-3","DOIUrl":"10.1007/s10470-025-02375-3","url":null,"abstract":"<div><p>Quantum Dot Cellular Automata (QCA) is gathering attention from researchers in recent years due to its attractive features of low power, high density and high speed to serve as transistor-less paradigm for next generation circuits. Programmable or configurable architectures in QCA are needed to promote multifunctional capability of logic circuits along with ease of demonstration and fabrication. Moreover, multilayer approach in QCA adds the area efficacy and immunity against random interference. This paper presents the design of novel programmable logic block (PLB) in QCA configuration in multilayer framework which can be easily used to generate variety of digital circuits. The proposed QCA based PLB is further used to realize combinational circuit such as adder etc<i>.</i> and sequential circuits such as D flip flop, random access memory (RAM) element, shift registers etc<i>.</i> The circuits are further analyzed to obtain performance metrics. A comparative assessment has been carried out for the proposed PLB circuit to establish compatibility with the existing circuits. The proposed PLB sets path towards development of future generation complex and configurable computing systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0