Analog Integrated Circuits and Signal Processing最新文献_第5页

An optimization approach control of EV solar charging system with step-up DC–DC converter 电动汽车太阳能充电系统与升压型 DC-DC 转换器的优化控制方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-28 DOI: 10.1007/s10470-024-02253-4

R. J. Venkatesh, R. Priya, P. Hemachandu, Chinthalacheruvu Venkata Krishna Reddy

{"title":"An optimization approach control of EV solar charging system with step-up DC–DC converter","authors":"R. J. Venkatesh, R. Priya, P. Hemachandu, Chinthalacheruvu Venkata Krishna Reddy","doi":"10.1007/s10470-024-02253-4","DOIUrl":"10.1007/s10470-024-02253-4","url":null,"abstract":"<div><p>An optimization technique for the control of a photovoltaic (PV)-fed electric vehicle (EV) solar charging station with a high gain of step-up dc-to-dc converter. An optimization approach is the Namib beetle optimization (NBOA) approach. This approach is used to control the EV solar charging station. Also, the principles of a switched capacitor and a coupled inductor are integrated into the interleaved structure of the NBOA converter to produce low-current, high-efficiency, and high-voltage gain. However, the major contribution is to minimize the total harmonic distortion (THD) and to control the EV solar Charging Station. The bi-directional DC-to-DC converter in an energy-storage-system has the advantages of high efficiency and fast response speed. By then, the NBOA technique is done in MATLAB software, and the performance is evaluated with the existing techniques. The NBOA system has low THD and high efficiency, which is compared with the existing ant-lion optimizer, wild horse optimizer, and salp-swarm algorithm, methods. From the analysis, the NBOA method provides a better outcome than the existing one.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 2","pages":"215 - 232"},"PeriodicalIF":1.2,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140008639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of a low phase noise, wide tunable CMOS based low power VCO with active inductor 设计和分析基于有源电感器的低相位噪声、宽可调 CMOS 低功率 VCO

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-28 DOI: 10.1007/s10470-024-02266-z

Isha Kadyan, Manoj Kumar

引用次数: 0

Correction: A floating memristor emulator for analog and digital applications with experimental results 更正：用于模拟和数字应用的浮动忆阻器仿真器及实验结果

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-27 DOI: 10.1007/s10470-024-02268-x

B. Suresha, Chandra Shankar, S. B. Rudraswamy

引用次数: 0

Novel high-gain narrowband antenna based on ENZ SIW structure and shorting pin 基于 ENZ SIW 结构和短路引脚的新型高增益窄带天线

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-26 DOI: 10.1007/s10470-024-02267-y

Rajesh Kumar Dash, Sadhana Kumari, Balamati Choudhury

{"title":"Novel high-gain narrowband antenna based on ENZ SIW structure and shorting pin","authors":"Rajesh Kumar Dash, Sadhana Kumari, Balamati Choudhury","doi":"10.1007/s10470-024-02267-y","DOIUrl":"10.1007/s10470-024-02267-y","url":null,"abstract":"<div><p>This paper provides an idea for designing a high-gain narrow-band substrate integrated waveguide (SIW) antenna. The high gain is achieved due to the epsilon-near-zero (ENZ) technique, and narrow-band performance is achieved due to impedance matching provided by a pair of symmetric shorting pins. In this paper, SIW is used near its cut-off frequency to realize the ENZ characteristics. Further, two symmetric open stubs are incorporated to reject the out out-of-band frequency signal. To attain narrow-band performance, pair of symmetric shorting pins are employed in place of the conventional way, i.e., tapered line transition to couple the energy from microstrip to SIW. To validate the proposed concept, a high-gain narrow-band SIW antenna has been designed for a frequency band on a 0.79 mm thick RT- DUROID 5880 substrate. Within the 7.77–8.07 GHz band, the proposed antenna radiates with gain and radiation efficiency of 6.51 dBi and 96%, respectively. The measured and simulated results are found to be consistent. The overall size of the proposed antenna is 28 X 22 mm<sup>2</sup>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 3","pages":"455 - 462"},"PeriodicalIF":1.2,"publicationDate":"2024-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139980436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system 使用自适应神经模糊推理系统的 5G 毫米波应用新型宽带、小尺寸和高增益贴片天线阵列

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-25 DOI: 10.1007/s10470-023-02245-w

Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou

{"title":"A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system","authors":"Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou","doi":"10.1007/s10470-023-02245-w","DOIUrl":"10.1007/s10470-023-02245-w","url":null,"abstract":"<div><p>In this paper a wide-band, small size and high gain modified patch antenna array and a single element antenna for fifth Generation (5G) millimetre-wave (mm-wave) applications have been presented. The designing of single element antenna and array antenna is based on the Adaptive Neuro-Fuzzy Inference systems (ANFIS). The ANFIS technique is used to estimate the dimensions of the single element as well as the spacing between patch antenna elements in antenna array. The single element’s operating frequency is 28 GHz, While the array antenna covers the frequency band from 23.6 to 29.2 GHz, resonating at 25 and 28 GHz. The antenna array was designed and simulated using the Rogers RT duroid 5880 Substrate, which has a dielectric constant of 2.2, a loss tangent <span>(tan ( delta ))</span> of 0.0009, and thickness of 0.508 mm. The proposed single element patch antenna has a size of 4<span>(times 4.8)</span> <span>(times)</span>0.508 <span>({text{mm}}^{3})</span> with wideband range from 23 to 38.6 GHz (15.6 GHz) with a gain of 4.17 dB. Based on these properties, the single element is expanded into a six-element array with a compact size of 13.2<span>(times)</span>23.8<span>(times)</span> 0.508 <span>({text{mm}}^{3})</span> in order to enhance the gain and to make the antenna radiation pattern directional. The designed antenna array has a wide-band from 23.6 to 29.2GHz (5.6 GHz) and a high gain of 11 dB, making it as strong candidate for future mm-wave applications.\u0000</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"603 - 618"},"PeriodicalIF":1.2,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02245-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139980196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scalable intelligent median filter core with adaptive impulse detector 具有自适应脉冲检测器的可扩展智能中值滤波器内核

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-25 DOI: 10.1007/s10470-024-02261-4

Nanduri Sambamurthy, Maddu Kamaraju

{"title":"Scalable intelligent median filter core with adaptive impulse detector","authors":"Nanduri Sambamurthy, Maddu Kamaraju","doi":"10.1007/s10470-024-02261-4","DOIUrl":"10.1007/s10470-024-02261-4","url":null,"abstract":"<div><p>This paper introduces a reconfigurable AI-enabled scalable median filter with an adaptive impulse detector designed for FPGA-based real-time imaging systems. Its primary objective is to address the degradation of image quality caused by mixed impulsive noise during real-time image transmission and reception. Existing median filters often struggle to provide real-time image processing results that meet high standards in terms of both accuracy and speed. This approach effectively suppresses noise in real-time images while preserving essential edge details, which are crucial for the performance of real-time imaging systems. The algorithm introduces a novel technique of replacing noisy pixels with the processed central value within the image filtering window. This ensures fidelity to the original pixel, which is vital for applications such as image filter cores. To handle high noise densities in real-time systems, the methodology employs a scalable sorting approach for median filtering and an impulse detector, ensuring robust noise reduction without excessive computational complexity. The AI-enabled scalable median filter system achieves a significant reduction in dynamic power consumption, realizing an impressive 46% decrease in power consumption and an 82% reduction in area compared to the existing system. This is particularly beneficial for addressing resource and power-aware constraints in real-time systems. Comprehensive performance evaluation, including metrics such as PSNR, MSE, IEF, and SSIM, demonstrates the efficacy of the filter in enhancing image quality, a critical factor for the success of real-time imaging systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"425 - 435"},"PeriodicalIF":1.2,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications 用于 FMCW 应用的 80-84.8 GHz PLL，带自动跟踪米勒分频器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-24 DOI: 10.1007/s10470-024-02258-z

Popong Effendrik, Wei-Zen Chen

{"title":"An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications","authors":"Popong Effendrik, Wei-Zen Chen","doi":"10.1007/s10470-024-02258-z","DOIUrl":"10.1007/s10470-024-02258-z","url":null,"abstract":"<div><p>To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FM<sub>error</sub>/BW<sub>chirp</sub> and RMS-FM<sub>error</sub>/(BW<sub>chirp</sub> × f<sub>c</sub> × T<sub>c</sub>) with value of 0.013% and 0.77e−12<b>,</b> respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"523 - 537"},"PeriodicalIF":1.2,"publicationDate":"2024-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-024-02258-z.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 4-D four-wing chaotic system with widely chaotic regions and multiple transient transitions 具有广泛混沌区和多重瞬态转换的四维四翼混沌系统

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-23 DOI: 10.1007/s10470-024-02260-5

Lingyun Li, Zhijun Chai, Yunxia Wang

引用次数: 0

Chip implementation of low-power high-efficient buck converter for battery-powered IOT applications 用于电池供电物联网应用的低功耗高效降压转换器的芯片实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-22 DOI: 10.1007/s10470-023-02204-5

Shih-Chang Hsia, Ming-Ju Hsieh

引用次数: 0

Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application 用于纳米互连应用的热感知电路模型和 MLGNR 性能分析

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-21 DOI: 10.1007/s10470-024-02254-3

Himanshu Sharma, Karmjit Singh Sandha

{"title":"Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application","authors":"Himanshu Sharma, Karmjit Singh Sandha","doi":"10.1007/s10470-024-02254-3","DOIUrl":"10.1007/s10470-024-02254-3","url":null,"abstract":"<div><p>This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"71 - 81"},"PeriodicalIF":1.2,"publicationDate":"2024-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139928283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0