Analog Integrated Circuits and Signal Processing最新文献_第5页

Estimation of polarization diversity in CPW fed compact dual band dual sense antenna with horn slot structure: 5G and WLAN applications 角槽结构 CPW 馈电紧凑型双频双感天线的极化分集估算：5G 和 WLAN 应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-12 DOI: 10.1007/s10470-024-02250-7

Krishna Chennakesava Rao Madaka, Pachiyannan Muthusamy

引用次数: 0

A design approach for class-AB operational amplifier using the gm/ID methodology 使用 gm/ID 方法的 AB 类运算放大器设计方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-11 DOI: 10.1007/s10470-024-02252-5

Chen Chen, Jinxing Cheng, Hongyi Wang, Youyou Fan, Kaikai Wu, Tao Tao, Qingbo Wang, Ai Yu, Weiwei Wen, Youpeng Wu, Yue Zhang

{"title":"A design approach for class-AB operational amplifier using the gm/ID methodology","authors":"Chen Chen, Jinxing Cheng, Hongyi Wang, Youyou Fan, Kaikai Wu, Tao Tao, Qingbo Wang, Ai Yu, Weiwei Wen, Youpeng Wu, Yue Zhang","doi":"10.1007/s10470-024-02252-5","DOIUrl":"10.1007/s10470-024-02252-5","url":null,"abstract":"<div><p>The primary contribution of this paper is the extension of the g<sub>m</sub>/I<sub>D</sub> design methodology to two-stage operational amplifiers with class-AB output stages. First, the circuit is analyzed from the perspective of the g<sub>m</sub>/I<sub>D</sub> methodology, with a focus on its performance metrics and constraints. Second, to handle optimization targets and constraints automatically, the circuit sizing task is formulated as a single-objective optimization problem, and an optimizer is employed to obtain the temporary solution automatically. Benefiting from the g<sub>m</sub>/I<sub>D</sub> methodology, the gap between analytical equations and circuit simulation is highly reduced. Third, following the temporary solution, a guided fine-tuning method is introduced to further optimize the temporary solution. To demonstrate the effectiveness of this approach, we compared the equation-based method using the square-law model, two simulation-based methods and a commercial tool, Cadence ADE GXL, employing SMIC 55 nm and SMIC 180 nm CMOS technologies. The simulation results confirm the success of the proposed approach, showing that it not only reduces the gap between analytical equations and simulations, but also achieves the best performance metrics.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 1","pages":"43 - 55"},"PeriodicalIF":1.2,"publicationDate":"2024-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A bidirectional four-port DC–DC converter for grid connected and isolated loads of hybrid renewable energy system using hybrid approach 采用混合方法为混合可再生能源系统的并网和隔离负载设计双向四端口 DC-DC 转换器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-10 DOI: 10.1007/s10470-024-02251-6

N. Karthikeyan, G. D. Anbarasi Jebaselvi

{"title":"A bidirectional four-port DC–DC converter for grid connected and isolated loads of hybrid renewable energy system using hybrid approach","authors":"N. Karthikeyan, G. D. Anbarasi Jebaselvi","doi":"10.1007/s10470-024-02251-6","DOIUrl":"10.1007/s10470-024-02251-6","url":null,"abstract":"<div><p>Most four-port converters typically enable bidirectional power flow through the low-voltage side battery port, which is used to discharge to the high-voltage side DC-link and charge from energy sources. However, system-level power management is restricted by the DC-link’s absence of bidirectional power transmission. This manuscript proposes a hybrid approach utilizing a four-port DC–DC converter that can operate in isolation and in conjunction with the grid for hybrid renewable energy systems. Moreover, the converter architecture enables bi-directional power flow between all four ports, including the high-voltage DC-link, allowing for flexible and efficient power management. The Random Decision Forest and Jellyfish Search technology are combined to form the JS-RDF technique, which goes by that name. The primary goal of the proposed method is to reduce power losses, enhance system performance, and ensure stable voltage profiles. The JS is used for robust optimization, adapting the converter to various conditions, while the RDF employs machine learning for optimal control pulse prediction, enhancing overall efficiency. The JS-RDF approach is implemented on the MATLAB platform and is compared with existing approaches. Also, the JS-RDF method demonstrates great power compared to other existing approaches. From the result, the proposed technique shows outstanding performance with minimal switching losses at 0.19 W and conduction losses at 0.43 W, leading to the lowest total losses of 0.62 W. This emphasizes the superior efficiency of the proposed approach in optimizing power conversion, highlighting its potential to improve the overall performance of converter systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"467 - 487"},"PeriodicalIF":1.2,"publicationDate":"2024-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications 为深度学习应用设计面积速度高效的 Anurupyena Vedic 乘法器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-09 DOI: 10.1007/s10470-024-02255-2

C. M. Kalaiselvi, R. S. Sabeenian

{"title":"Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications","authors":"C. M. Kalaiselvi, R. S. Sabeenian","doi":"10.1007/s10470-024-02255-2","DOIUrl":"10.1007/s10470-024-02255-2","url":null,"abstract":"<div><p>Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the Field Programmable Gate Array (FPGA) implementation employing Very Large-Scale integration (VLSI) design approaches and parallel computing technology. Signal processing, machine learning, and reconfigurable computing research should be closely monitored as artificial intelligence develops. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in Arithmetic Logic Unit (ALU), Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a specific hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 3","pages":"521 - 533"},"PeriodicalIF":1.2,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139762004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electromagnetic coupling suppression of circularly polarized mimo antenna with novel loop parasitic for UWB communication 用于 UWB 通信的带有新型环形寄生器的圆极化 mimo 天线的电磁耦合抑制功能

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-08 DOI: 10.1007/s10470-024-02256-1

Muhammad Irshad Khan, Shaobin Liu, Saeed Ur Rahman, Muhammad Kabir Khan, Muhammad Sajjad, Abdul Basit, Jianliang Mao, Amil Daraz

{"title":"Electromagnetic coupling suppression of circularly polarized mimo antenna with novel loop parasitic for UWB communication","authors":"Muhammad Irshad Khan, Shaobin Liu, Saeed Ur Rahman, Muhammad Kabir Khan, Muhammad Sajjad, Abdul Basit, Jianliang Mao, Amil Daraz","doi":"10.1007/s10470-024-02256-1","DOIUrl":"10.1007/s10470-024-02256-1","url":null,"abstract":"<div><p>In this article, four elements circularly polarized trapezoid multiple inputs and multiple outputs (MIMO) antenna for UWB application is presented. The electrical dimension of presented four elements MIMO antenna in term of lambda (λ) is 0.44λ × 0.44λ × 0.012λ. The novel loop parasitic is used for the enhancement of isolation and impedance bandwidth. The reflection coefficient (Sij ∈ i = j) is less than − 10dB in range of 2.4 GHz and 13.5 GHz and isolation (Sij ∈ i ≠ j) is greater than 22dB in given range. The axial ratio bandwidth (ARBW) of presented trapezoid antenna is 3.6 GHz; less than − 3dB in the range of 6.7 and 10.3 GHz. The peak gain is 5.9dBi, diversity gain (DG) > 9.89dB and envelope correlation coefficient (ECC) < 0.022. Various other parameters such as radiation pattern, reflection coefficient, Isolation, multiplexing efficiency, ECC, DG and peak gain are discussed in detail for experimental validation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"577 - 588"},"PeriodicalIF":1.2,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An all-digital low-power, low-frequency GRO-based time to digital converter for biomedical applications 用于生物医学应用的基于 GRO 的全数字、低功耗、低频率时间数字转换器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-06 DOI: 10.1007/s10470-023-02246-9

Elnaz Zafarkhah, Maryam Zare, Nima S. Anzabi-Nezhad, Zahra Sohrabi

引用次数: 0

Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic 利用伪 NCFET 逻辑设计高能效脉冲触发三元触发器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-06 DOI: 10.1007/s10470-023-02236-x

Sudha Vani Yamani, M. V. S. RamPrasad, Gundala Dinesh, Eegala Yamini Yeshaswila, Chelluri Ravi Teja, Botta Lokesh

{"title":"Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic","authors":"Sudha Vani Yamani, M. V. S. RamPrasad, Gundala Dinesh, Eegala Yamini Yeshaswila, Chelluri Ravi Teja, Botta Lokesh","doi":"10.1007/s10470-023-02236-x","DOIUrl":"10.1007/s10470-023-02236-x","url":null,"abstract":"<div><p>In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS, occurs serious challenges such as higher leakage currents and higher static power consumption have been raised in high-performance circuits. Therefore, to address these issues, we explored carbon nanotube field effect transistors (CNTFETs) with multi-valued logic (MVL). In this paper, we designed an energy-efficient Pulse triggered Ternary Flip Flops (P-TFF) such as Data Close to Output (P-DCO-TFF), Signal Feed Through (P-SFT-TFF), and Delay (P-D-TFF) with pseudo NCFET (N-channel CNTFET) logic. These flip-flops use ternary logic, which is 0, V<sub>dd</sub>/2, and V<sub>dd</sub> as logic 0, 1, and 2, respectively. The complete design is done by the stanford 32 nm CNTFETs. The simulations are performed and waveforms are obtained in Cadence Virtuoso Software. We found that the suggested pulse-triggered TFFs performed better than the conventional ternary FF (C-TFF) structure in terms of energy, delay, and power. This simulation result shows 17.8%, 14%, and 47.7% energy reduction in P-SFT-TFF, P-DCO-TFF, and P-D-TFF, respectively, compared with C-TFF structure. Also performed the Monte Carlo Simulations to these proposed TFF designs. The P-D-TFF exhibits very efficient results in terms of delay, energy, and power consumption. This article also simulated the Ternary Universal Shift Register (TUSR) with Proposed P-D-TFF.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 1","pages":"151 - 163"},"PeriodicalIF":1.2,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A phase noise filter for RF oscillators 用于射频振荡器的相位噪声滤波器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-05 DOI: 10.1007/s10470-024-02249-0

Debdut Biswas

引用次数: 0

Frequency reconfigurable antenna array modelling based on MoM-GEC method for RFID, WiMax and WLAN applications 基于 MoM-GEC 方法的频率可重构天线阵列建模，适用于 RFID、WiMax 和 WLAN 应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-03 DOI: 10.1007/s10470-023-02244-x

Heithem Helali, Mourad Aidi, Taoufik Aguili

{"title":"Frequency reconfigurable antenna array modelling based on MoM-GEC method for RFID, WiMax and WLAN applications","authors":"Heithem Helali, Mourad Aidi, Taoufik Aguili","doi":"10.1007/s10470-023-02244-x","DOIUrl":"10.1007/s10470-023-02244-x","url":null,"abstract":"<div><p>Technology is advancing daily, and it has impacted almost every aspect of our lives. We show that growth in the number of miniaturized communications systems that are covering different wireless services can achieve a wide frequency range. The present work aims to propose a new rigorous formulation to model a reconfigurable array system used for different wireless applications. The studied structure consists of a reconfigurable antenna array composed of parallel microstrip antennas excited by localized voltage sources and commanded by located PIN diodes. Diodes are used to adjust the length of the radiating element in order to shift the resonant frequency. The proposed formulation consists to combine the moment method and generalized equivalent circuit’s method (MoM-GEC) to model the antenna array. The PIN diode is considered in the mathematical formulation by an impedance surface model. The input impedance, the reflection parameter (<span>({S}_{11})</span>) and the current distribution density obtained with this method are presented and discussed. The results were in close agreement with those obtained by software simulation. The obtained results offer the possibility to generate various modes governed by a decision tree. Thus, these modes are related to different resonant frequencies suitable for RFID, WiMax and WLAN applications with a large bandwidth reaching 526 MHz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"553 - 566"},"PeriodicalIF":1.2,"publicationDate":"2024-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139662995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer 基于全变频器的 12.5 Gb/s 1.38 mW 光接收器，带多级反馈 TIA 和连续时间线性均衡器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-03 DOI: 10.1007/s10470-024-02248-1

Peng Yan, Chaerin Hong, Po-Hsuan Chang, Hyungryul Kang, Dedeepya Annabattuni, Ankur Kumar, Yang-Hang Fan, Ruida Liu, Ramy Rady, Samuel Palermo

引用次数: 0