Analog Integrated Circuits and Signal Processing最新文献

{"title":"BCSSA-VMD and ICOA-ELM based fault diagnosis method for analogue circuits","authors":"Dazhang You,&nbsp;Shan Liu,&nbsp;Ye Yuan,&nbsp;Yepeng Zhang","doi":"10.1007/s10470-025-02360-w","DOIUrl":"10.1007/s10470-025-02360-w","url":null,"abstract":"<div><p>Analog circuits are an important component of integrated circuit systems, and circuit systems are the foundation for ensuring the normal operation of electronic devices. Therefore, it is necessary to efficiently diagnose and maintain faults in analog circuits. However, due to the tolerance, high nonlinearity, and susceptibility to environmental interference of analog circuit components, the development of related research on fault diagnosis has been hindered, and it cannot meet the current practical requirements for high safety and reliability of electronic devices. With the continuous increase in circuit scale and integration level, how to effectively and as much as possible extract more discriminative fault features is the key research direction of analog circuit fault diagnosis. Therefore, this article proposes a variational model decomposition (VMD) feature extraction method that combines Butterfly and Cauchy Sparrow search algorithms (BCSSA) and relies on an improved crayfish optimization algorithm (COA) to optimize the Extreme Learning Machine (ELM). Decomposition (VMD) feature extraction method, and rely on Improved Crayfish Optimization Algorithm (COA) Optimized Extreme Learning Machine (ELM) to complete the classification of faults. Firstly, the BCSSA algorithm is used to optimize the number of VMD decomposition modes K and the penalty factor <i>α</i> to achieve the optimal VMD decomposition of the original fault signal, obtain a series of Intrinsic Mode Function (IMF) and calculate its envelope entropy, determine the optimal IMF component by selecting the IMF component with the lowest envelope entropy., and calculate its time-domain parameter, then normalize and reduce the dimensionality to construct the vector that contains the characteristics of the fault. The normalized dimensionality reduction process constitutes the fault feature vector; secondly, the ICOA algorithm is introduced to optimize the ELM; Ultimately, the fault feature vector is fed into the ELM to acquire the fault diagnosis results. The simulation test examples of the Sallen-Key bandpass filter circuit and the Four-op-amp circuit show that the accuracy of the proposed improved VMD and ELM fault diagnosis method is as high as 99.68%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Insights of quad port MIMO antenna for 5G NR n77/n79 to X-bands with reconfigurable grounds using PIN diodes","authors":"Gayatri Tangirala,&nbsp;Srinivasu Garikipati,&nbsp;Manikya Krishna Chaitanya Durbhakula,&nbsp;Virendra Kumar Sharma","doi":"10.1007/s10470-025-02366-4","DOIUrl":"10.1007/s10470-025-02366-4","url":null,"abstract":"<div><p>This manuscript explores the development of a quad-port Multiple-Input-Multiple-Output (MIMO) antenna featuring reconfigurable grounds tailored for 5G NR n77/n79 and X-band applications, utilizing PIN diodes. The research begins with the evolution of a single unit Ultra Wideband antenna, which is subsequently expanded to a reconfigurable grounds 2 × 2 MIMO antenna controlled by a single PIN diode. Further to a reconfigurable grounds 4 × 4 MIMO antenna managed by four PIN diodes. This work is innovative in its approach, as it examines and designs MIMO antennas that can switch between unconnected and connected ground states through reconfiguration techniques. This MIMO antenna is printed on a FR4 substrate, with dimensions of 0.597λ₀ × 0.448λ₀ × 0.0171λ₀ mm³, where λ₀ is determined based on the lowest resonating frequency. It operates across a frequency range of 3.2–12 GHz with connected grounds. In the majority of the band the designs show mutual coupling  ≤  − 15 dB. The performance is assessed at every stage and graphs are compared for both unconnected and connected grounds. The inferences are included on all the metrics like gain, isolation, efficiency, radiation patterns, S-parameters, Mean Effective Gain, Channel Capacity Loss, Diversity Gain, Envelope Correlation Coefficient, and Total Active Reflection Coefficient. The stub introduced to connect the grounds itself act as an efficient decoupling network. The printed MIMO performance results are matches with simulated results. This work has 5G wireless applications including RF energy harvesting and cognitive radio.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Blind 2-microphone acoustic noise reduction algorithms using efficient variable step-size adapted by minimizing the intercorrelation function","authors":"Redha Bendoumia","doi":"10.1007/s10470-025-02335-x","DOIUrl":"10.1007/s10470-025-02335-x","url":null,"abstract":"<div><p>Recent advancements in adaptive noise signal reduction have utilized 2-microphones adaptive algorithms. Specifically, the normalized form of least-mean-square algorithm (NLMS) with fixed-step-size parameters (FS) has been combined with direct-and-recursive structures of source separation. Compared to conventional one-microphone methods, these combinations provide superior speech quality. However, the main limitation of these 2-microphones adapting algorithms (Direct combination: Forward NLMS and Recursive combination: Backward NLMS) lies in their poor steady state regime with large FS value, while small step-sizes values result a slow speed of convergence. To address these issues, we propose a new variable step-size (VS) approach in this study, based on minimizing the intercorrelation function in the time domain for the basic FNLMS and BNLMS algorithms. Our approach is proposed exactly to determine an optimal value of VS parameters by minimizing the intercorrelation between the enhanced signal and the noisy microphone signals. These methods improve steady state values and convergence speed at the same time. The proposed 2-microphones adapting algorithms were evaluated through simulations conducted in high-noise environments, using the system of mismatch criterion and estimation of output segmental signal-to-noise ratio ones. The comparative simulations results confirmed that our algorithms outperform FS algorithms in terms of steady state values and convergence speed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of array system configuration using the smoothed-pad algorithm","authors":"Mario Batubara,&nbsp;Timbul Manik,&nbsp;Peberlin Sitompul,&nbsp;Musthofa Lathif","doi":"10.1007/s10470-025-02362-8","DOIUrl":"10.1007/s10470-025-02362-8","url":null,"abstract":"<div><p>The source of astronomical objects, in general, is a very far distance from the observation instrument so that the transmitted signal is received very small and is at risk of being disturbed by other sources around the receiving system. Therefore, the concept of multiple receivers with array interferometry configuration arrays is used to improve the quality of the source signal detected by the receiving system. The position of each receiving system, known as the antenna pad, determines the quality performance of the received signal output. The antenna positions are arranged in a discrete grid system so that there is a vacancy between antenna pads. In this paper, a computational technique is present to overcome the region’s emptiness between one antenna to its neighbor. As an initial result, the integrating of each position with its neighboring pads with some of its smoothing functions is optimal in filling the void region and maximizing the u-v coverage.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low power high speed 14T-TSPC-DomDFF design and analysis in CMOS 16nm technology","authors":"Ramsha Suhail,&nbsp;Pragya Srivastava,&nbsp;Richa Yadav,&nbsp;Nandini Baliyan,&nbsp;Rewa Chaudhary","doi":"10.1007/s10470-025-02371-7","DOIUrl":"10.1007/s10470-025-02371-7","url":null,"abstract":"<div><p>Utilised in a range of applications such as registers, counters, and state machines, the D Flip-Flop (DFF) is a flexible device that has undergone development over time with innovative design approaches to enhance power efficiency. True Single Phase Clock (TSPC) logic has constantly been a preferred option in high-speed applications. This work introduces an enhanced 14 Transistor TSPC-based positive edge-triggered Domino DFF (TSPC DomDFF) at 16 nm with a Clock-to-Q (CQD) latency of 55.4ps, improved power consumption of 96.8nW, and salient Power Delay Product (PDP) and Energy Delay Product (EDP) as 5.36aJ and 0.297aJ-ns, respectively, at an operating voltage of 0.9 V. It showcases the performance of a high speed and power efficient design with 32%, 77%, 85%, 94% improvement in PDP with respect to MTSPC, 26TSPC, 18T HFF, and MSDFF respectively. The results are validated through detailed robust analysis. Furthermore, the proposed 14T TSPC DomDFF is implemented to construct a 4-bit Serial-in-Serial-out (SISO) Shift Register (4-SISO SR) at operating frequency of 5 GHz. The improved results enabled the physical layout design to be accommodated within an optimized area of 3.7µm² for the proposed circuit and 15.4µm² for the proposed application.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low-power, high-speed carry look ahead adder utilizing 11-T hybrid full adder module based 4:2 compressor unit for low-power applications","authors":"Nimai Halder,&nbsp;Biswarup Mukherjee","doi":"10.1007/s10470-025-02361-9","DOIUrl":"10.1007/s10470-025-02361-9","url":null,"abstract":"<div><p>In this study, a novel low-power, high-speed hybrid architecture for a 16-bit carry look-ahead adder (CLA) employing 4:2 compressors is proposed. To enhance compressor latency and power efficiency, a new hybrid full adder architecture based on eleven transistors is implemented. The conventional CMOS (CCMOS) architecture of CLAs is hindered by poor latency due to the significant parasitic capacitance presented by higher-order carry generation modules, unlike the ripple carry adder architecture. To mitigate latency issues in the CLA architecture, the design generates odd and even carry bits independently. The proposed 16-bit CLA architecture is simulated using a 45 nm PTM technology model with the Mentor Graphics Tanner EDA tool. Comprehensive simulation-based analyses and comparisons with state-of-the-art methodologies are conducted, focusing on power consumption, delay, and area (transistor count). The proposed design has a power-delay product of 108 femtojoules, which is 53% better than the CCMOS 16-bit CLA architecture.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of high-speed and 6-bit flash ADC module for non-contact vital sign signal processing in biomedical application","authors":"Pushparaj Pal,&nbsp;Banoth Krishna,&nbsp;Amod Kumar,&nbsp;Sandeep Singh Gill,&nbsp;Garima Saini","doi":"10.1007/s10470-025-02376-2","DOIUrl":"10.1007/s10470-025-02376-2","url":null,"abstract":"<div><p>The signal processing is the primary factor for improving the accuracy of bio signals in electronic devices with respect to speed and resolution. The ADC is often called the heart of the electronics processing system. Without the ADC module, the device cannot proceed to further processing stages and becomes non-functional. In biomedical applications, healthcare service providers remotely monitor patients using non-contact vital sign detection and signal monitoring through CW Doppler radar of 2.45 GHz. The system collects tiny signals remotely, with HR signals of (0.2–0.5)Hz and RR signals of (0.3–0.7)Hz. Recovering these signals from the received data, containing clutters and noise, is a challenging task that requires a high-speed, high-resolution, and accurate-based system. The SAR-ADC has existing problems with high speed and bit resolution, system performance, and accuracy, which are overcome in the flash ADC with reduced hardware. The received signal is further processed using the DAQ system. The system uses a 6-bit 1GS/s flash ADC for enhanced system performance. Simulation results show an INL of -0.49/+0.76 LSB and DNL of -0.65/+0.59 LSB, respectively. At -0.3 dBFS and a 1 kHz sinusoidal signal, the SNDR is 47dB (6.4 ENOB). The system operates at power level of 96.08uW with a supply voltage of 1.6 V. The implementation is carried out using simulation tools such as Cadence Virtuoso, and MATLAB platforms.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single event transient (SET) for a novel step-truncated SELBOX FinFET device","authors":"Baojun Liu,&nbsp;Jing Zhu","doi":"10.1007/s10470-025-02367-3","DOIUrl":"10.1007/s10470-025-02367-3","url":null,"abstract":"<div><p>A novel FinFET structure is derived from the calibrated conventional SOI FinFET at 14 nm technology node. It is designed as a step and low truncated fin with a small opening in the box (STS-FinFET). Single event transients (SETs) of serval FinFETs are investigated, including conventional FinFET (C-FinFET), SELBOX FinFET (SELBOX-FinFET), truncated-fin SELBOX FinFET (T-FinFET), semicircular-truncated SELBOX FinFET (SEMC-FinFET). The results show that although the deposited charge is significantly increased, T-FinFET, and SEMC-FinFET, in particular STS-FinFET, can dramatically reduce the sensitivity to SET. Compared with C-FinFET, the relative decrements of the SET current peak, pulse width, collected charge and bipolar amplification coefficient for the proposed STS-FinFET are 15.91%, 52.41%, 63.78%, and 93.80%, respectively. The novel structure presents more immune to SET than the others. The reason is discussed from the synergistic effect of the small opening induced by SELBOX and the cross section derived from the step and truncated fin.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An ultra-fast settling and low area bit synchronizer architecture","authors":"Amitava Ghosh,&nbsp;Anindya Sundar Dhar","doi":"10.1007/s10470-025-02364-6","DOIUrl":"10.1007/s10470-025-02364-6","url":null,"abstract":"<div><p>The paper presents the architecture design of a bit synchronizer suited for wireless sensor node applications. It detects a 0–1 transition sent from transmitter that subsequently triggers a counter clocked by a reference. The counter counts a certain number of reference cycles and generates a strobe signal that is used to sample the demodulated waveform at the maximum signal to noise ratio (SNR) instant. Because of the position of the maximum SNR point, there is a latency in the strobe signal. This latency can be measured off-chip and on-chip. Off-chip solution entails observing a repetitive 0–1 pattern sent from the transmitter, and the reference clock post fabrication in an oscilloscope in test lab and writing the latency in terms of reference cycle counts into the chip. On-chip solution uses samplers to sample the demodulated waveform at multiple instants and finds the time where the maximum sampled value occurs. Algorithm was designed first from which the architecture was generated. For the off-chip method, circuit design followed by layout was also performed. The bit synchronizer requires just two bits (for on-chip solution three bits are required) to align with the optimum sampling instant which is very fast compared to existing literature and hence has ultra-fast settling capability. The circuit requires 2364 transistors and the area occupied is 0.069mm². Power consumption is also low being 7.26 µW while bit error ratio less than 10⁻³ was achieved for different parameter settings. The receiver design has been targeted for implant telemetry in the 402-405 MHz frequency band.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and analysis of 2 × 1 MIMO antenna with inverted E-shaped unit cell for high isolation","authors":"B. Elizabeth Caroline,&nbsp;K. Sagadevan,&nbsp;J. Vidhya,&nbsp;K. Mangaiyarkarasi","doi":"10.1007/s10470-025-02373-5","DOIUrl":"10.1007/s10470-025-02373-5","url":null,"abstract":"<div><p>Wireless communication technology extensively explores and optimizes key parameters within a Multiple Input Multiple Output (MIMO) antenna system, with a primary emphasis on achieving high isolation and low correlation. The focus is to enhance the gain and Envelope Correlation Coefficient (ECC) while prioritizing diversity and Voltage Standing Wave Ratio (VSWR) optimization for 2*1 patch antenna. Through systematic design, simulation, and practical implementation, significant signal strength and reliability improvements are targeted. The directional focus will be finely tuned to maximize performance by adding 1–5 unit cells of the inverted E-shaped (IES) structure to improve the isolation. This work aims to provide valuable insights for developing high-performance MIMO antennas, with applications across evolving wireless communication technologies, by improving the performance in terms of correlation and isolation. The Proposed MIMO antenna has a very low ECC value of 0.001, diversity of 9.99 dB, VSWR of 1.32, and gain of 0.23 at 5.8 GHZ.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}