Analog Integrated Circuits and Signal Processing最新文献

{"title":"Novel approximate Booth multipliers (ABm-eRx) based on efficient encoding and reduction for error-tolerant applications","authors":"Jayasheela Moses,&nbsp;Sukanya Balasubramani,&nbsp;Umapathi Krishnamoorthy","doi":"10.1007/s10470-025-02365-5","DOIUrl":"10.1007/s10470-025-02365-5","url":null,"abstract":"<div><p>Energy efficient and performance optimised multiplier hardware is of high demand as they are the fundamental and most significant block in every signal processing and computing unit. In addition, they are the most power-hunger blocks too. Thus, in this article, two novel and efficient Booth encoded multiplier architectures are proposed utilising approximate computing techniques. Efficient optimisation with good accuracy is achieved by using a combination of approximate encoding and approximate partial product reduction. The multiplier architectures ABm-eR1 and ABm-eR2 are implemented in Xilinx. Results reveal that the multipliers ABm-eR1, ABm-eR2 consume 9% and 10% lesser area in terms of LUTs along with noticeable power and delay reduction when compared to exact Booth encoded architecture. Simulations depict a minimal error of 1.31 × 10^–3 NMED which is on-par with existing approximate multipliers. In addition, the multipliers ABm-eR1 and ABm-eR2 when evaluated across image multiplication, sharpening and smoothing produced a PSNR of 42.27 db, 41.19 db, 40.26 db and 40.61 db, 39.32 db, 39.05 db respectively. These results demonstrate that the proposed multiplier architectures perform on-par with the existing approximate Booth multipliers when used for image processing applications. Intrinsic to their efficient performance, the proposed architectures are good candidates for realising error-resilient applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a high-gain N-path filter with harmonic rejection","authors":"Shuxiang Song,&nbsp;Changping Liu,&nbsp;Pinqun Jiang,&nbsp;Mingcan Cen","doi":"10.1007/s10470-025-02374-4","DOIUrl":"10.1007/s10470-025-02374-4","url":null,"abstract":"<div><p>This paper presents an enhanced N-path filter architecture addressing the fundamental limitations of conventional designs in wireless communication systems. The proposed solution tackles two critical challenges: insufficient harmonic rejection and signal loss. By integrating a high-gain low-noise amplifier (LNA) at the input stage and implementing a novel transconductance amplifier-based weighted sinusoidal signal fitting technique, the filter achieves superior performance metrics. Implemented in SMIC 180 nm CMOS technology, the design demonstrates frequency tunability from 800 MHz to 1.2 GHz. Simulation results show third and fifth harmonic rejection ratios of 61 dB and 67 dB, respectively. The filter exhibits a gain of 21 dB with a noise figure of 8–9 dB and an IIP3 of <span>(-)</span>6.2 dBm. These results represent a significant advancement over traditional N-path filter implementations, offering promising prospects for practical wireless applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Very compact ultra-wideband slot antenna with integrated LTE band","authors":"Boualem Hammache,&nbsp;Idris Messaoudene,&nbsp;Abderraouf Messai,&nbsp;Arun Kesavan,&nbsp;Tayeb A. Denidni","doi":"10.1007/s10470-025-02382-4","DOIUrl":"10.1007/s10470-025-02382-4","url":null,"abstract":"<div><p>This work presents a very compact ultra-wideband (UWB) slot antenna with an integrated long-term evolution (LTE) band at 2.6 GHz. The slot UWB antenna has a small size of 24 mm × 8 mm × 1.524 mm. Additional elementary slots (stepped slots) are etched in the back side of the antenna to obtain an UWB range by assembly the resonance frequency of each elementary slot. An F-shaped slot is integrated into the back side of the antenna to create a resonance frequency in the LTE band. For the experimental results, the proposed antenna provides two resonance frequency bands. The first mode is an UWB bandwidth between 3.1 and 12 GHz, and the second one operates at the LTE band between 2.58 and 2.73 GHz, where the reflection coefficient is less than − 10 dB. The radiation characteristics of the antenna are omnidirectional in the horizontal plane and bidirectional in the vertical plane. A good agreement is shown between the measured and simulated results in terms of impedance matching and radiation pattern.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reducing impulsive noise in active noise control systems using FxLMS algorithm based on soft thresholding techniques","authors":"V. Saravanan,&nbsp;N. Santhiyakumari,&nbsp;P. Shanmuga Sundaram","doi":"10.1007/s10470-025-02380-6","DOIUrl":"10.1007/s10470-025-02380-6","url":null,"abstract":"<div><p>Impulsive noise significantly impacts signal quality and system performance, necessitating effective methods for its reduction. This paper introduces two adaptive filtering techniques based on the FxLMS algorithm, designed to address this challenge. The first method employs dynamic input thresholding, incorporating gradient-based and SNR-driven adjustments to suppress impulsive noise while retaining essential signal components. The second method builds on this by introducing hybrid thresholding applied to both input signals and filter coefficients, supported by double error smoothing to improve stability and adaptability under varying noise conditions. To evaluate the proposed methods, a comparative analysis is conducted with the Variable FxLMS Hybrid Thresholding (VFxLHT) technique, considering metrics such as steady-state noise suppression and computational efficiency. The results demonstrate that the proposed methods perform reliably across diverse noise conditions, maintaining signal fidelity while efficiently utilizing computational resources. These methods are intended as practical solutions for applications where impulsive noise control is essential to ensure reliable system operation without excessive computational complexity.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast and ultra-low energy subthreshold level shifter using split-gate buffer for low-power digital VLSI systems","authors":"S. A. Sivakumar,&nbsp;B. Senthilkumar,&nbsp;Selvakumar Rajendran","doi":"10.1007/s10470-025-02377-1","DOIUrl":"10.1007/s10470-025-02377-1","url":null,"abstract":"<div><p>Low-energy operation is predominant feature in the modern wireless sensor node and implantable biomedical applications. Scaling the supply voltage towards sub-/near-threshold level is vital design methodology to achieve energy-efficient operation. Voltage scaling can be adopted in the multiple supply voltage design incorporating interfacing circuit called voltage level shifters to attain power-efficient operation. This paper presents differential cascode voltage switch structure based high-speed and low-energy voltage level shifter for converting subthreshold voltage to nominal output voltage. The proposed level shifter (LS) utilizes NMOS/PMOS diode pairs along with the cross-coupled PMOS to address the current contention issue by suppressing the current from pull-up network while pull-down network is activated. The switching speed of the level conversion is enhanced by pass transistor and boosting devices in the pull-down network. Further, split-gate inverter/buffer at the output stage ensures high performance by alleviating static power and accelerating speed performance. The proposed LS is implemented in CMOS 180 nm technology on Cadence (Virtuoso) platform and analyzed using Spectre circuit simulator. The simulation results reveal the subthreshold level conversion from 220 mV to 1.8 V and wider frequency range of conversion. In addition, it ensures the delay of 8.57 ns, energy/transition of 39.4 fJ for level conversion from 0.4 to 1.8 V with input signal frequency of 1 MHz. Moreover, the LS consumes static power of 0.302 nW at standby mode.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BCSSA-VMD and ICOA-ELM based fault diagnosis method for analogue circuits","authors":"Dazhang You,&nbsp;Shan Liu,&nbsp;Ye Yuan,&nbsp;Yepeng Zhang","doi":"10.1007/s10470-025-02360-w","DOIUrl":"10.1007/s10470-025-02360-w","url":null,"abstract":"<div><p>Analog circuits are an important component of integrated circuit systems, and circuit systems are the foundation for ensuring the normal operation of electronic devices. Therefore, it is necessary to efficiently diagnose and maintain faults in analog circuits. However, due to the tolerance, high nonlinearity, and susceptibility to environmental interference of analog circuit components, the development of related research on fault diagnosis has been hindered, and it cannot meet the current practical requirements for high safety and reliability of electronic devices. With the continuous increase in circuit scale and integration level, how to effectively and as much as possible extract more discriminative fault features is the key research direction of analog circuit fault diagnosis. Therefore, this article proposes a variational model decomposition (VMD) feature extraction method that combines Butterfly and Cauchy Sparrow search algorithms (BCSSA) and relies on an improved crayfish optimization algorithm (COA) to optimize the Extreme Learning Machine (ELM). Decomposition (VMD) feature extraction method, and rely on Improved Crayfish Optimization Algorithm (COA) Optimized Extreme Learning Machine (ELM) to complete the classification of faults. Firstly, the BCSSA algorithm is used to optimize the number of VMD decomposition modes K and the penalty factor <i>α</i> to achieve the optimal VMD decomposition of the original fault signal, obtain a series of Intrinsic Mode Function (IMF) and calculate its envelope entropy, determine the optimal IMF component by selecting the IMF component with the lowest envelope entropy., and calculate its time-domain parameter, then normalize and reduce the dimensionality to construct the vector that contains the characteristics of the fault. The normalized dimensionality reduction process constitutes the fault feature vector; secondly, the ICOA algorithm is introduced to optimize the ELM; Ultimately, the fault feature vector is fed into the ELM to acquire the fault diagnosis results. The simulation test examples of the Sallen-Key bandpass filter circuit and the Four-op-amp circuit show that the accuracy of the proposed improved VMD and ELM fault diagnosis method is as high as 99.68%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Insights of quad port MIMO antenna for 5G NR n77/n79 to X-bands with reconfigurable grounds using PIN diodes","authors":"Gayatri Tangirala,&nbsp;Srinivasu Garikipati,&nbsp;Manikya Krishna Chaitanya Durbhakula,&nbsp;Virendra Kumar Sharma","doi":"10.1007/s10470-025-02366-4","DOIUrl":"10.1007/s10470-025-02366-4","url":null,"abstract":"<div><p>This manuscript explores the development of a quad-port Multiple-Input-Multiple-Output (MIMO) antenna featuring reconfigurable grounds tailored for 5G NR n77/n79 and X-band applications, utilizing PIN diodes. The research begins with the evolution of a single unit Ultra Wideband antenna, which is subsequently expanded to a reconfigurable grounds 2 × 2 MIMO antenna controlled by a single PIN diode. Further to a reconfigurable grounds 4 × 4 MIMO antenna managed by four PIN diodes. This work is innovative in its approach, as it examines and designs MIMO antennas that can switch between unconnected and connected ground states through reconfiguration techniques. This MIMO antenna is printed on a FR4 substrate, with dimensions of 0.597λ₀ × 0.448λ₀ × 0.0171λ₀ mm³, where λ₀ is determined based on the lowest resonating frequency. It operates across a frequency range of 3.2–12 GHz with connected grounds. In the majority of the band the designs show mutual coupling  ≤  − 15 dB. The performance is assessed at every stage and graphs are compared for both unconnected and connected grounds. The inferences are included on all the metrics like gain, isolation, efficiency, radiation patterns, S-parameters, Mean Effective Gain, Channel Capacity Loss, Diversity Gain, Envelope Correlation Coefficient, and Total Active Reflection Coefficient. The stub introduced to connect the grounds itself act as an efficient decoupling network. The printed MIMO performance results are matches with simulated results. This work has 5G wireless applications including RF energy harvesting and cognitive radio.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Blind 2-microphone acoustic noise reduction algorithms using efficient variable step-size adapted by minimizing the intercorrelation function","authors":"Redha Bendoumia","doi":"10.1007/s10470-025-02335-x","DOIUrl":"10.1007/s10470-025-02335-x","url":null,"abstract":"<div><p>Recent advancements in adaptive noise signal reduction have utilized 2-microphones adaptive algorithms. Specifically, the normalized form of least-mean-square algorithm (NLMS) with fixed-step-size parameters (FS) has been combined with direct-and-recursive structures of source separation. Compared to conventional one-microphone methods, these combinations provide superior speech quality. However, the main limitation of these 2-microphones adapting algorithms (Direct combination: Forward NLMS and Recursive combination: Backward NLMS) lies in their poor steady state regime with large FS value, while small step-sizes values result a slow speed of convergence. To address these issues, we propose a new variable step-size (VS) approach in this study, based on minimizing the intercorrelation function in the time domain for the basic FNLMS and BNLMS algorithms. Our approach is proposed exactly to determine an optimal value of VS parameters by minimizing the intercorrelation between the enhanced signal and the noisy microphone signals. These methods improve steady state values and convergence speed at the same time. The proposed 2-microphones adapting algorithms were evaluated through simulations conducted in high-noise environments, using the system of mismatch criterion and estimation of output segmental signal-to-noise ratio ones. The comparative simulations results confirmed that our algorithms outperform FS algorithms in terms of steady state values and convergence speed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of array system configuration using the smoothed-pad algorithm","authors":"Mario Batubara,&nbsp;Timbul Manik,&nbsp;Peberlin Sitompul,&nbsp;Musthofa Lathif","doi":"10.1007/s10470-025-02362-8","DOIUrl":"10.1007/s10470-025-02362-8","url":null,"abstract":"<div><p>The source of astronomical objects, in general, is a very far distance from the observation instrument so that the transmitted signal is received very small and is at risk of being disturbed by other sources around the receiving system. Therefore, the concept of multiple receivers with array interferometry configuration arrays is used to improve the quality of the source signal detected by the receiving system. The position of each receiving system, known as the antenna pad, determines the quality performance of the received signal output. The antenna positions are arranged in a discrete grid system so that there is a vacancy between antenna pads. In this paper, a computational technique is present to overcome the region’s emptiness between one antenna to its neighbor. As an initial result, the integrating of each position with its neighboring pads with some of its smoothing functions is optimal in filling the void region and maximizing the u-v coverage.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low power high speed 14T-TSPC-DomDFF design and analysis in CMOS 16nm technology","authors":"Ramsha Suhail,&nbsp;Pragya Srivastava,&nbsp;Richa Yadav,&nbsp;Nandini Baliyan,&nbsp;Rewa Chaudhary","doi":"10.1007/s10470-025-02371-7","DOIUrl":"10.1007/s10470-025-02371-7","url":null,"abstract":"<div><p>Utilised in a range of applications such as registers, counters, and state machines, the D Flip-Flop (DFF) is a flexible device that has undergone development over time with innovative design approaches to enhance power efficiency. True Single Phase Clock (TSPC) logic has constantly been a preferred option in high-speed applications. This work introduces an enhanced 14 Transistor TSPC-based positive edge-triggered Domino DFF (TSPC DomDFF) at 16 nm with a Clock-to-Q (CQD) latency of 55.4ps, improved power consumption of 96.8nW, and salient Power Delay Product (PDP) and Energy Delay Product (EDP) as 5.36aJ and 0.297aJ-ns, respectively, at an operating voltage of 0.9 V. It showcases the performance of a high speed and power efficient design with 32%, 77%, 85%, 94% improvement in PDP with respect to MTSPC, 26TSPC, 18T HFF, and MSDFF respectively. The results are validated through detailed robust analysis. Furthermore, the proposed 14T TSPC DomDFF is implemented to construct a 4-bit Serial-in-Serial-out (SISO) Shift Register (4-SISO SR) at operating frequency of 5 GHz. The improved results enabled the physical layout design to be accommodated within an optimized area of 3.7µm² for the proposed circuit and 15.4µm² for the proposed application.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"123 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}