Analog Integrated Circuits and Signal Processing最新文献

{"title":"Impact of trap states and steric effects on Ge-source V-TFET based pesticide biosensor","authors":"Aravind Madhav,&nbsp;Neha Paras","doi":"10.1007/s10470-026-02619-w","DOIUrl":"10.1007/s10470-026-02619-w","url":null,"abstract":"<div><p>This paper presents a vertically tunneled Ge-source TFET pesticide biosensor in which device design, pesticide–HfO₂ interaction, and realistic non-idealities collectively determine sensing performance. The vertical band-to-band tunneling junction is modulated by adsorption of glyphosate molecule on the HfO₂ surface. The influence of biomolecular charge density (–3 × 10¹³, 0, + 3 × 10¹³ cm²) is examined in terms of drain current, surface potential, subthreshold slope, I_on/I_off, sensitivity, and linearity metrics such as IIP₃, VIP₃, and IMD₃. The results show that positive biomolecular charge enhances band bending and carrier injection, resulting in improved tunnelling efficiency and higher sensitivity, whereas negative charge increases the tunnelling barrier and weakens the sensing response. Fill-factor analysis indicates that increased biomolecular occupancy strengthens electrostatic coupling and improves sensitivity. Positional analysis further shows that biomolecules located near the gate oxide/sensing region provide stronger channel-potential modulation and higher sensitivity. The effect of trap-assisted tunnelling is evaluated for semi-filled cavity configurations, where TAT modifies the total drain-current response and enhances I_ds sensitivity in selected cases. Steric and repulsive steric effects significantly alter effective capacitance, electric-field distribution, tunnelling behavior, and sensing accuracy, revealing a trade-off between electrostatic current enhancement and chemical sensing sensitivity. This study shows that optimization of biosensor structure, analyte arrangement, fill factor, and trap mitigation is essential for reliable and high-performance pesticide detection.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148614315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Convergence-driven metaheuristic framework for pareto-optimal VLSI floorplanning using ACSBO-QIFA","authors":"M. Prema,&nbsp;T. Vaishnavi,&nbsp;G. Merlin Suba,&nbsp;Gunaselvi Manohar","doi":"10.1007/s10470-026-02615-0","DOIUrl":"10.1007/s10470-026-02615-0","url":null,"abstract":"<div><p>The persistent advancement of Very-Large-Scale Integration (VLSI) technology continues to place increasing demands on floorplanning techniques to achieve a maximum optimization of chip area, interconnect wirelength, and heat dissipations-destructive to performance, power consumption, and reliability. A classical optimization technique would face problems such as premature convergence, sub-optimal trade-offs, and scalability with respect to multi-objective scenarios. The aim of the study is to develop and characterize a novel hybrid metaheuristic framework, viz. ACSBO-QIFA, which integrates AC-SBO with QIFA. The ACSBO-QIFA approach used the chaotic dynamics for enhanced global exploration and the quantum-inspired mechanisms for accurate local refinement, providing a strong convergence behavior whisking-away from local optima. For evaluation, a dynamically weighted multi-objective fitness function was constructed with varying emphasis placed on area, wirelength, and thermal constraints, enabling flexible prioritization of design goals. The experimental verification conducted on MCNC benchmark circuits (apte, ami33, ami49, xerox, hp) proved its supremacy, even better than the latest methods. The new ACSBO-QIFA framework provides major advancements compared to existing solutions based on wirelength reductions (up to 3.60% on hp), lower temperatures (up to 3.92% on apte), and an overall area decrease of nearly 1.27% on xerox. On average for all the tests performed, the respective wirelengths were reduced by 1.82%, temperatures decreased by 2.34%, and the areas decreased by 0.47%. Collectively, these results demonstrate the excellent ability to optimize multiple objectives simultaneously. The demonstrated results add to the confidence in the ACSBO-QIFA for the generation of Pareto-optimal floorplanning, thus proposing it to be an efficient and high-scalable solution to challenges in modern VLSI design. The work creates the next roadmap for floorplanning tools to escort the balance between computational efficiency and constraints in varying semiconductor technologies.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148614027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power-aware Lorentz-equivariant quantum graph neural network for accurate power estimation in CMOS-VLSI circuits","authors":"Satyaraj D,&nbsp;Vigneash L,&nbsp; Priyadharsini,&nbsp;Kondru Venkata Murali Siva Prasad","doi":"10.1007/s10470-026-02603-4","DOIUrl":"10.1007/s10470-026-02603-4","url":null,"abstract":"<div><p>The Complementary Metal-Oxide Semiconductor–Very Large Scale Integration (CMOS-VLSI) scalability has introduced increased power density and energy consumption in recent years. Modeling complex relationships among integrated circuit components remains challenging. Existing models fail to capture interactions under varying conditions, limiting accurate power prediction. In this paper, a Power-Aware Lorentz-Equivariant Quantum Graph Neural Network for Accurate Power Estimation in CMOS-VLSI Circuits (PLEQGN-VLSI-RPEE) is proposed. Initially, ISCAS’89 benchmark circuits are modeled as directed graphs, capturing both combinational and sequential behaviors through node features such as switching activity and electrical parameters. Then, Power-Aware Lorentz-Equivariant Quantum Graph Neural Network (PLEQGN) estimates power by capturing spatial-temporal dependencies via Lorentz-equivariant message passing and quantum-inspired encoding, while power-aware attention emphasizes high switching activity nodes to improve estimation accuracy in combinational and sequential circuits. Finally, House Swallow Optimization (HSO) is employed to optimize network weights and biases, minimizing estimation error. The proposed PLEQGN-VLSI-RPEE method is implemented in Python, and its performance is evaluated using several metrics such as Mean Square Error (MSE), correlation coefficient, power consumption prediction, and time complexity. The proposed PLEQGN-VLSI-RPEE approach achieved superior results, with an MSE of 0.23 mW, a correlation coefficient of 0.96, and a predicted power of 0.89 mW, thereby outstripping existing methods.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148459132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a novel high-performance, energy-efficient, and area-optimized quadcross urdhva tiryakbhyam vedic multiplier","authors":"A. Arul,&nbsp;M. Kathirvelu","doi":"10.1007/s10470-026-02609-y","DOIUrl":"10.1007/s10470-026-02609-y","url":null,"abstract":"<div><p>This research presents the design and implementation of a novel QuadCross Urdhva Tiryakbhyam (QCUT) Vedic multiplier utilizing the Urdhva Tiryakbhyam sutra to enhance the arithmetic computation efficiency. The proposed multiplier design integrates novel AND gates and hybrid half- and full-adder circuits. The novel multiplier circuit operates at high speed and relies significantly on the innovative 6 T-AND gate circuits. The proposed 6 T-AND gate circuit combines an inverter, a transmission gate, and a pull-down network using pass transistor logic to ensure error-free outputs. The proposed hybrid half-adder circuit uses an XOR-AND gate configuration to optimize the chip die area and reduce the average power consumption of these multiplier circuits. Specifically, the novel XOR circuit incorporates an inverter, a 2-to-1 mux, and pass transistor logic. The novel Vedic multiplier circuit integrates with hybrid full-swing adder (HFSA) circuits, which increase overall efficiency. Our innovative 4 × 4 QCUT Vedic multiplier demonstrated outperformance compared to its counterparts, achieving an average power of 103.64 μW, remarkably low delays of 335.26 ps, and a superior average PDP of 34.75 fJ. Using the Cadence Virtuoso software with GPDK 45 nm technology within the ADEXL and LayoutXL design environment suites ensured the consistency of all circuits. This proposed method effectively combines the ancient Urdhva Tiryakbhyam (UT) sutra with the novel QuadCross technique to address contemporary problems in electronics and digital computing. It demonstrates the efficiency, scalability, and versatility of these proposed methods for the next-generation digital multipliers.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 2","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148459133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The role of asymmetry in elevating nanosheet FET: RF and circuit metrics","authors":"Raj Saha,&nbsp;Anubhab Saha,&nbsp;Akash Mandal,&nbsp;Tridib Kar,&nbsp;Subir Kumar Maity,&nbsp;Udai P. Singh,&nbsp;Rajendra Prasad","doi":"10.1007/s10470-026-02614-1","DOIUrl":"10.1007/s10470-026-02614-1","url":null,"abstract":"<div><p>This study details the design of an asymmetric source-drain (S/D) nanosheet FET (NSFET) featuring a silicon-germanium (SiGe) source. Furthermore, it includes an analysis of its DC, AC, and RF characteristics, as well as the performance of a resistive-load inverter. The performance metrics have been compared with a bulk NSFET of the same effective width (<span>(W_{textrm{eff}})</span>). The SiGe source lowers the source channel barrier via conduction-band offset and bandgap narrowing, enabling stronger electron injection. As a result, the asymmetric S/D NSFET exhibits higher drain current in strong inversion and improved transconductance (<span>(g_m)</span>), ON current (<span>(I_{ON})</span>), cutoff frequency (<span>(f_T)</span>), and transconductance frequency product (TFP), highlighting its suitability for high-frequency RF/microwave and high-speed digital/sensing applications. The off-state current (<span>(I_{OFF})</span>) remains approximately the same for both devices, indicating that the source engineering improves the ON-state performance without significantly affecting leakage. In addition, gate leakage remain comparable to the bulk NSFET, while subthreshold swing and DIBL show minimal variation. Circuit-level evaluation with a resistive-load inverter shows a slightly steeper voltage-transfer characteristic and higher small-signal gain <span>(A_v = partial V_{out}/partial V_{in})</span> than the bulk NSFET, underscoring its potential as an effective amplifier.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148465881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unveiling the impact of ITCs on High-k SOI GaN FinFET and its sensitivity analysis for improved reliability: a simulation study","authors":"Vandana Singh Rajawat,&nbsp;Bharat Choudhary,&nbsp;Ajay Kumar","doi":"10.1007/s10470-026-02617-y","DOIUrl":"10.1007/s10470-026-02617-y","url":null,"abstract":"<div><p>This study examined the effects of different interface trap charges on High-k SOI GaN FinFET at short channel length, and the outcomes were contrasted with those of Si FinFET. The analog performance is compared through parameters such as subthreshold swing (SS), current ratio (I_ON/I_OFF) and threshold voltage (V_Th). Acceptor traps affect both devices more than donor traps do, due to their tendency to become positively charged and unscreened under typical operating conditions. High-k SOI GaN FinFETs have lower V_Th and SS shifts (5% &amp; 1.3%, respectively) than Si FinFETs (11% &amp; 23%, respectively) due to a combination of factors, including a higher bandgap and larger oxide capacitance. Also, the effect of temperature on the DC parameters of the proposed device under various trap charges has been investigated. Furthermore, sensitivity analysis for the proposed device under donor and acceptor trap charges, varying temperature, metal work function, and various doping concentrations across the source, drain, and channel regions, has been performed. Results reveal that the proposed device is more sensitive to acceptor traps than to donor traps. Under acceptor traps, the proposed device provides sensitivities of 100, 98, 108, and 101 for metal work function, source doping, drain doping, and channel doping variation, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148465836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4.9 GS/s strongarm latch comparator topology with offset correction in 32-nm","authors":"Chokkakula Ganesh,&nbsp;A. Murali,&nbsp;B. Vamsy Krishna,&nbsp;T. Ananda Babu,&nbsp;Girraj Sharma,&nbsp;Asisa Kumar Panigrahy,&nbsp;M. Durga Prakash","doi":"10.1007/s10470-026-02611-4","DOIUrl":"10.1007/s10470-026-02611-4","url":null,"abstract":"<div><p>In mixed-signal integrated circuit design, comparators are essential, especially for low-power, high-speed applications such as data converters, communication systems, and portable devices. Conventional comparator designs often struggle to balance speed and power efficiency. This paper proposes a low-power, high-speed modified strongARM latch circuit topology with an offset correction. The proposed design performance is compared with open-loop, preamplifier latch-based, and strongARM latch comparators. The proposed design incorporates innovative architectural modifications to enhance speed, power efficiency, and offset. The proposed comparator achieves significant delay reductions of 61%, 55%, and 47% compared to the open-loop, preamplifier latch-based, and strongARM latch comparators, respectively. Furthermore, the proposed design achieves a 30.7% reduction in dynamic power dissipation compared to the strongARM design. PVT analysis was performed by evaluating the design across standard corners (TT, FF and SS) and under a 5% drop in supply voltage (1.0 V to 0.95 V). The offset correction mechanism of the proposed comparator significantly increases the number of successful output samples, which can be observed through Monte Carlo simulation using Synopsys Custom Compiler at a 32 nm technology node.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148465581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A self-correcting signal quantization based on error correcting codes","authors":"Gaël Mahé,&nbsp;Fatimetou El Jili,&nbsp;Mamadou Mboup","doi":"10.1007/s10470-026-02613-2","DOIUrl":"10.1007/s10470-026-02613-2","url":null,"abstract":"<div><p>We propose a quantization method that makes a signal correctable after it has been corrupted by noise. The principle is to replace each bit level in the binary representation of each vector of time or time-frequency samples by a codeword of the same length, provided by an error-correction coder. Thus, assuming that the amount of errors does not exceed the correction capabilities, decoding each bit level of the noisy signal can suppress the noise. We demonstrate how to determine the necessary error correction capability for each bit level based on the signal and noise probability density functions along with the desired binary error probability. The codewords are chosen from codebooks with the adequate error correction capabilities so as to minimize the quadratic error between the original and the quantized signals, utilizing a modified matching pursuit algorithm. Applying this quantization method on a speech signal transmitted through a noisy channel demonstrates that it is possible to choose a set of coders so that the noise resulting from the quantizing-channel-decoding chain is less annoying than the channel noise alone.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148465295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An FSK generator using CFOAs and electronically-controllable CMOS resistors","authors":"Manish Rai,&nbsp;A. K. Singh,&nbsp;Raj Senani","doi":"10.1007/s10470-026-02610-5","DOIUrl":"10.1007/s10470-026-02610-5","url":null,"abstract":"<div><p>In this paper, a frequency shift keying (FSK) modulation scheme has been proposed which is based upon a current feedback operational amplifier (CFOA)-based oscillator, two CMOS floating voltage-controlled positive resistors (FVCPR) and a CFOA-based auxiliary circuit for providing an appropriate DC bias signal and the modulating signal to the two FVCPRs. An advantageous feature of the proposed scheme is that, since all the subcircuits of the oscillator have a gain of unity at all frequencies, the amplitude of the output FSK waveform remains constant when frequencies are switched between two values and hence, no external amplitude stabilization circuit is needed. The workability of the proposed design has been demonstrated by SPICE simulations.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148465475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.439 (ppm/^circ{rm C} ) CMOS bandgap reference with 4(sim )40V supply-range and high-order curvature compensations","authors":"Chunlai Wang,&nbsp;Shaobin Zhu,&nbsp;Yugeng Zhang,&nbsp;Muhammad Ahsan Farooq Qaisar,&nbsp;Weihua Han","doi":"10.1007/s10470-026-02604-3","DOIUrl":"10.1007/s10470-026-02604-3","url":null,"abstract":"<div><p>This paper demonstrates a high-precision bandgap reference (BGR) that features a wide input voltage range and high-order temperature compensation. The design achieves an extremely low temperature coefficient (TC) across a wide –40℃ to 160℃ operating range. This low TC is enabled by a novel multi-segment curvature compensation (MSCC) circuit, which incorporates subtraction-addition circuits with current mirror techniques based on a conventional current-mode BGR. Furthermore, a pre-regulator is incorporated to extend the input range from 4 to 40 V, thereby improving immunity to supply voltage variations. The designed BGR is fabricated using a 0.18 µm Bipolar–CMOS–DMOS (BCD) process. Simulation results demonstrate a stable voltage of <span>(1.2 V)</span> over the full temperature range, with a TC of only <span>(0.439 ppm/^circ{rm C}. )</span> Additionally, the power supply rejection ratio (PSRR) respectively reaches <span>(-129.5 dB)</span> at 10 Hz,<span>(-123.8 dB)</span> at 1 kHz, and <span>(-72.7 dB)</span> at 100 kHz.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148465476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}