Analog Integrated Circuits and Signal Processing最新文献

{"title":"Exploration of low area-high speed by hybrid method of Radix-8 Booth encoding and Vedic multiplier","authors":"C. M. Kalaiselvi,&nbsp;R. S. Sabeenian","doi":"10.1007/s10470-025-02339-7","DOIUrl":"10.1007/s10470-025-02339-7","url":null,"abstract":"<div><p>As technological scalability reaches its limitations, novel techniques for computing efficiency have been explored. Three different, high-speed, low-area systems for multiplying two signed numbers were proposed. An innovative architecture was introduced by implementing both the techniques of Booth encoding and Vedic Multiplication sutras by improving the area and speed. Three different architectures of radix encoding (i.e.) Radix-8 with the Vedic multiplier are proposed in this paper. To examine the benefits of rapid arithmetic units, hybrid Booth encoding with Vedic multiplier (Urdhva Tiryakbhyam sutra) was implemented and simulated using Xilinx ISE 14.7 and Xilinx Vivado 2019.1 with FPGA and in ASIC 45 nm TSMC CMOS technology. The proposed design is found to have a high speed with minimal area consumption and includes a variety of cutting-edge architecture. For Hybrid Booth-Vedic-Radix-8 encoding (HBVR-8), the findings show that the proposed multiplier decreases area by 92.7%, 94.9%, and 95.4% for the three proposed architectures. The Area-Delay Product (ADP) was reduced by 1%, 41% and 51% for all three proposed architectures. The findings show that the provided method works better than the alternatives previously offered in the literature, despite the reached configurability and affordable design.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143396527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Systems classification of air pollutants using Adam optimized CNN with XGBoost feature selection","authors":"S. Prakash,&nbsp;K. Sangeetha","doi":"10.1007/s10470-025-02299-y","DOIUrl":"10.1007/s10470-025-02299-y","url":null,"abstract":"<div><p>Since air pollutants released by motor vehicles have a bigger impact on human health than other air pollutants, air pollution is currently a very severe issue. Forecasting air quality has been used to control air pollution, as has public warning. The approaches existing today have many drawbacks like lower accuracy, lower performance, and high dimensionality problem, and hence to overcome all these drawbacks, the proposed method has been introduced. To classify the air pollutants in the dataset, a Convolution Neural Network (CNN), and eXtreme Gradient Boosting (XGBoost) based model (XGB-CNN) has been proposed. By using XGBoost to choose features from the pre-processed data, the number of parameters, high dimensionality issue, and training time are all decreased. Also, Adam optimizer is enhanced using power exponent learning rate to eliminate issues in fixed learning rate. CNN is used to categorize air pollutants into four types: sulfur dioxide (SO₂), ozone (O₃), nitrogen dioxide (NO₂), and carbon monoxide (CO) based on the Air Quality Index level of specified features. In terms of accuracy, F1-score, precision, recall and the effectiveness of the proposed XGB-CNN is compared to Decision Tree, Logistic Regression, k-Nearest-Neighbor, and Support Vector Machine, Long Short-term memory. It has also been shown that the proposed XGB-CNN method outperforms the existing systems in terms of efficiency by 5%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143373389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new design of an efficient configurable circuit based on quantum-dot technology for digital image processing","authors":"Ligang Tang,&nbsp;Tong Kong,&nbsp;Saied Seyedi","doi":"10.1007/s10470-025-02337-9","DOIUrl":"10.1007/s10470-025-02337-9","url":null,"abstract":"<div><p>Image processing is the computational manipulation and analysis of digital images, encompassing various techniques and algorithms to enhance, transform, segment, and extract meaningful information from images. It plays a vital role in various fields, including computer vision, medical imaging, remote sensing, and entertainment, enabling tasks like object recognition, image enhancement, and pattern detection by utilizing methods such as filtering, edge detection, and machine learning to process visual data and extract valuable insights. Image processing circuits play a pivotal role in digital circuits, with Quantum-dot Cellular Automata (<i>QCA</i>) technology emerging as a viable option for nano-scale circuit implementation. While QCA presents an enticing avenue for circuit design, it has faced setbacks due to a notable prevalence of fabrication defects, thereby instigating a compelling area of exploration within QCA circuitry. Simultaneously, the significance of morphological operation circuits in digital circuits and image processing system design cannot be overstated. In this context, the present study undertakes the challenge of crafting a distinctive QCA-based morphological operations circuit that excels in area efficiency, robustness, and fault tolerance. Within the realm of QCA nano-technology, integrating fault-tolerant gates and cell redundancy emerges as a key strategy to ensure fault tolerance. A prime example is using a <i>5-input fault-tolerant</i> majority gate, ingeniously harnessed to construct an efficient fault-tolerant morphological operations circuit. To materialize this endeavor, the <i>QCADesigner-E</i> tool takes center stage and is employed to meticulously implement the devised circuits. The outcomes of this endeavor, including evaluations of single-cell defects, quantum cost, area utilization, and delay time, unequivocally demonstrate the superiority of the designed QCA circuit compared to its predecessors. Notably, the engineered circuit boasts a minimal delay of approximately <i>0.75 clock cycles</i>, marking a significant stride forward from previous QCA circuitry. In the wake of previous challenges that plagued QCA circuits, strides have been made to rectify these issues, fostering a burgeoning landscape of fault-tolerant and resilient QCA-based solutions. The amalgamation of image processing and fault-tolerant circuitry promises to unlock new vistas for advanced digital systems in the nano-scale domain.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the design of a level-crossing ADC with 1-bit DAC and rail-to-rail continuous-time comparator","authors":"Fereshte Shahbazi,&nbsp;Hossein Shamsi","doi":"10.1007/s10470-025-02344-w","DOIUrl":"10.1007/s10470-025-02344-w","url":null,"abstract":"<div><p>A level-crossing ADC, which includes a 1-bit DAC, a rail-to-rail continuous-time comparator and a 3-stage continuous-time comparator, has been simulated in 0.18 μm CMOS process with 0.8 V supply voltage. Interpolation between samples has been used to add more samples to the original signal and reconstruct ADC’s output signal. The ADC has SNDR of 47.2 dB (with polynomial interpolation), ENOB of 7.5-bit and power consumption of 460 nW for 1 kHz sinusoidal input signal with common-mode voltage of 400 mV and amplitude of 800 m<span>(:{text{V}}_{text{P}text{P}})</span>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143370045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PAPR reduction and low power-consumption LDO in OFDM transceiver","authors":"Liu Bing,&nbsp;Wu Hong","doi":"10.1007/s10470-025-02341-z","DOIUrl":"10.1007/s10470-025-02341-z","url":null,"abstract":"<div><p>The article mainly discusses the method of reducing PAPR of multi-carrier modulation transmitters in portable application. We firstly discussed the phase noise in OFDM system by power-supply disturbance, and some common algorithms to suppress PAPR. Further we propose an improved structural circuit of the non-capacitor LDO in the transmitter power supply, which can regulate the power load capacity to improve PAPR performance of OFDM transmitter. Based on the statistical information on sending data and precoder, we demonstrate that the power circuit can maintain a fast response and a lower average energy consumption. In addition, tests have shown that the proposed LDO circuit can maintain stable output voltage under conditions of rapid switches in load current values.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143370053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Metastability-based random number generator with current-controlled offset compensation","authors":"Yasin Talay","doi":"10.1007/s10470-024-02298-5","DOIUrl":"10.1007/s10470-024-02298-5","url":null,"abstract":"<div><p>The paper presents the design and measurement results of a metastability based true random number generator (TRNG) core, which was fabricated with HHGRACE 130-nm CMOS technology. Design and simulation results of a complete TRNG intended for hardware cryptographic systems, internet-of-things (IoT), smartcards and secure communication applications is also presented. Random numbers are generated from the differential noise occurring at the StrongARM comparator inputs. Tests were carried out at 0 <span>(^{circ })</span>C, 50 <span>(^{circ })</span>C and 70 <span>(^{circ })</span>C on two separate chips, which confirmed full compliance with NIST and AIS-31 randomness criteria. The proposed complete TRNG occupies 10000 <span>(upmu)</span>m<span>(^2)</span> area, and offers 30-Mbps throughput while consuming 1.35 mW for 1.5-V power supply voltage.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143369999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A compact quintuple band miniaturized elliptical planar monopole antenna for 5G/6G wireless systems","authors":"Digvijay Pandey,&nbsp;Manvinder Sharma,&nbsp;Rajneesh Talwar,&nbsp;Binay Kumar Pandey","doi":"10.1007/s10470-025-02310-6","DOIUrl":"10.1007/s10470-025-02310-6","url":null,"abstract":"<div><p>In the modern era of wireless communications, there is an ever increasing demand for compact antennas. The antennas that can operate across multiple frequency bands while effectively rejecting potential interfering signals. This need arises from the rapidly growing number of wireless systems and applications coexisting within the limited available spectrum. In this paper, elliptical monopole planar antenna with penta band notched characteristics is designed and fabricated for 5G/6G wireless system. The proposed antenna design incorporates two elliptical split ring resonators on the radiation patch to enable band rejection from 3.7 to 4.2 GHz for C band satellite communication along with 5.15–5.35 GHz for the lower WLAN band. A special metamaterial structure consisting of a two via double slot type EBG creates dual notches at 4.5–4.7 GHz for INSAT and 5.725–5.825 GHz for the upper band of WLAN. Additionally, In the vicinity of the feed line, a step impedance resonator suppresses the 7.95–8.55 GHz ITU band. This multi band notched characteristic makes the antenna suitable for applications requiring concurrent operation across multiple bands while mitigating interference from other co existing wireless services.The antenna is made with FR4 substrate and of a compact size of 38 × 38 × 0.8 mm³, making it suitable for integration into modern portable and wireless devices.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143370054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid fractal antenna design for UWB applications inspired by Giuseppe Peano and Sierpinski Carpet","authors":"Sanae Attioui,&nbsp;Asma Khabba,&nbsp;Lahcen Aguni,&nbsp;Saida Ibnyaich,&nbsp;Abdelouhab Zeroual","doi":"10.1007/s10470-025-02338-8","DOIUrl":"10.1007/s10470-025-02338-8","url":null,"abstract":"<div><p>This manuscript serves to introduce an ultra-wideband fractal antenna, which combines the Sierpinski carpet and Giuseppe Peano fractal structures along with a new developed ground geometry, intentionally created for ultra-wideband applications. The High Frequency Structure Simulator HFSS was employed to conduct a deep analysis on the suggested antenna, which is compact in size measuring <span>(30times 30times 1.6~textrm{mm}^{3})</span>. The proposed design can be employed for various purposes such as ultra-wideband applications, sub-6GHz 5 G applications, WIMAX, WLAN, C-Band, and X-Band for satellite communication, etc. The proposed fractal-based antenna has been carefully optimized through parametric study to function effectively across a frequency range spanning from 3.32 to 11.96 GHz and a maximum gain of 5.6 dB. To confirm the simulation outcomes and the operational bandwidth, The suggested fractal antenna prototype was fabricated utilizing the cost-effective FR4 substrate. The experimental and simulation results have shown a good concordance, which provides substantial evidence on the validity of the proposed design. Due to its wide impedance bandwidth good radiation performance and small footprint, the suggested antenna is highly recommended and considered as a good choice for ultra-wide band communication and other wireless applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143362015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An X-band high linearity rail-to-rail variable-gain LNA in 65 nm CMOS technology","authors":"Razieh Ghasemi,&nbsp;Hassan Daryanavard,&nbsp;Meisam Pourahmadi-Nakhli","doi":"10.1007/s10470-025-02311-5","DOIUrl":"10.1007/s10470-025-02311-5","url":null,"abstract":"<div><p>In this paper a low noise figure (NF) variable-gain low noise amplifier (VG-LNA) is presented. In the proposed circuit a gain cascaded branch is utilized to provide a rail-to-rail control voltage to vary the gain of LNA in a wide range and improve the dynamic range of the front-end receiver block. Besides, the gain of the proposed LNA is amplified by using a current reused technique with the rearrangement of its components, leading to an improvement of the total occupied area by more than 22%. The performance of the proposed VG-LNA is evaluated by the post-layout simulation results provided by TSMC 65 nm CMOS technology with a 1.2 V supply voltage. The simulation results demonstrate that the gain of the circuit is varied linearly from 15 to 24.2 dB by changing the control voltage from rail-to-rail. Besides, the proposed VG-LNA has an NF of less than 3.3 dB and S11 of better than − 23 dB in a wide temperature range while the power consumption is 9.3 mW @ 9.3 GHz center frequency. Also, the occupied area of the VG-LNA is 0.187 mm² (407 µm × 460 µm).</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ECRAAL: a high-performance multiplier design by efficient charge recovery asynchronous adiabatic logic","authors":"S. Nagaraj,&nbsp;G. M. Sreerama Reddy,&nbsp;S. Aruna Mastani","doi":"10.1007/s10470-025-02313-3","DOIUrl":"10.1007/s10470-025-02313-3","url":null,"abstract":"<div><p>Power consumption is one of the most important factors in modern digital signal processor (DSP) systems. A number of measures for minimizing power consumption, such as reducing supply voltage, switching activity, and capacitance, have been incorporated into the digital design of complementary metal oxide semiconductors (CMOS). However, these strategies don't work with the current CMOS design. As a result, this study concentrated on adiabatic logic, which has proven to be an outstanding way for developing low-power digital circuits. Adiabatic logic circuits return power to their source rather than release power as heat. So, in this research, novel and efficient charge recovery asynchronous adiabatic logic (ECRAAL)-based logic gates are developed to design a high-performance multiplier for high-speed digital circuits. The proposed adiabatic logic-based multiplier is designed using the Tanner EDA tool, and various performance metrics are used to assess the proposed multiplier's efficacy. The results analyzed show that the proposed 16-bit multiplier has a maximum propagation delay that is 38.46% and 16.46% less than Transmission Gate (TG) CMOS and Transmission-gate based Full Adder (TFA) designs, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}