Analog Integrated Circuits and Signal Processing最新文献_第6页

Integration of cascaded controllers for super-lift Luo converter with buck converter in solar photovoltaic and electric vehicle 太阳能光伏发电和电动汽车中超升罗转换器与降压转换器的级联控制器集成

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-20 DOI: 10.1007/s10470-024-02259-y

B. Ashok, Prawin Angel Michael

{"title":"Integration of cascaded controllers for super-lift Luo converter with buck converter in solar photovoltaic and electric vehicle","authors":"B. Ashok, Prawin Angel Michael","doi":"10.1007/s10470-024-02259-y","DOIUrl":"10.1007/s10470-024-02259-y","url":null,"abstract":"<div><p>Power electronic converters are utilized to regulate the charging voltage of electric vehicles (EV) batteries based on photovoltaic (PV), ensuring it falls within the desired range. Nevertheless, multi-port DC-DC converters have encountered challenges like bulky transformers and multiple switches, resulting in reduced reliability. To address these issues, this study presents super lift Luo and buck converter (SLBC) designed for the integration of PV and EV. The DC-DC converter presented in the work, integrated with SLBC, produces both step-up and step-down outputs from single input. The step-up output is achieved through the application of the super-lift method, enabling the elevation of voltage. This method allows for the generation of high-gain voltages using straightforward structures, eliminating the need for additional transformers or electric circuits for control and regulation. For fine tuning the duty cycle of the proposed converter, an efficient control scheme employing a cascaded structure of the TID (tilt integral derivative) with FOPID (fractional order proportional integral derivative with a filter), referred as the cascaded TID-FOPID controller is proposed. The tuning of the cascaded TID-FOPID controller parameters is accomplished using improved Harris Hawks optimization (IHHO). The analysis is carried out in the MATLAB platform and compared to various existing approaches. Analysed parameters include motor torque and speed, converter efficiency across duty cycles (0.1 to 0.6), frequency response, voltage gain comparative analysis among converters at a duty cycle of 0.6, voltage gain, voltage stress, and diode stress comparisons in the proposed converter. The efficiency attained by the proposed method reaches approximately 98%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"449 - 466"},"PeriodicalIF":1.2,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139920981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A floating meminductor emulator using modified differential voltage current conveyor transconductance amplifier and its application 使用改进型差分电压电流传输跨导放大器的浮动记忆电感仿真器及其应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-20 DOI: 10.1007/s10470-024-02257-0

Rupam Das, Shireesh Kumar Rai, Bhawna Aggarwal

{"title":"A floating meminductor emulator using modified differential voltage current conveyor transconductance amplifier and its application","authors":"Rupam Das, Shireesh Kumar Rai, Bhawna Aggarwal","doi":"10.1007/s10470-024-02257-0","DOIUrl":"10.1007/s10470-024-02257-0","url":null,"abstract":"<div><p>In this paper, a modified differential voltage current conveyor transconductance amplifier (MDVCCTA) based meminductor emulator has been proposed. The proposed meminductor is realized using one MDVCCTA, one resistor, and two grounded capacitors that leads to a very simple configuration. The emulator is working for a significant range of frequencies up to 80 MHz. The transient and non-volatility tests are found to be satisfactory. The corner and Monte Carlo analyses are done to verify the robustness of the proposed design. In addition, to assess the endurance of the recommended meminductor emulator, its workability with variations in supply voltage, temperature, and component values has been investigated. The pinched hysteresis loops that are fingerprints for the meminductor emulator are not deformed for any such variations. A comparison of suggested meminductor with those available in literature has been done based on several performance parameters. Two applications that demonstrate the viability of the suggested meminductor emulator have also been comprehended.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 3","pages":"475 - 496"},"PeriodicalIF":1.2,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139921000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC 为指数转换集成电路扩展信号动态范围并降低电源电压

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-19 DOI: 10.1007/s10470-023-02247-8

Naoya Nishiyama, Fumiya Matsui, Yuji Sano

{"title":"Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC","authors":"Naoya Nishiyama, Fumiya Matsui, Yuji Sano","doi":"10.1007/s10470-023-02247-8","DOIUrl":"10.1007/s10470-023-02247-8","url":null,"abstract":"<div><p>In order to compensate for the non-linearity of an electronic device, an exponentiation conversion circuit that can change the power exponent to any value has been proposed. The exponentiation conversion circuit multiplies the logarithmically converted input signal by a power exponent value to perform exponential conversion. As a result, we can obtain the power function characteristic of a power exponent value. This circuit is a small-scale circuit that utilizes the exponential characteristics of the MOSFET subthreshold region. In a conventional circuit, expansion of the signal dynamic range and reduction of the power supply voltage have been an issue. In this paper, it was confirmed by simulation that the signal dynamic range has expanded by optimizing the current density of MOSFETs. In addition, the linearity of the multiplying circuit was improved by feedback produced by the operational amplifier circuits. We proposed reducing its power supply voltage from 6.0 to 3.3 V by a new multiplying circuit that can eliminate the restriction of maximum voltage gain. Our circuit expands its signal dynamic range from 17.5 to 42.7 dB in condition of the power exponent value from 0.50 to 2.0.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 1","pages":"185 - 194"},"PeriodicalIF":1.2,"publicationDate":"2024-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02247-8.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139920953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental Investigation on the Side Mode Injection Locking of a Single-loop OEO under RF Signal Injection 射频信号注入下单环 OEO 侧模注入锁定的实验研究

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-18 DOI: 10.1007/s10470-024-02262-3

Jayjeet Sarkar, Abhijit Banerjee, Gefeson Mendes Pacheco, Nikhil Ranjan Das

引用次数: 0

Estimation of polarization diversity in CPW fed compact dual band dual sense antenna with horn slot structure: 5G and WLAN applications 角槽结构 CPW 馈电紧凑型双频双感天线的极化分集估算：5G 和 WLAN 应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-12 DOI: 10.1007/s10470-024-02250-7

Krishna Chennakesava Rao Madaka, Pachiyannan Muthusamy

引用次数: 0

A design approach for class-AB operational amplifier using the gm/ID methodology 使用 gm/ID 方法的 AB 类运算放大器设计方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-11 DOI: 10.1007/s10470-024-02252-5

Chen Chen, Jinxing Cheng, Hongyi Wang, Youyou Fan, Kaikai Wu, Tao Tao, Qingbo Wang, Ai Yu, Weiwei Wen, Youpeng Wu, Yue Zhang

{"title":"A design approach for class-AB operational amplifier using the gm/ID methodology","authors":"Chen Chen, Jinxing Cheng, Hongyi Wang, Youyou Fan, Kaikai Wu, Tao Tao, Qingbo Wang, Ai Yu, Weiwei Wen, Youpeng Wu, Yue Zhang","doi":"10.1007/s10470-024-02252-5","DOIUrl":"10.1007/s10470-024-02252-5","url":null,"abstract":"<div><p>The primary contribution of this paper is the extension of the g<sub>m</sub>/I<sub>D</sub> design methodology to two-stage operational amplifiers with class-AB output stages. First, the circuit is analyzed from the perspective of the g<sub>m</sub>/I<sub>D</sub> methodology, with a focus on its performance metrics and constraints. Second, to handle optimization targets and constraints automatically, the circuit sizing task is formulated as a single-objective optimization problem, and an optimizer is employed to obtain the temporary solution automatically. Benefiting from the g<sub>m</sub>/I<sub>D</sub> methodology, the gap between analytical equations and circuit simulation is highly reduced. Third, following the temporary solution, a guided fine-tuning method is introduced to further optimize the temporary solution. To demonstrate the effectiveness of this approach, we compared the equation-based method using the square-law model, two simulation-based methods and a commercial tool, Cadence ADE GXL, employing SMIC 55 nm and SMIC 180 nm CMOS technologies. The simulation results confirm the success of the proposed approach, showing that it not only reduces the gap between analytical equations and simulations, but also achieves the best performance metrics.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 1","pages":"43 - 55"},"PeriodicalIF":1.2,"publicationDate":"2024-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A bidirectional four-port DC–DC converter for grid connected and isolated loads of hybrid renewable energy system using hybrid approach 采用混合方法为混合可再生能源系统的并网和隔离负载设计双向四端口 DC-DC 转换器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-10 DOI: 10.1007/s10470-024-02251-6

N. Karthikeyan, G. D. Anbarasi Jebaselvi

{"title":"A bidirectional four-port DC–DC converter for grid connected and isolated loads of hybrid renewable energy system using hybrid approach","authors":"N. Karthikeyan, G. D. Anbarasi Jebaselvi","doi":"10.1007/s10470-024-02251-6","DOIUrl":"10.1007/s10470-024-02251-6","url":null,"abstract":"<div><p>Most four-port converters typically enable bidirectional power flow through the low-voltage side battery port, which is used to discharge to the high-voltage side DC-link and charge from energy sources. However, system-level power management is restricted by the DC-link’s absence of bidirectional power transmission. This manuscript proposes a hybrid approach utilizing a four-port DC–DC converter that can operate in isolation and in conjunction with the grid for hybrid renewable energy systems. Moreover, the converter architecture enables bi-directional power flow between all four ports, including the high-voltage DC-link, allowing for flexible and efficient power management. The Random Decision Forest and Jellyfish Search technology are combined to form the JS-RDF technique, which goes by that name. The primary goal of the proposed method is to reduce power losses, enhance system performance, and ensure stable voltage profiles. The JS is used for robust optimization, adapting the converter to various conditions, while the RDF employs machine learning for optimal control pulse prediction, enhancing overall efficiency. The JS-RDF approach is implemented on the MATLAB platform and is compared with existing approaches. Also, the JS-RDF method demonstrates great power compared to other existing approaches. From the result, the proposed technique shows outstanding performance with minimal switching losses at 0.19 W and conduction losses at 0.43 W, leading to the lowest total losses of 0.62 W. This emphasizes the superior efficiency of the proposed approach in optimizing power conversion, highlighting its potential to improve the overall performance of converter systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"467 - 487"},"PeriodicalIF":1.2,"publicationDate":"2024-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications 为深度学习应用设计面积速度高效的 Anurupyena Vedic 乘法器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-09 DOI: 10.1007/s10470-024-02255-2

C. M. Kalaiselvi, R. S. Sabeenian

{"title":"Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications","authors":"C. M. Kalaiselvi, R. S. Sabeenian","doi":"10.1007/s10470-024-02255-2","DOIUrl":"10.1007/s10470-024-02255-2","url":null,"abstract":"<div><p>Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the Field Programmable Gate Array (FPGA) implementation employing Very Large-Scale integration (VLSI) design approaches and parallel computing technology. Signal processing, machine learning, and reconfigurable computing research should be closely monitored as artificial intelligence develops. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in Arithmetic Logic Unit (ALU), Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a specific hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 3","pages":"521 - 533"},"PeriodicalIF":1.2,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139762004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electromagnetic coupling suppression of circularly polarized mimo antenna with novel loop parasitic for UWB communication 用于 UWB 通信的带有新型环形寄生器的圆极化 mimo 天线的电磁耦合抑制功能

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-08 DOI: 10.1007/s10470-024-02256-1

Muhammad Irshad Khan, Shaobin Liu, Saeed Ur Rahman, Muhammad Kabir Khan, Muhammad Sajjad, Abdul Basit, Jianliang Mao, Amil Daraz

{"title":"Electromagnetic coupling suppression of circularly polarized mimo antenna with novel loop parasitic for UWB communication","authors":"Muhammad Irshad Khan, Shaobin Liu, Saeed Ur Rahman, Muhammad Kabir Khan, Muhammad Sajjad, Abdul Basit, Jianliang Mao, Amil Daraz","doi":"10.1007/s10470-024-02256-1","DOIUrl":"10.1007/s10470-024-02256-1","url":null,"abstract":"<div><p>In this article, four elements circularly polarized trapezoid multiple inputs and multiple outputs (MIMO) antenna for UWB application is presented. The electrical dimension of presented four elements MIMO antenna in term of lambda (λ) is 0.44λ × 0.44λ × 0.012λ. The novel loop parasitic is used for the enhancement of isolation and impedance bandwidth. The reflection coefficient (Sij ∈ i = j) is less than − 10dB in range of 2.4 GHz and 13.5 GHz and isolation (Sij ∈ i ≠ j) is greater than 22dB in given range. The axial ratio bandwidth (ARBW) of presented trapezoid antenna is 3.6 GHz; less than − 3dB in the range of 6.7 and 10.3 GHz. The peak gain is 5.9dBi, diversity gain (DG) > 9.89dB and envelope correlation coefficient (ECC) < 0.022. Various other parameters such as radiation pattern, reflection coefficient, Isolation, multiplexing efficiency, ECC, DG and peak gain are discussed in detail for experimental validation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"118 3","pages":"577 - 588"},"PeriodicalIF":1.2,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139761748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An all-digital low-power, low-frequency GRO-based time to digital converter for biomedical applications 用于生物医学应用的基于 GRO 的全数字、低功耗、低频率时间数字转换器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-06 DOI: 10.1007/s10470-023-02246-9

Elnaz Zafarkhah, Maryam Zare, Nima S. Anzabi-Nezhad, Zahra Sohrabi

引用次数: 0