Analog Integrated Circuits and Signal Processing最新文献_第6页

Register design in positive feedback source coupled logic for mixed-signal applications 混合信号应用中正反馈源耦合逻辑的寄存器设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-15 DOI: 10.1007/s10470-025-02462-5

Shikha, Kirti Gupta, Neeta Pandey

{"title":"Register design in positive feedback source coupled logic for mixed-signal applications","authors":"Shikha, Kirti Gupta, Neeta Pandey","doi":"10.1007/s10470-025-02462-5","DOIUrl":"10.1007/s10470-025-02462-5","url":null,"abstract":"<div><p>This paper presents the design of positive feedback source coupled logic (PFSCL) registers for mixed-signal applications. The paper proposes static and dynamic PFSCL registers design. The two static register (SR-1, SR-2) designs involves feedback connection and employs PFSCL fundamental cells (SR-1) and PFSCL tri-state buffers (SR-2). The proposed dynamic PFSCL register (DR) avoids the feedback connection and simultaneously lowers the overall power consumption. The paper is extended for the design of clock skew insensitive register by addressing the clock overlap issue. All the proposed PFSCL registers are simulated in LTspice using PTM 90 nm CMOS technology parameters and the layouts are drawn in the microwind tool. The performance of the proposed registers has been compared with conventional CMOS registers. It is observed that proposed DR achieves maximum improvements across all key performance parameters. A maximum reduction of 94.45%, 77.6%, 86.25%, 85%, 78.5% in CLK to Q, D to Q propagation delay, power, setup and hold time respectively at the cost of 48% increased. Also, the Monte Carlo and corner simulation results reveals that proposed dynamic register design exhibits the lowest variations in both CLK-Q and D-Q propagation delay. Finally, a serial in serial out shift register implementation is included as a design example.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145165385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel fault-tolerant T flip-flop in ternary QCA 一种新颖的三元QCA容错T触发器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-10 DOI: 10.1007/s10470-025-02456-3

Mina Ahmadi Marjeghal, Reza Sabbaghi-Nadooshan, Ahmadali Ashrafian

{"title":"A novel fault-tolerant T flip-flop in ternary QCA","authors":"Mina Ahmadi Marjeghal, Reza Sabbaghi-Nadooshan, Ahmadali Ashrafian","doi":"10.1007/s10470-025-02456-3","DOIUrl":"10.1007/s10470-025-02456-3","url":null,"abstract":"<div><p>While complementary metal-oxide-semiconductor (CMOS) technology has been widely adopted, challenges such as increasing leakage current and physical limitations have driven researchers toward emerging quantum-dot cellular automata (QCA) technology. Notable features of QCA include extremely high density, low power consumption, and high switching speed. Moreover, the design of multi-valued logic systems, as an alternative to standard binary systems, has gained significant interest among researchers. Designing digital circuits in a multi-valued system offers numerous advantages over traditional binary methods. This paper presents novel structures for T flip-flops in multi-valued QCA technology. The impact of single-cell omission and extra-cell deposition defects on the proposed circuits is investigated. Initially, a ternary T flip-flop is proposed based on 56 cells with a delay of 1.25 clock cycles and an area of 0.012 µm<sup>2</sup>. Subsequently, a novel ternary T flip-flop is proposed by employing a new XOR design in the structure with only 33 cells, an area of 0.007 µm<sup>2</sup>, and a delay of 1 clock cycle, exhibiting superior properties compared to previous designs. Additionally, in comparison with the most similar structure in the literature, our method requires 29% fewer cells. The present research evaluates the proposed ternary T flip-flop, considering the range of inherent defects in QCA systems. Among the existing defects, single-cell omission and extra-cell deposition defects of the proposed circuits are examined. Fault tolerance values higher than 70% for the proposed circuits indicate greater tolerance to the mentioned defects in these designs compared to their counterparts.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145163438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel low-voltage low-power very high gain fully differential CMOS class AB pure current mode current operational amplifier 一种新型的低电压、低功率、高增益全差分CMOS AB类纯电流模电流运算放大器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-08 DOI: 10.1007/s10470-025-02431-y

Behnam Abdoli, Seyed Javad Azhari

{"title":"A novel low-voltage low-power very high gain fully differential CMOS class AB pure current mode current operational amplifier","authors":"Behnam Abdoli, Seyed Javad Azhari","doi":"10.1007/s10470-025-02431-y","DOIUrl":"10.1007/s10470-025-02431-y","url":null,"abstract":"<div><p>In this paper, a novel fully differential (FD) class AB pure current mode current operational amplifier (COA) is designed and presented. In order to attain highly desired features such as high current gain, very high current drive ratio (I<sub>outmax</sub>/I<sub>bias</sub>) low power consumption, high linearity and good frequency performance, a powerful feedback-based technique is included in the gain stage of the amplifier. Also using the fully differential and class AB structure, implementing FG-MOS transistors in the current output stage along with avoiding high impedance nodes leads to a greatly desired performance in terms of CMRR, PSRR, output current drive capability and low voltage - low power operation which makes the proposed COA suitable for mixed mode and accurate applications. The detailed operation of the proposed COA is far enough discussed, and its small-signal equations are provided. The outstanding properties of the amplifier are verified by Cadence simulations using TSMC 65 nm CMOS technology parameters. To study the robustness of the COA against technology and voltage non-idealities and get results as reliable and practical as measurement, pre-layout and post-layout simulations both plus Monte Carlo analysis are also performed. Under ± 0.9 V supply voltage and 68 µA output bias current, the proposed COA can deliver the output current of ± 1040 mA with THD of − 44 dB, output impedance of 1.88 MΩ, drive ratio (I<sub>outmax</sub>/I<sub>bias</sub>) of 15,300, 108 dB gain, -3dB bandwidth of 14.8 MHz and low consumed power of 282 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results are as 74 µA, ± 920 mA, − 42 dB, 1.64 MΩ, 12,450, 102 dB, 12.2 MHz and 298 µw for the same arrange of parameters in pre-layout. These results which are as close as possible to the measuring ones prove the remarkable performance of the proposed COA and its superiority over yet artworks.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145163358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient flash ADC architecture based on MoS({}_2) transistors 基于MoS ({}_2)晶体管的高能效闪存ADC架构

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-07 DOI: 10.1007/s10470-025-02457-2

Ashkan Horri

{"title":"Energy-Efficient flash ADC architecture based on MoS({}_2) transistors","authors":"Ashkan Horri","doi":"10.1007/s10470-025-02457-2","DOIUrl":"10.1007/s10470-025-02457-2","url":null,"abstract":"<div><p>In this paper, we utilize the advantages of Molybdenum Disulfide (MoS<span>({}_2)</span>) transistors to design a Flash analog-to-digital converter (ADC) that achieves a reduced active area and dynamic power. MoS<span>({}_2)</span> field-effect transistors (FETs) are a class of emerging devices based on two-dimensional (2D) materials, offering high ON/OFF current ratios, excellent electrostatic control, and scalability, making them suitable for next-generation low-power electronics. To eliminate static power dissipation, the proposed ADC incorporates the threshold inverter quantization (TIQ) technique. A SPICE-compatible charge-based model for MoS<span>({}_2)</span> transistor, published in the literature, is used to simulate the proposed ADC. Due to their high ON/OFF current ratio and nanoscale geometry, MoS<span>({}_2)</span> FETs enable significant reductions in ADC active area and dynamic power relative to traditional device technologies. Simulation results reveal that the differential nonlinearity (DNL) ranges of [-0.18, 0.12]LSB , and the integral nonlinearity (INL) ranges of [-0.32, 0.24]LSB, both satisfying the requirements for 4-bit resolution at a 2 V operating voltage. In addition, the low ADC active area of 3050 <span>(mu m^2)</span> rendering it well-suited for implementation in very large-scale integration (VLSI) circuits. Variations in process, temperature, and supply voltage affect the proposed method, and their influence on ADC performance is analyzed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145162907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design space exploration of array-based approximate squaring unit for error-tolerant computing 基于阵列的容错近似平方单元的设计空间探索

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-07 DOI: 10.1007/s10470-025-02459-0

Mahmoud Masadeh, Alain Aoun, Sofiène Tahar

{"title":"Design space exploration of array-based approximate squaring unit for error-tolerant computing","authors":"Mahmoud Masadeh, Alain Aoun, Sofiène Tahar","doi":"10.1007/s10470-025-02459-0","DOIUrl":"10.1007/s10470-025-02459-0","url":null,"abstract":"<div><p>The squaring circuit is an essential computational element of Digital Signal Processing (DSP) designs that directly affect their area, speed and power consumption. Various DSP applications have noisy and redundant input data. Thus, implementing an approximate squaring function will cause minor quality degradation with a significant reduction in hardware costs. In this paper, we perform a design space exploration (DSE) of an energy-efficient array-based approximate squaring function. The proposed designs are 8-bit unsigned and signed, with reduced area, power, and delay. Towards this goal, we introduced four energy-efficient approximate <b>I</b>ne<b>x</b>act <b>F</b>ull <b>A</b>dders (IxFAs) that are suitable for the squaring function. The proposed IxFAs and 14 existing approximate full adders (FAs) are used to perform a DSE of approximate squaring units with various configurations based on the type of the used approximate FAs and the level of approximation. The IxFA-based squaring designs have a reduced area, power, and delay compared to the exact array squarer. Moreover, compared to the state-of-the-art, the proposed designs have less area, energy, and power consumption while offering competitive quality. They were further tested for DSP applications and showed high-quality results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145163078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fuel cell EV for smart charging with stochastic network planning using hybrid EOO-SNN approach 基于混合EOO-SNN方法的燃料电池电动汽车智能充电随机网络规划

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-07 DOI: 10.1007/s10470-025-02429-6

S. Dhas Bensam, K. S. Kavitha Kumari, Amarendra Alluri, P. Rajesh

{"title":"Fuel cell EV for smart charging with stochastic network planning using hybrid EOO-SNN approach","authors":"S. Dhas Bensam, K. S. Kavitha Kumari, Amarendra Alluri, P. Rajesh","doi":"10.1007/s10470-025-02429-6","DOIUrl":"10.1007/s10470-025-02429-6","url":null,"abstract":"<div><p>This paper proposes a hybrid method for network expansion planning for electric vehicle charging stations. The hybrid method is the combination of Eurasian Oystercatcher optimizer (EOO) and spiking neural network (SNN) approach and is usually referred as EOO-SNN approach. The major purpose of the work is to extend the optimal charging strategy for EVs, which includes the allocation of charging resources to decrease the charging costs, increase the charging efficiency, and decrease the impact on the power grid. The EOO is used to optimize various aspects, such as charging time, charging station placement, and network expansion planning. The ideal solution is predicted using the SNN. The approach also combined with smart grid technologies, such as demand response mechanisms and fuel cell integration with battery energy storage system, to optimize the energy system and ensure efficient and sustainable EV charging. The proposed method supports scalability/adaptability in EV charging systems, effective charging strategy formulation, and worldwide optimisation of charging infrastructure growth. The proposed method’s effectiveness is then evaluated on the MATLAB platform and compared to other existing approaches. The efficacy of the proposed system is high as 45%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145162900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving routing and energy consumption in wireless sensor networks by data fusion-based clustering 基于数据融合的聚类改进无线传感器网络的路由和能耗

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-07-07 DOI: 10.1007/s10470-025-02454-5

Mojdeh. Mahdavi, Rezvan. Khandani

{"title":"Improving routing and energy consumption in wireless sensor networks by data fusion-based clustering","authors":"Mojdeh. Mahdavi, Rezvan. Khandani","doi":"10.1007/s10470-025-02454-5","DOIUrl":"10.1007/s10470-025-02454-5","url":null,"abstract":"<div><p>The technique of clustering and using cluster heads that are connected to a sink node has been a very effective approach to reducing energy consumption and increasing the service life of sensor networks. In the present study, a density-based clustering technique is used, and then, three parameters, including residual energy, link quality, and data delivery rate, are considered as three evidence sources to determine the scores of sensor nodes and cluster heads. These three parameters are used for data fusion at signal and decision levels based on the Dempster-Shafer evidence theory so that the scores of the sensor nodes are determined. After fusion, cluster heads are selected. Moreover, appropriate sensor nodes are chosen from the neighbors for intra-cluster routing based on their scores. As an advantage of the method proposed in this study, the number of clusters is not selected by an external component. Moreover, evidence-based data fusion allows aggregating data from different heterogeneous sources. A comparison of the proposed scheme with the Fuzzy logic-based unequal clustering (FBUC), energy-aware unequal clustering algorithm (EAUCF), and low energy adaptive clustering hierarchy (LEACH) methods shows, respectively, 0.04, 0.14, and 0.18 joules improvement in residual energy, and 1.9%, 7.2%, and 10.6% improvement in network lifetime.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145163031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient static random access memory cell using ferroelectric surrounding gate tunnel FETs based on negative capacitance 基于负电容的铁电环栅隧道场效应管高效静态随机存取存储单元

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-30 DOI: 10.1007/s10470-025-02452-7

J. Agnes Sorna Niruba, R. Manjith, S. Anusha, S. P. Valan Arasu, S. Pousia

引用次数: 0

Low-noise 10-bit SAR ADC with auto-zero comparator using fully differential difference amplifier 低噪声10位SAR ADC与自动归零比较器采用全差分差分放大器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-28 DOI: 10.1007/s10470-025-02442-9

Hyeoktae Son, Mookyoung Yoo, Sanggyun Kang, Byeongkwan Jin, Kyounghwan Kim, Jihyang Wi, Gibae Nam, Seungmin Ahn, Hyoungho Ko

{"title":"Low-noise 10-bit SAR ADC with auto-zero comparator using fully differential difference amplifier","authors":"Hyeoktae Son, Mookyoung Yoo, Sanggyun Kang, Byeongkwan Jin, Kyounghwan Kim, Jihyang Wi, Gibae Nam, Seungmin Ahn, Hyoungho Ko","doi":"10.1007/s10470-025-02442-9","DOIUrl":"10.1007/s10470-025-02442-9","url":null,"abstract":"<div><p>This paper presents a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an RC hybrid digital-to-analog converter (DAC) and auto-zero (AZ) comparator. To reduce the circuit area and to achieve the high linearity, we propose the use of an RC hybrid DAC inside an SAR ADC. The resistor array is arranged in the least significant bit (LSB) ladder, and the capacitor array is arranged in the most significant bit (MSB) ladder. Placing RDAC instead of CDAC in a 4-bit LSB ladder can reduce the total capacitance area. To reduce the offset and low-frequency noise, various AZ techniques are widely adopted for the comparator, however, the offset storage capacitor is placed in serial to the signal path, the signal charges in CDAC or offset storage capacitors can be distorted. In this design, an autozeroed pre-amplifier is designed using a fully differential difference amplifier (FDDA) and feedback offset sampling to prevent the charge distortion during the AZ operation. The proposed SAR ADC is implemented using a standard 0.18 μm CMOS process. The simulated and measured effective number of bits (ENOB) of this SAR ADC are 9.98-bit and 9.56-bit, respectively. The linearity performance of the proposed SAR ADC was measured with DNL having a maximum of 0.28 LSB and a minimum of -0.18 LSB, while INL had a maximum of 0.5 LSB and a minimum of -0.19 LSB. And the proposed SAR ADC’s total current consumption is 41.4 µA with a 1.8 V power supply.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145170160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low cost all-dielectric water based resonant absorber 一种低成本全介电水基谐振吸收器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-24 DOI: 10.1007/s10470-025-02449-2

Avinash, Nisha Gupta

{"title":"A low cost all-dielectric water based resonant absorber","authors":"Avinash, Nisha Gupta","doi":"10.1007/s10470-025-02449-2","DOIUrl":"10.1007/s10470-025-02449-2","url":null,"abstract":"<div><p>A promising technique for lowering interference is to absorb electromagnetic (EM) energy and partially transform it into heat. EM absorbers are able to achieve this phenomenon. Most electromagnetic absorbers are based on metamaterials and can absorb a broad range of frequencies. However, for specific applications, a resonant absorber is needed. In this paper, a purely water based, frequency selective surface (FSS) resonant absorber is proposed. The structural design of the proposed absorber consists of an array of square shaped cavities made of acrylic sheet for holding the water. The ground plane made of conducting foil/tape is placed at the bottom. The dimension of the unit cell is 0.45<span>(lambda _l)</span><span>(times)</span> 0.45<span>(lambda _l)</span><span>(times)</span> 0.05<span>(lambda _l)</span> where, <span>(lambda _l)</span> is the wavelength at the lowest operating frequency. The EM absorber shows more than 99.99<span>(%)</span> absorption and 17.14<span>(%)</span> fractional bandwidth (FBW) at resonating frequency of 3.5 GHz at different polarization angles, make it suitable for WiMax/CBRS/n78 5G band application. The performance of the proposed absorber is analyzed both through simulation and measurement. A comparison between the simulated and the measured results shows good agreement. </p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145169386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0