Design space exploration of array-based approximate squaring unit for error-tolerant computing

Abstract

The squaring circuit is an essential computational element of Digital Signal Processing (DSP) designs that directly affect their area, speed and power consumption. Various DSP applications have noisy and redundant input data. Thus, implementing an approximate squaring function will cause minor quality degradation with a significant reduction in hardware costs. In this paper, we perform a design space exploration (DSE) of an energy-efficient array-based approximate squaring function. The proposed designs are 8-bit unsigned and signed, with reduced area, power, and delay. Towards this goal, we introduced four energy-efficient approximate Inexact Full Adders (IxFAs) that are suitable for the squaring function. The proposed IxFAs and 14 existing approximate full adders (FAs) are used to perform a DSE of approximate squaring units with various configurations based on the type of the used approximate FAs and the level of approximation. The IxFA-based squaring designs have a reduced area, power, and delay compared to the exact array squarer. Moreover, compared to the state-of-the-art, the proposed designs have less area, energy, and power consumption while offering competitive quality. They were further tested for DSP applications and showed high-quality results.