Efficient static random access memory cell using ferroelectric surrounding gate tunnel FETs based on negative capacitance

Abstract

In this proposal, the modified ferroelectrics surrounding gate tunnel FETs, gate stack engineering, and various gate metals are analyzed using analytical models. Using stacked oxide SiO2/high-k and dual materials (DM), surround gate (SG) tunnel FETs (TFETs) were created to combine the scaling benefits of gate stack engineering with the high efficiency of dual material engineering. Kane's equation calculates the band-to-band (BTBT) tunneling rate and the drain current. For the DMSG-TFET, a two-dimensional (2D) mathematical model of the electric field and surface potential was created. The Poisson's equations are solved with corresponding system boundary conditions in two dimensions. It has also been investigated whether changing device parameters affects its output. A 3-D computer simulator tool called ANSYS was used to verify the mathematical results of the TFET, which is implemented using an inverter circuit.