Analog Integrated Circuits and Signal Processing最新文献_第7页

A comprehensive review of low-power design techniques in VLSI systems: From device physics to algorithmic optimization VLSI系统中低功耗设计技术的全面回顾：从器件物理到算法优化

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-07-04 DOI: 10.1007/s10470-026-02612-3

Marina Papadopoulou, Michael Dossis, Evangelos Karvounis

引用次数: 0

Low-Complexity VLSI architecture for OTFS transceiver under Fully Parallel and Pipelined Hardware Architecture using Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks 基于Cosine-Krawtchouk点离散激活、chebichef可操纵Lyrebird卷积变换网络的全并行和管道硬件架构下OTFS收发器的低复杂度VLSI架构

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-07-02 DOI: 10.1007/s10470-026-02605-2

Balamurugan Rajangam, Maheswari Murali

{"title":"Low-Complexity VLSI architecture for OTFS transceiver under Fully Parallel and Pipelined Hardware Architecture using Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks","authors":"Balamurugan Rajangam, Maheswari Murali","doi":"10.1007/s10470-026-02605-2","DOIUrl":"10.1007/s10470-026-02605-2","url":null,"abstract":"<div><p>Orthogonal Time Frequency Space (OTFS) modulation has gained attention as a reliable wireless communication technique, especially under high-mobility and time-varying channel conditions. However, conventional OTFS transceiver designs face significant challenges in terms of hardware complexity, low throughput, and inefficient execution in multi-path fading environments. To overcome these limitations, this paper introduces an OTFS Transceiver with Low-Complexity VLSI Architecture in A Fully Parallel and Pipelined Hardware Architecture in Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks (CosKPWD-ATSL-CTN). The suggested CosKPWD-ATSL-CTN framework combines Point-wise Activations and Steerable Convolutional Networks (PWASCN) with Discrete Cosine-Krawtchouk-Tchebichef Transform (DCKTKT) to provide a better level of representation of the signal in the delay-Doppler context. It uses a depth-pipelined and fully parallel hardware design to run important operations like FFT/IFFT and modulation, and uses the Lyrebird Optimization Algorithm (LOA) to allocate resources optimally. The implementation results on the platform based on 7vx485tfg1157-1 FPGA indicate that the design can achieve a peak throughput of 217.83 Tbps, with only 61,842 LUTs and 19,865 flip-flops, with the highest possible clock frequency being 168.37 MHz. This architecture achieves superior performance over conventional OTFS designs by reducing latency, minimizing logic complexity, and delivering high-speed, energy-efficient signal processing under dynamic multi-path fading conditions.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148380265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A scalable asynchronous Mod-10 BCD counter realization using delay flip-flops: A quantum-dot cellular automata approach 使用延迟触发器的可扩展异步Mod-10 BCD计数器实现：量子点元胞自动机方法

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-06-30 DOI: 10.1007/s10470-026-02608-z

Rohit Kumar Shaw, Angshuman Khan, Sudip Halder

{"title":"A scalable asynchronous Mod-10 BCD counter realization using delay flip-flops: A quantum-dot cellular automata approach","authors":"Rohit Kumar Shaw, Angshuman Khan, Sudip Halder","doi":"10.1007/s10470-026-02608-z","DOIUrl":"10.1007/s10470-026-02608-z","url":null,"abstract":"<div><p>Quantum-dot Cellular Automata (QCA) offers a paradigm shift from conventional semiconductor technologies, leveraging quantum-mechanical tunneling and Coulomb interaction for ultra-low-power nanocomputing. This paper addresses the critical gap in QCA-based sequential circuits, particularly the absence of application-specific decimal systems, by proposing a novel D flip-flop and the first asynchronous Mod-10 BCD counter. The optimized D flip-flop utilizes only 21 cells, achieves a latency of 0.75 clock cycles, 33.3% faster than conventional designs, and exhibits the lowest reported energy dissipation. This robust D-FF enables a scalable BCD counter with integrated reset logic, designed using multilayer crossovers to ensure signal integrity and full input-output accessibility. The counter consumes 52.9% less energy than prior binary counters. It demonstrates exceptional thermal stability across the temperature range of 1–10 K. These improvements in latency, energy efficiency, and functional completeness establish a new benchmark for QCA sequential design, paving the way for practical decimal applications, such as digital clocks and calculators, while providing a reliable foundation for future QCA-based nanoarchitectures.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148380914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A reconfigurable analog logic architecture based on clar cells for combinational and arithmetic systems 一种用于组合和算术系统的基于清晰单元的可重构模拟逻辑结构

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-06-27 DOI: 10.1007/s10470-026-02607-0

J. Gonzalez-Contreras, R. E. Lozoya-Ponce, L. J. Ontanon-Garcia

{"title":"A reconfigurable analog logic architecture based on clar cells for combinational and arithmetic systems","authors":"J. Gonzalez-Contreras, R. E. Lozoya-Ponce, L. J. Ontanon-Garcia","doi":"10.1007/s10470-026-02607-0","DOIUrl":"10.1007/s10470-026-02607-0","url":null,"abstract":"<div><p>This work presents a reconfigurable analog logic architecture based on Cell Logic Analog Reconfigurable (CLAR) for the implementation of combinational logic and arithmetic functions. Each CLAR cell performs weighted summation and threshold-based operations using standard analog components, enabling the realization of Boolean logic functions through parameter reconfiguration. A systematic mapping between Boolean functions and analog weighted-sum structures is established, allowing the construction of higher-level building blocks such as adders, subtractors, comparators, and multiplexers. These elements are integrated into a one-bit analog arithmetic–logic unit (ALU), which is validated through simulation and proof-of-concept experimental observations. In addition to functional validation, the work includes an analysis of key performance aspects such as propagation delay, power consumption, and scalability. A comparison with digital, Field-Programmable Analog Arrays based, and emerging analog approaches highlights the trade-offs between flexibility, hardware efficiency, and implementation constraints. Although the proposed architecture is not intended to compete with highly integrated solutions in terms of area or power consumption, it provides a modular, transparent, and accessible platform for rapid prototyping, experimental research, and education in analog computation. The results demonstrate that CLAR-based systems constitute a viable and extensible approach for reconfigurable analog logic and arithmetic design, complementing conventional digital implementations.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"128 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148323863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In depth study of junctionless tunnel field effect transistors for mixed signal applications 深入研究了用于混合信号的无结隧道场效应晶体管

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-06-22 DOI: 10.1007/s10470-026-02599-x

Tamilarasi Raja, A. S. Augustine Fletcher

{"title":"In depth study of junctionless tunnel field effect transistors for mixed signal applications","authors":"Tamilarasi Raja, A. S. Augustine Fletcher","doi":"10.1007/s10470-026-02599-x","DOIUrl":"10.1007/s10470-026-02599-x","url":null,"abstract":"<div><p>The rapid advancement of modern electronics demands innovative solutions for low-power, high-performance semiconductor devices. Junctionless Tunnel Field-Effect Transistors (JL-TFETs) have emerged as a promising alternative to traditional MOSFETs, offering simplified fabrication, elimination of PN junctions, and enhanced reliability through reduced ambipolar effects and suppression of random doping fluctuations. By combining the strengths of JL-FETs and TFETs, JL-TFETs provide superior electrical performance, including higher on-state current (<span>(I_{ON})</span>), less SS (subthreshold swing), minimal leakage current (<span>(I_{OFF})</span>) and an exceptional <span>(I_{ON}/I_{OFF})</span> ratio. This review delves into the comparative analysis of homogeneous and heterogeneous JL-TFET structures, emphasizing their DC and AC performance metrics. Heterogeneous JL-TFETs, leveraging low-bandgap materials such as <span>({Si_XGe_{X-1}})</span> and AlGaAs at critical regions, exhibit enhanced tunneling performance, lower power consumption and improved frequency performance. Advanced fabrication techniques like silicon-on-nothing (SON) technology and the integration of high-k dielectrics are explored for further optimization. Dual-material gate structures and material-engineered designs are analyzed to reveal their role in achieving superior performance and enhanced device scalability. The study presents a detailed evaluation of critical parameters, including SS, <span>(I_{ON})</span>, <span>(I_{OFF})</span>, tunneling rates, cut-off frequency (<span>(f_t)</span>), maximum oscillation frequency (<span>(f_{max})</span>), gain bandwidth product (GBW), output conductance <span>(g_d)</span> and transconductance (<span>(g_m)</span>). By consolidating recent advancements, this review highlights the transformative potential of JL-TFETs for next-generation high-speed analog and RF applications, offering comprehensive foundation for future research and development in the field.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148323487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A four MOSFETs based grounded memristor emulator 基于四个mosfet的接地忆阻器仿真器

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-06-19 DOI: 10.1007/s10470-026-02602-5

Navnit Kumar, Neeta Pandey, Manjeet Kumar, Manish Kumar

{"title":"A four MOSFETs based grounded memristor emulator","authors":"Navnit Kumar, Neeta Pandey, Manjeet Kumar, Manish Kumar","doi":"10.1007/s10470-026-02602-5","DOIUrl":"10.1007/s10470-026-02602-5","url":null,"abstract":"<div><p>A novel off- the-shelf Grounded Memristor Emulator (GME) based on four MOS transistors is reported in this brief. It consists of one PMOS and three NMOS transistors. The proposed emulator utilizes MOS capacitors instead of passive capacitors. Consequently, it can be stated that the circuit is exceedingly easy and appropriate for VLSI implementation. The fingerprint of memristor is represented by a pinched hysteresis loop thoroughly analyzed by SPICE simulator utilizing 180-nm CMOS technology with a bias voltage of ± 0.45 V. The designed circuit demonstrates non-linear behavior effectively up to 400 <span>(:text{M}text{H}text{z})</span>. The suggested circuit consumes 9.03 <span>(:{upmu:}text{W})</span> of power. Moreover, area of the layout of the proposed circuit is 627.41 <span>(:{{upmu:}text{m}}^{2}.)</span> Further, the analysis of non-ideal conditions and post-layout simulations have been incorporated to illustrate the impact of parasitic components on the designed memristor emulator. In addition, the feasible practical applications are examined via the implementation of relaxation oscillator, which is suitable for biomedical and neuromorphic applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 3","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148281769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Correction to: Optimizing deep convolutional neural network with an IP-bounded binary optimization and optimal extreme learning machine for pulse repetition interval modulation recognition 修正：用ip有界二进制优化和最优极限学习机优化深度卷积神经网络，用于脉冲重复间隔调制识别

IF 1.8 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-06-16 DOI: 10.1007/s10470-026-02601-6

Xiaoxia Zheng, Seyed Majid Hasani Azhdari, Mohammad Khishe, Azar Mahmoodzadeh, Hamed Agahi

引用次数: 0

Energy-efficient and fault-tolerant demultiplexer design in QCA nanotechnology QCA纳米技术中节能和容错的多路复用器设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-25 DOI: 10.1007/s10470-026-02600-7

Vijay Kumar Sharma

{"title":"Energy-efficient and fault-tolerant demultiplexer design in QCA nanotechnology","authors":"Vijay Kumar Sharma","doi":"10.1007/s10470-026-02600-7","DOIUrl":"10.1007/s10470-026-02600-7","url":null,"abstract":"<div><p>The dimension of traditional transistor is scaled down in the nanoscale regime, which causes size scalability and secondary issues restrictions for the complementary metal oxide semiconductor (CMOS) technology. To address these challenges in the nanoscale regime, there is a need for a prospective CMOS successor. Quantum-dot cellular automata (QCA) is a promising nanotechnology for designing circuits in the nanoscale regime. QCA emerges as the circuit design technology that can replace transistor technology completely in the nanoscale regime. A demultiplexer is an important operation in a communication system. Hence, a single-layered elementary 1:2 demultiplexer is proposed in QCA technology using 18 QCA cells and a single clock phase. The proposed 1:2 demultiplexer is tested for a single cell missing and addition faults. To check the effectiveness of the proposed 1:2 demultiplexer for higher order circuit, a single-layered 1:4 demultiplexer is also developed using the proposed 1:2 demultiplexer. The proposed designs are compared with the existing works to evaluate the performance. The proposed 1:2 and 1:4 demultiplexers reduce cells count by 5.26% and 4.17%, respectively, as compared to the best-reported work. The energy dissipation is also computed to confirm the circuits’ energy-efficient behaviour using QCA Designer-E and QCA Pro tools. The proposed 1:2 and 1:4 demultiplexers minimize the energy dissipation by 12.27% and 8.67%, respectively, at 1.5 kink energy level as compared to the available work.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148009869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA enabled decoder design for multi-kernal polar codes in 5G communication 5G通信中多内核极化码的FPGA解码器设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-21 DOI: 10.1007/s10470-026-02594-2

Moulana, A. Niranjil Kumar

{"title":"FPGA enabled decoder design for multi-kernal polar codes in 5G communication","authors":"Moulana, A. Niranjil Kumar","doi":"10.1007/s10470-026-02594-2","DOIUrl":"10.1007/s10470-026-02594-2","url":null,"abstract":"<div><p>Polar codes have been the focus of increasing attention over the past ten years, and they have been selected as the control channel coding scheme in fifth-generation (5G) wireless communication systems. Because of its capacity-achieving property, multi-kernel (MK) polar codes are recommended as one of the most attractive channel codes to obtain more flexible block lengths. Polar codes have improved significantly over the last 10 years in terms of power, decoding delay, complexity, and error-correction performance for finite-length codes under Field-Programmable Gate Array (FPGA) enabled belief propagation (BP) and successive cancellation (SC) algorithms. Nevertheless, the FPGA-enabled successive cancellation list (SCL) decoder is very large and has a long decoding latency. Therefore, based on the BPL decoding algorithm, a Belief Propagation List (BPL) decoder for MK polar codes is proposed in this research. Decoding makes use of multiple permuted factor graphs (PFGs) to further explore possible codewords. Finally, using Xilinx Verilog coding, the hardware architectures of the BPL decoder are executed in an FPGA. The result analysis shows that the proposed BPL decoder architecture accomplishes 250.64 MHz maximum frequency, 3.02Gbps throughput, and consumes 0.922 ns decoding delay for 1024-bit code length on the Virtex-7 FPGA platform.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148009289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low power and highly stable 10 T SRAM cell design using stacked and MTCMOS techniques 采用堆叠和MTCMOS技术的低功耗和高稳定的10 T SRAM单元设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-05-21 DOI: 10.1007/s10470-026-02598-y

Md. Mozahidul Islam, Fariha Zaman, Md. Tawfiq Amin

{"title":"Low power and highly stable 10 T SRAM cell design using stacked and MTCMOS techniques","authors":"Md. Mozahidul Islam, Fariha Zaman, Md. Tawfiq Amin","doi":"10.1007/s10470-026-02598-y","DOIUrl":"10.1007/s10470-026-02598-y","url":null,"abstract":"<div><p>Power reduction and stability enhancement remain critical challenges in advanced SRAM design. This paper presents a comparative study of conventional, stacked, and Multi-Threshold CMOS (MTCMOS) 10T SRAM cells implemented in 90 nm CMOS technology. The stacked configuration leverages the stack effect to suppress subthreshold leakage and mitigate drain-induced barrier lowering, achieving ultra-low standby power with moderate read/write delays. In contrast, the MTCMOS architecture employs low and high-threshold transistors with sleep-based power gating, reducing leakage while maintaining high-speed operation. Simulation results show that the stacked 10T SRAM achieves read static noise margin (RSNM), hold static noise margin (HSNM), and write static noise margin (WSNM) values of 470 mV, 570 mV, and 230 mV, respectively, with read/write power consumption of 0.03 <span>(upmu)</span>W and 0.77 <span>(upmu)</span>W, respectively. The MTCMOS-based design demonstrates superior stability (RSNM: 616 mV, HSNM: 660 mV, WSNM: 1 V) and faster access times (read: 50 ps, write: 70 ps) at higher dynamic power. Total power consumption is 78.7 <span>(upmu)</span>W for stacked SRAM and 13.8 <span>(upmu)</span>W for MTCMOS SRAM. N-curve analysis, process corner evaluation, Post Layout with DRC/LVS checked, and Monte Carlo simulations confirm robust operation under variability. Overall, MTCMOS SRAM is optimal for ultra-low-power applications and better suited for high-speed, high-stability systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148009281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0