Analog Integrated Circuits and Signal Processing最新文献_第7页

Design of multi-element QAM backscatter modulated tag based on backscatter communication 基于后向散射通信的多元QAM后向散射调制标签设计

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-24 DOI: 10.1007/s10470-025-02455-4

Jumin Zhao, Jiapeng Shi, Deng-ao Li, Yajun Li, Jie Cheng

{"title":"Design of multi-element QAM backscatter modulated tag based on backscatter communication","authors":"Jumin Zhao, Jiapeng Shi, Deng-ao Li, Yajun Li, Jie Cheng","doi":"10.1007/s10470-025-02455-4","DOIUrl":"10.1007/s10470-025-02455-4","url":null,"abstract":"<div><p>The low throughput of backscatter systems impedes Internet of Things (IoT) deployment. Although coding optimization and rate adaptation schemes exist for low-order modulation, inherent modulation constraints still limit large-data transmission in complex channels. In addition, the design scheme of fixed high-order modulation tags has poor environmental robustness. In order to solve the above problems, this paper designs a low-power multiple quadrature amplitude modulation(MQAM) modulated tag with an operating frequency of 920 MHz. The modulation space is significantly enlarged by optimizing the selection of reflection coefficient, designing series impedance branch and double <span>(Pi)</span><span>(mu)</span>s) is realized at the tag end based on LMV331 comparator. The experimental results show that the tag can achieve an average throughput of 15.36 Mbit/s at a communication distance of 1.8 m and a power consumption of 0.57 mW, which is a significant increase in throughput compared with the traditional low-order tags, and also has a significant advantage over the fixed high-order modulation tags in terms of communication distance and power consumption.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145168248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical analytical approach for hydrogen sensing of Al0.43Ga0.57As/La2O3: Pt-based CSDG MOSFET Al0.43Ga0.57As/La2O3: pt基CSDG MOSFET氢传感的电分析方法

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-24 DOI: 10.1007/s10470-025-02447-4

Naveenbalaji Gowthaman, Viranjay M. Srivastava

{"title":"Electrical analytical approach for hydrogen sensing of Al0.43Ga0.57As/La2O3: Pt-based CSDG MOSFET","authors":"Naveenbalaji Gowthaman, Viranjay M. Srivastava","doi":"10.1007/s10470-025-02447-4","DOIUrl":"10.1007/s10470-025-02447-4","url":null,"abstract":"<div><p>Nanotechnology has enabled novel sensing approaches with significant potential for environmental monitoring and technological advancements. This research explores the integration of nano-materials in hydrogen sensing, leveraging advanced fabrication techniques to analyze the electrical characteristics of Al<sub>0.43</sub>Ga<sub>0.57</sub>As Cylindrical Surrounding Double-Gate (CSDG) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The incorporation of nano-materials enhances sensitivity and selectivity, enabling hydrogen gas detection at extremely low concentrations. The sensor maintains a robust response even at elevated temperatures, such as 393 K. The results indicate peak frequencies of 57.36 GHz at 1.105 mA, 56.95 GHz at 1.161 mA, and 56.54 GHz at 1.222 mA for InGaAs (4.6 V), InGaAs (5.0 V), and AlGaAs (1.3 V) configurations, respectively. Thermodynamic analysis reveals hydrogen adsorption enthalpies of approximately − 0.58 and − 0.19 kJ/mol for DG and CSDG MOSFET devices. This interdisciplinary approach highlights the synergy between nano-material-based hydrogen sensing and fabrication technology, offering a transformative solution for hydrogen detection in industrial processes and emerging energy applications. Furthermore, the strategic implementation of fabrication techniques enhances the precision and reproducibility of sensor devices, ensuring consistent and reliable performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02447-4.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145168092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Theoretical and hardware-level precising in MASH 1-1-1 modulators with eliminable dither 具有可消除抖动的mash1.1调制器的理论和硬件级精度

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-24 DOI: 10.1007/s10470-025-02445-6

Gisela De La Fuente-Cortes, Rosalba Perdomo-Cosme, Maria M. Perez-Torres, Victor R. Gonzalez-Diaz

引用次数: 0

Nondestructive reading technique and refreshment circuit for symmetric and asymmetric stochastic memristors 对称和非对称随机忆阻器无损读取技术及刷新电路

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-24 DOI: 10.1007/s10470-025-02440-x

Mai M. Goda, Hassan Mostafa, Ahmed M. Soliman

{"title":"Nondestructive reading technique and refreshment circuit for symmetric and asymmetric stochastic memristors","authors":"Mai M. Goda, Hassan Mostafa, Ahmed M. Soliman","doi":"10.1007/s10470-025-02440-x","DOIUrl":"10.1007/s10470-025-02440-x","url":null,"abstract":"<div><p>Eventually, Neuromorphic computing structures, which are bio-inspired alternatives to more conventional computing techniques, have been more notable. The researchers have attempted to harness the inherent disparity in electronic design to invent neuromorphic systems with intrinsically stochastic behavior. Theoretically, Networks incorporating stochastic neural networks (NNs) component can develop complicated statistical models of their environments. The memristors’ disparity in neuromorphic structures is mimicked in abstract models of noisy and unreliable brain parts. The stochastic memristor is an intrinsic source of disparity that permits neurons to generate spikes stochastically. The stochastic memristors are mimicked in bi-stable stochastic synapses. This paper studies the stochastic behavior of various memristor models. The configuration of the two-transistor-one-memristor (2T1M) synapse is very efficient in the neuromorphic synapse for its capability to adjust the reading and upgrade the weight on-chip by signals and applied with a nondestructive reading mechanism for asymmetric and symmetric stochastic memristors. A refreshment circuit is applied to recover the right weight when any destructive reading operations occur.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145168421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Frequency compensated triple cascode telescopic operational amplifier 频率补偿三级联码伸缩运算放大器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-24 DOI: 10.1007/s10470-025-02441-w

Komal Duhan, Neelam Rup Prakash, Jasbir Kaur, Sameeksha Munjal

引用次数: 0

A review of high current digital constant current sources in Switch-Mode power supplies 开关电源中大电流数字恒流源的研究进展

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-20 DOI: 10.1007/s10470-025-02453-6

Maoliang Jian, Wangyu Du, Xiao Ling, Jianhua Zhang, Lianqiao Yang

引用次数: 0

Work function engineered polarity-controlled TFET for digital circuit applications: design and performance analysis 工作功能工程极性控制TFET的数字电路应用：设计和性能分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-20 DOI: 10.1007/s10470-025-02446-5

Sajai Vir Singh, Mukesh Kumar Bind, Kaushal Kumar Nigam, Dharmender

{"title":"Work function engineered polarity-controlled TFET for digital circuit applications: design and performance analysis","authors":"Sajai Vir Singh, Mukesh Kumar Bind, Kaushal Kumar Nigam,  Dharmender","doi":"10.1007/s10470-025-02446-5","DOIUrl":"10.1007/s10470-025-02446-5","url":null,"abstract":"<div><p>In this manuscript, a polarity-controlled TFET (PC-TFET) with an engineered work function is investigated for the realization of both primary and universal Boolean logic functions in digital applications. The primary objective of the proposed approach is to reduce the number of transistors required for implementing digital logic functions on a chip compared to conventional MOS-based technology. To achieve this, the p<sup>+</sup> and n<sup>+</sup> regions at the source and drain are induced using an appropriate work function on an ultra thin silicon film for n-type TFET. This single PC-nTFET device is highly versatile and capable of realizing all fundamental two-input Boolean functions, including NOT, OR, NAND, XOR, AND, and NOR by adjusting bias voltages at the control and polarity gates (CG and PG). The operational behavior of the realized logic functions is analyzed through various parameters, such as carrier concentrations, energy band diagrams, transfer characteristics, and transient characteristics. The decision to designate a higher ON-current as output logic “1\" and a low OFF-current as output logic “0\" is both practical and intuitive. Additionally, the junction- and doping-free nature of the proposed model represents a strategic design choice that simplifies fabrication complexity and reduces costs. Overall, this model demonstrates strong potential for the implementation of high-speed, power-efficient digital circuits and compact logic functions.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145167110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low-temperature coefficient, low power, and area-efficient temperature-compensated CMOS voltage reference for energy harvesting systems 低温度系数，低功耗，面积有效的温度补偿CMOS电压基准能量收集系统

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-20 DOI: 10.1007/s10470-025-02427-8

Komal Duggal, Rishikesh Pandey, Vandana Niranjan

{"title":"A low-temperature coefficient, low power, and area-efficient temperature-compensated CMOS voltage reference for energy harvesting systems","authors":"Komal Duggal, Rishikesh Pandey, Vandana Niranjan","doi":"10.1007/s10470-025-02427-8","DOIUrl":"10.1007/s10470-025-02427-8","url":null,"abstract":"<div><p>A simple all-MOS transistor-based voltage reference without using any passive resistor or amplifier is presented in this paper. The temperature compensation has been achieved by utilizing a sequence of composite NMOS transistors, to attain a low-temperature coefficient reference voltage across an extensive range of temperatures. Since temperature compensation in the proposed voltage reference has been attained by using only three NMOS transistors rather than the larger compensation circuits, it reduces the area consumption while still attaining the minimal temperature coefficient. Achieving a temperature coefficient of less than 10 ppm/°C is a common goal for BJT-based voltage references while the proposed voltage reference can achieve this goal using only the MOS transistors with standard threshold voltages. The proposed temperature-compensated CMOS voltage reference has been simulated in 180 nm which delivers an output reference voltage of 451.2 mV. Measurement outcomes show that the suggested circuit works for an extensive range of temperatures from − 40 °C to 140 °C with a minimum temperature coefficient of 7.5 ppm/°C which is the feature of the BJT-based BGR. The power supply rejection ratio for the frequency range of 1 Hz–10 kHz is obtained as − 53.81 dB and the line sensitivity is computed as 0.35%/V. The output noise is 0.51 µV/√Hz at 1 Hz. Moreover, at ambient temperature, the area and power consumed by the proposed circuit are 0.000428 mm<sup>2</sup> and 0.7 µW, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145167867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low distortion analog switch for high linearity and performance applications based on negative-voltage bootstrapped capacitor and dummy switch techniques 基于负电压自举电容和虚拟开关技术的高线性度和高性能应用的低失真模拟开关

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-17 DOI: 10.1007/s10470-025-02450-9

Mahtab Nasri Nasrabadi, Mehdi Dolatshahi

{"title":"A low distortion analog switch for high linearity and performance applications based on negative-voltage bootstrapped capacitor and dummy switch techniques","authors":"Mahtab Nasri Nasrabadi, Mehdi Dolatshahi","doi":"10.1007/s10470-025-02450-9","DOIUrl":"10.1007/s10470-025-02450-9","url":null,"abstract":"<div><p>This study introduces a novel bootstrapped sampling switch designed for high-resolution, low-distortion input analog-to-digital converters (ADCs). The proposed switch incorporates negative-voltage bootstrapped capacitor and dummy switch techniques. The primary advantages of the proposed circuit include significant reductions in charge injection effects and parasitic gate capacitance, achieved through the dummy switch and negative-voltage bootstrapped capacitor techniques, respectively. The proposed design reduces parasitic capacitance by over 30% compared to conventional structures. Simulated in 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology, the switch delivers rail-to-rail input voltage performance. It achieves an effective number of bits (ENOB) of 17.4 bit, a signal-to-noise and distortion (SINAD) ratio of 106.5 dB, a signal-to-noise ratio (SNR) of 108.5 dB, a spurious-free dynamic range (SFDR) of 113.2 dB, and a total harmonic distortion (THD) of -110.8 dB at a supply voltage of 1.8 V and a sampling rate of 50 MHz. This makes the proposed switch highly suitable for low-voltage, high-accuracy, and high-speed applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145166591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Defect analysis and optimization of nanomaterial-based liner materials for 3D-IC integration 3D-IC集成纳米材料衬里材料缺陷分析与优化

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2025-06-16 DOI: 10.1007/s10470-025-02444-7

Santosh Kumar Tallapalli, V. Vijayakumar, Asisa Kumar Panigrahy, N. Arun Vignesh

{"title":"Defect analysis and optimization of nanomaterial-based liner materials for 3D-IC integration","authors":"Santosh Kumar Tallapalli, V. Vijayakumar, Asisa Kumar Panigrahy, N. Arun Vignesh","doi":"10.1007/s10470-025-02444-7","DOIUrl":"10.1007/s10470-025-02444-7","url":null,"abstract":"<div><p>Many technological advancements have been made because of the growth of IC. Everyday use of technology has had a profound impact on lives and existence, which would be unthinkable without them. As a result, the reliability issues associated with recent devices necessitate extraordinary, specialized effort. Accommodating several devices in a single and planar IC leads to various system-level damages to the IC, like the hot carrier effect, oxide breakdown, etc. This paper examines optimization strategies to improve the performance of nanomaterial-based liner materials in noise coupling sustainability. It also gives a complete defect analysis of those materials through electrical interventions. Active devices in one IC are integrated through another IC via vertical bonding. Through Silicon Vias (TSVs) and operational transistors are a major issue when implementing 3D IC, since it significantly lowers system efficiency. This study provides an innovative way to reduce electrical interference by utilizing several electrical interference designs, which include the TTSV framework, which also incorporates Thermal TSV while simulation, and the ETSV framework, which solely utilizes electrical signal carrying TSV. The study examined the electrical intervention of TSV-carrying signals to the substrate and other TSV. Additionally, using several suggested designs, this work shows further elevated frequency regimes up to 1 THz. Our simulation result suggests the proposed model has a marginal advantage in 3D IC developments with more than a 30% drop in electrical signal intervention from signal-carrying TSV to other TSV. Additionally, a guard ring was used to demonstrate electrical interference. When Teflon AF1600 liner material was used at the victim along with a P + protection ring, TSV demonstrated very little electrical interference. Additionally, the thermal effect was studied for the proposed TSV model.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145166658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0