Analog Integrated Circuits and Signal Processing最新文献

{"title":"Widely tunable THz source based on constructive wave oscillator in a 130-nm SiGe BiCMOS","authors":"Göker Ariyak","doi":"10.1007/s10470-025-02333-z","DOIUrl":"10.1007/s10470-025-02333-z","url":null,"abstract":"<div><p>This paper presents a novel tunable THz source based on a six-section Constructive Wave Oscillator (CWO) designed in a 130-nm SiGe BiCMOS process. Unlike traditional THz source designs that rely on VCOs and frequency multipliers, this approach offers a simple, compact, and yet power-efficient solution. The proposed architecture achieves a <span>(10 %)</span> tuning range and generates phasor signals beyond the conventional I/Q (<span>(0^{circ })</span>–<span>(90^{circ })</span>) type, enabling new possibilities for modulation schemes and harmonic cancellation. The design generates a 0.285 THz signal based on a tunable CWO operating at 95 GHz, with 95 GHz signals distributed along the ring with <span>(60^{circ })</span> phases. The THz source combines these signals to produce a signal at <span>(3f_0)</span> using a harmonic cancellation technique. The circuit occupies a compact area of 0.46 × 0.51 <span>(hbox {mm}^2)</span> and dissipates only 60 mW of DC power from a 2V supply. The tunable THz source demonstrates a simulated -22 dBm output power and a phase noise of -76 dBc/Hz at a 1 MHz offset, making it a significant advancement in the field of THz signal generation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 512-ns conversion time 13-bit parallel two-step single-slope ADC for hundreds of mpxiel CMOS image sensors","authors":"Ruiming Xu,&nbsp;Zhongjie Guo,&nbsp;Changxu Su,&nbsp;Suiyang Liu,&nbsp;Ningmei Yu","doi":"10.1007/s10470-025-02314-2","DOIUrl":"10.1007/s10470-025-02314-2","url":null,"abstract":"<div><p>This paper proposes a 13-bit parallel two-step single slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be + 0.8/-0.8 LSB and + 2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 74.4% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143110115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A probabilistic approach to design inexact compressors for approximate booth multipliers","authors":"Bindu G Gowda,&nbsp;H C Prashanth,&nbsp;V N Muralidhara,&nbsp;Madhav Rao","doi":"10.1007/s10470-025-02327-x","DOIUrl":"10.1007/s10470-025-02327-x","url":null,"abstract":"<div><p>Approximate computing is accepted for error-tolerant tasks including image and signal processing applications, where execution time is more critical than accuracy. Approximation in the multiplier design is considered highly beneficial due to reduced hardware requirements and yet achieves acceptable inference from the rendered output. A probabilistic approach to build approximate compressors specifically for Radix-4 modified booth multiplier is designed to provide power and footprint savings, and at the same time offer performance benefits with lesser errors. The inexact compressor design when applied on the booth encoded reduced partial products (PP) offers a significant improvement over the existing approximate multiplier design. Five variants of inexact multiplier designs were derived by placing approximate compressors across the columns of the Booth multiplier generated partial product matrix (PPM). Two additional design variants including truncation on the lower significant part of the PPM in the multiplier design were also investigated. All the proposed multiplier design variants were synthesized and characterized for hardware parameters, and error metrics. Two design configurations: Design-1 with the conventional approach of sign extending each PP rows till the <span>((2n-1){th})</span> bit in an <span>(ntimes n)</span> multiplier, and Design-2 without sign extension with a modified PPM, are considered to evaluate all the seven proposed multiplier variants in each case. The <span>(9times 9)</span> Design-1 achieved the maximum benefit of 46.27%, 61.18%, 16.79%, and 66.18% in footprint, power, delay, and overall product of delay and power (PDP), while Design-2 achieved the maximum of 61.33%, 77.54%, 41.45%, and 86.8% footprint, power, delay, and PDP savings respectively over their exact versions. <span>(16times 16)</span> Design-2 variant exhibited the maximum of 11.29%, 32.01%, and 32.42% area, power and PDP improvements, respectively, among the evaluated design variants in comparison with the exact one. The proposed approximate multipliers also showcased superior Mean Relative Error Distance (MRED) and <span>(P_{textrm{RED}})</span> (Probability of getting an RED smaller than 2%) when compared with various existing works. The proposed design variants in this work were evaluated for the applications: image smoothing using the Gaussian filter, image segmentation using k-means clustering which is an unsupervised learning algorithm popularly used in computer vision systems, <span>(mu -law)</span> algorithm which is a standard companding algorithm mainly used in telecommunication systems, and Convolutional Neural Network (CNN) to present error-tolerant results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143110031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of high-performance quaternary half adder, full adder, and multiplier","authors":"Majid Jafari,&nbsp;Samira Sayedsalehi,&nbsp;Reza Faghih Mirzaee,&nbsp;Razieh Farazkish","doi":"10.1007/s10470-025-02317-z","DOIUrl":"10.1007/s10470-025-02317-z","url":null,"abstract":"<div><p>This paper presents high-performance quaternary circuit cells, including adders and a multiplier, based on carbon nanotube field-effect transistors (CNTFETs). The proposed circuits consist of two separate parts, each of which is designed independently. The first part is a new quaternary decoder, and the second part is the main circuit body constructed by pass-transistor logic (PTL) and transmission-gate logic (TGL). These circuit methodologies result in novel quaternary designs with fewer transistors compared to the existing circuits in the literature. Several simulations by HSPICE and the 32nm CNTFET library are performed to evaluate the performance of the new circuits. Compared to previous works, the proposed designs reduce power-delay product (PDP) and energy-delay product (EDP) considerably. For example, the new quaternary full adder (QFA), with 46 fewer transistors, decreases the PDP and EDP of the best existing competitor by 32.6% and 65.3%, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143109911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel six-wing chaotic system with line equilibrium and its application in image encryption","authors":"Ping Li,&nbsp;Lei Xia,&nbsp;Yigang Fan,&nbsp;Jin Qian","doi":"10.1007/s10470-025-02309-z","DOIUrl":"10.1007/s10470-025-02309-z","url":null,"abstract":"<div><p>This paper presents a novel chaotic system with linear equilibrium, which has six wings compared to the conventional chaotic system. Different types of attractors, including chaotic, cycle-doubling bifurcation and coexisting attractor types, are obtained by controlling a single parameter through analytical tools such as phase diagrams, bifurcation diagrams, Poincare diagrams, and Lyapunov exponentials (LEs) as a means of verifying that the system has dynamical properties suing a high degree of complexity and stochasticity. In particular, offset lifting control and sensitivity to initial values are found. In addition, two positive LEs are observed when the parameters are fixed. The agreement between the analogue circuit and the numerical simulation through Multisim simulation confirms the feasibility of the theoretical model of the new system. The proposed system is applied to image encryption based on the classical algorithms, and its histogram, neighbouring pixel correlation, attack resistance and information entropy can be verified. The experimental results show that the new system is very sensitive to the key and plaintext, and it can effectively resist statistical attacks and differential attacks.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143110032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fully digital temperature sensor with 187-(mu text {m}^{2}) front-end for on-chip thermal management in 55-nm CMOS","authors":"Zhao Yang,&nbsp;Hao Li,&nbsp;Peiyong Zhang","doi":"10.1007/s10470-025-02321-3","DOIUrl":"10.1007/s10470-025-02321-3","url":null,"abstract":"<div><p>This article proposes a fully digital temperature sensor with ultra-small sensing front-end for on-chip thermal management. Utilizing the temperature characteristics of MOSFET leakage current, an innovative Leakage-Dominated inverting Schmitt-Trigger (LDST) is proposed. The ring oscillator composed of LDST achieves temperature-to-frequency conversion. Different from the traditional fixed resolution and conversion time within the full temperature range, Adaptive Resolution Frequency-to-Digital Converter (AR-FDC) is proposed to realize faster measurement speed at high temperatures to timely prevent chip overheating while maintaining high resolution at low temperatures. Fabricated with a 55 nm CMOS process, the front-end of proposed temperature sensor occupies a silicon area of just 187 <span>(mu text {m}^2)</span>. The temperature sensor achieves a resolution Figure of Merit (FoM) of 208 <span>(text {pJ}cdot text {K}^{2})</span>, the power consumption of 7.2 <span>(mu text {W})</span>, the resolution of 112 mK, the conversion time of 1.66 ms at 20<span>(^circ hbox { C})</span>, the max-min inaccuracy of <span>(+0.48/-0.46^circ hbox { C})</span> and 3<span>(sigma)</span>-inaccuracy of ±0.73<span>(^circ hbox { C})</span> from <span>(-10)</span> to 120<span>(^circ hbox { C})</span> after two-point calibration. It can operate under a supply voltage ranging from 0.8 to 1.3 V, with a supply sensitivity of 3.02 <span>(sim)</span> 4.51<span>(^circ hbox { C})</span>/V.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143109722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reversible logic circuit design using QCA based modified Fredkin gate","authors":"Jadav C. Das,&nbsp;Tanay Chattopadhyay,&nbsp;Debashis De","doi":"10.1007/s10470-025-02325-z","DOIUrl":"10.1007/s10470-025-02325-z","url":null,"abstract":"<div><p>Quantum-dot cellular automata (QCA) is presently considered for implementing ultra-large-scale integrated circuits. The design of different arithmetic and logical units using QCA is of high research interest in the current scenario. Apart from this, QCA has also found its application in the reversible domain. To the best of our knowledge various QCA based reversible circuits have already been reported in many works. But most of the works are mainly focused on designing the well-established reversible gates viz. Fredkin, Toffoli, Peres, etc. in QCA and making bigger circuits using these gates. The research reported in this literature deals with a completely new QCA layout of a reversible gate. This proposed gate is an updated version of Fredkin gate and named as modified Fredkin gate (MFG). We can implement 16 primitive logic operations using a single MFG unit. Apart from that, MFG is a quantum gate whose quantum realization is also shown in this literature. The proposed 4 × 4 MFG can configure the circuit of <i>n</i>-input XOR-XNOR and OR-AND gate.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143109721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new dual memristor hyperchaotic system: dynamic properties, electronic circuit, and image encryption","authors":"Jie Fang,&nbsp;Jiabin Wang,&nbsp;Kaihui Zhao,&nbsp;Yong Jiang,&nbsp;Wanyong Liang","doi":"10.1007/s10470-025-02322-2","DOIUrl":"10.1007/s10470-025-02322-2","url":null,"abstract":"<div><p>A dual memristor four-dimensional hyperchaotic system with charge-controlled memristor and flux-controlled memristor is introduced in this paper. The basic dynamic properties analysize indicate that the system has infinitely line equilibrium points and rich memristor chaotic dynamics properties. The equivalent electronic circuit of the dual memristor hyperchaotic system is realized by means of integrated operational amplifiers and common electronic devices. The experimental results of the circuit are consistent with the numerical simulation results, which prove the existence and physical realizability of the system. Finally, a new image encryption algorithm is designed by combining the chaotic sequences generated by the new dual memristor hyperchaotic system with DNA dynamic encryption and image block diffusion. The initial values of the chaotic sequences are related to the pixel values of the original image, so it can effectively improve the resistance of encryption algorithms to plaintext attacks. The DNA matrix is divided into DNA sub-matrices blocks to realize diffusion operation, which greatly enhances the spatial complexity and security of the encryption algorithm. The simulation examples and algorithm security analysis demonstrate the effectiveness of the proposed encryption scheme.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143109648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and simulation of low power single event upset-resilient SRAM cell","authors":"Neha Pannu,&nbsp;Neelam Rup Prakash","doi":"10.1007/s10470-025-02326-y","DOIUrl":"10.1007/s10470-025-02326-y","url":null,"abstract":"<div><p>Radiation induced soft errors impact memory circuits and their response gets transposed or disturbed which makes it crucial to protect the memory unit. Radiation-immune memory devices have extensive applications in space, biomedical, smart devices, and wearable devices. A radiation hardened by design circuit using Dual Interlocked Storage Cell (DICE) is implemented with varied transistor sizing to propose the design that has optimum performance and minimum power dissipation. The design is tested for Single Event Upsets using the double exponential current model for current source of maximum amplitude 1 A. The proposed design is validated using Cadence Virtuoso version IC 6.1.5 at 180 nm CMOS technology node with variation of ± 10% of V_DD = 1.8 V. The sensitivity of the circuit to process, voltage and temperature variations are shown with the help of Monte Carlo simulations. Various iterations performed during simulations make the proposed circuit suitable for use in critical applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143109660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel semi elliptical slotted dual port rectenna for RF energy harvesting","authors":"John Bosco John Paul,&nbsp;Aruldas Shobha Rekh,&nbsp;Evangeline Persis Gell Prabakaran","doi":"10.1007/s10470-025-02323-1","DOIUrl":"10.1007/s10470-025-02323-1","url":null,"abstract":"<div><p>In this paper, a novel semi elliptical slotted dual-port microstrip rectenna for harvesting ambient radio frequency (RF) energy is presented. This green energy harvesting technique captures the RF radiation with the help of an antenna and converts it to direct current (DC) power with the help of a rectifier to activate electronic devices. The presented antenna in this paper is characterized by semi elliptical shaped slots and features two ports 1 and 2. In Port 1, the antenna is designed to harvest energy from 1.71 GHz, 2.33 GHz, 5 GHz, and 5.8 GHz, while in Port 2, it is designed to harvest energy from 2.31 GHz, 3.26 GHz, and 3.84 GHz. The antenna's dimensions are 44 × 44 (mm) which is designed and simulated in HFSS Software. Aside from the antenna, a non-uniform transmission line matching circuit and a voltage doubler rectifying circuit are developed in ADS software for converting the RF power acquired by the antenna into DC power. Furthermore, the proposed antenna is fabricated and measured with a Keysight Vector Network Analyzer. The rectifying circuit is also fabricated which measures 25 × 17 (mm). At both Port 1 and 2, antenna simulation results of return loss, current distribution, radiation pattern in E-plane and H-plane, and VSWR are obtained. The antenna's simulated and measured results are observed to agree with each other. Moreover, with an input power of 10 dBm, the maximum efficiency is found to be 52%, and the output voltage is 3.2 V. The novelty of this paper lies in the fact that inserting semi elliptical slots on the four sides of the antenna’s patch creates multiple resonance frequencies and also reduces the size. Ultimately, the proposed rectenna system is compact with good efficiency, output voltage and a potential alternative source for powering low-power devices.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143109666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}