Design of high-performance quaternary half adder, full adder, and multiplier

Abstract

This paper presents high-performance quaternary circuit cells, including adders and a multiplier, based on carbon nanotube field-effect transistors (CNTFETs). The proposed circuits consist of two separate parts, each of which is designed independently. The first part is a new quaternary decoder, and the second part is the main circuit body constructed by pass-transistor logic (PTL) and transmission-gate logic (TGL). These circuit methodologies result in novel quaternary designs with fewer transistors compared to the existing circuits in the literature. Several simulations by HSPICE and the 32nm CNTFET library are performed to evaluate the performance of the new circuits. Compared to previous works, the proposed designs reduce power-delay product (PDP) and energy-delay product (EDP) considerably. For example, the new quaternary full adder (QFA), with 46 fewer transistors, decreases the PDP and EDP of the best existing competitor by 32.6% and 65.3%, respectively.