Modeling and simulation of low power single event upset-resilient SRAM cell

Abstract

Radiation induced soft errors impact memory circuits and their response gets transposed or disturbed which makes it crucial to protect the memory unit. Radiation-immune memory devices have extensive applications in space, biomedical, smart devices, and wearable devices. A radiation hardened by design circuit using Dual Interlocked Storage Cell (DICE) is implemented with varied transistor sizing to propose the design that has optimum performance and minimum power dissipation. The design is tested for Single Event Upsets using the double exponential current model for current source of maximum amplitude 1 A. The proposed design is validated using Cadence Virtuoso version IC 6.1.5 at 180 nm CMOS technology node with variation of ± 10% of V_DD = 1.8 V. The sensitivity of the circuit to process, voltage and temperature variations are shown with the help of Monte Carlo simulations. Various iterations performed during simulations make the proposed circuit suitable for use in critical applications.