Analog Integrated Circuits and Signal Processing最新文献_第10页

FPGAs: architecture, design flow, and emerging applications—industrial perspectives fpga：架构，设计流程和新兴应用-工业前景

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-14 DOI: 10.1007/s10470-026-02563-9

Huu Q. Tran

{"title":"FPGAs: architecture, design flow, and emerging applications—industrial perspectives","authors":"Huu Q. Tran","doi":"10.1007/s10470-026-02563-9","DOIUrl":"10.1007/s10470-026-02563-9","url":null,"abstract":"<div>\u0000 \u0000 <p>The convergence of artificial intelligence, cyber–physical systems, and sustainable manufacturing is reshaping the industrial landscape under the principles of Industry 5.0. This evolution calls for hardware platforms that seamlessly combine real-time determinism, reconfigurability, and energy efficiency while ensuring long-term reliability in demanding environments. Field-Programmable Gate Arrays (FPGAs) have become pivotal in this transition, bridging the gap between general-purpose processors and application-specific hardware. This paper presents a comprehensive survey of modern FPGA technology from an Industry 5.0 perspective. More than one hundred recent studies, industrial reports, and vendor architectures are synthesised to characterise FPGA evolution across three dimensions: architectural foundations, unified design methodologies, and emerging application domains. The survey highlights how heterogeneous SoC integration, high-level synthesis, partial reconfiguration, and AI-assisted EDA workflows collectively enable deterministic, low-power, and adaptive hardware platforms for robotics, smart manufacturing, intelligent transportation, healthcare systems, and edge AI. Furthermore, the review outlines future directions, including chiplet-based integration, virtualized reconfigurable fabrics, neuromorphic/quantum hybrids, and sustainability-aware lifecycle design. By consolidating cross-domain insights, this survey positions FPGAs as a core enabling technology for human-centric, resilient, and sustainable Industry 5.0 cyber-physical ecosystems.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147441562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementation of hybrid random number generator on FPGA: Combining lorenz chaotic system with carry chain based ring oscillator 混合随机数发生器在FPGA上的实现：结合lorenz混沌系统和进位链环振荡器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-10 DOI: 10.1007/s10470-026-02572-8

Baoshuo Fan, Xiangye Zeng, Jingyi Wang, Mingming Luo, Xiaoyu Li, Jianfei Liu, Jia Lu, Jie Ma

{"title":"Implementation of hybrid random number generator on FPGA: Combining lorenz chaotic system with carry chain based ring oscillator","authors":"Baoshuo Fan, Xiangye Zeng, Jingyi Wang, Mingming Luo, Xiaoyu Li, Jianfei Liu, Jia Lu, Jie Ma","doi":"10.1007/s10470-026-02572-8","DOIUrl":"10.1007/s10470-026-02572-8","url":null,"abstract":"<div><p>Random number generators (RNGs) are crucial in various fields like radar anti-jamming, cryptographic security, and physical testing. These fields demand that RNGs provide high randomness, unpredictability, and throughput. This paper presents a combination of true random number generator (TRNG) and the Lorenz chaotic system to develop a novel hybrid random number generator (HRNG) on FPGA. By periodically updating the initial value of the Lorenz chaotic system with true random numbers, the HRNG is able to realize the unpredictability of chaotic systems. The TRNG employs ring oscillator (RO) as the entropy source, and utilizes carry-logic primitives within FPGA to improve entropy extraction efficiency. The proposed HRNG is implemented on Xilinx FPGAs with resource-saving and data throughput features and achieves 484.86 Mbps and 400 Mbps throughput on Xilinx Kintex-7 and Spartan-6 FPGAs, respectively. The random numbers yielded by the HRNG are verified by the NIST 800 − 22 test and GM/T 0005-2021 test, indicating that the HRNG output meets cryptographic standards and exhibits adequate randomness.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"127 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147375301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Voltage controlled ring oscillator with multi-frequency shift keying technique for jitter reduction in 180 nm CMOS technology 在180nm CMOS技术中采用多频移键控技术的压控环形振荡器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-07 DOI: 10.1007/s10470-026-02576-4

Abhishek Mishra, Anil Singh, Alpana Agarwal

{"title":"Voltage controlled ring oscillator with multi-frequency shift keying technique for jitter reduction in 180 nm CMOS technology","authors":"Abhishek Mishra, Anil Singh, Alpana Agarwal","doi":"10.1007/s10470-026-02576-4","DOIUrl":"10.1007/s10470-026-02576-4","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO) with an enhancement in the linearity range of VCRO by many folds. The proposed technique is helpful in VCRO-based analog-to-digital converters (ADC), Phase Locked Loop (PLL), and time-based circuits, where the jitter accumulation of VCRO severely degrades performance. In the proposed technique, a 4-bit vernier time-to-digital converter (VTDC) is used to extract jitter in terms of 4-bit thermometer code (TC) with a sensitivity of 10 ps/bit. The 4-bit thermometer code is input to a multi-frequency shift keying (M-FSK) bit generator to tune the frequency of VCRO for reducing jitter, and in this way the complexity of the thermometer to binary code converter circuit is bypassed. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply and occupies an area of 89.59 × 79 μm<sup>2</sup>. After enabling the proposed technique, the RMS jitter reduces from 125.95 ps to 76.125 ps for VCRO running at 76.08 MHz and consumes a total power of 1.6mW with FOM of -202.276 dB.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling and simulation of GaInAsN/GaAs MOS-HEMT for rapid detection in biosensor applications 用于生物传感器快速检测的GaInAsN/GaAs MOS-HEMT建模和仿真

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-04 DOI: 10.1007/s10470-026-02574-6

Chumki Das, Kaushik Mazumdar

{"title":"Modeling and simulation of GaInAsN/GaAs MOS-HEMT for rapid detection in biosensor applications","authors":"Chumki Das, Kaushik Mazumdar","doi":"10.1007/s10470-026-02574-6","DOIUrl":"10.1007/s10470-026-02574-6","url":null,"abstract":"<div>\u0000 \u0000 <p>High Electron Mobility Transistors (HEMTs) technology is being explored for the development of biosensors. While numerous floating gate HEMT-based biosensors have been experimentally developed, limited research exists on the modeling of MOSHEMT-based biosensors. In this work, an analytical model for an GaInAsN/GaAs MOSHEMT biosensor is presented for the first time, aimed at detecting biomolecules such as proteins, streptavidin, ChOx, and uricase using a dielectric modulation approach. The study focuses on detecting change in drain current for different biomolecules. Simulations of the proposed MOSHEMT structure were carried out using the SILVCO ATLAS TCAD device simulator. The simulation results show significant variations in the drain current and threshold voltage due to changes in the biomolecules within the cavity region. The threshold voltage experiences the highest positive shift for uricase, attributed to its low dielectric constant. The outcomes of the analytical model have been validated, showing strong agreement with the simulated results.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147363219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A highly tunable ultra-low cut-off frequency gm-c filter with bandwidth stabilization technique 具有带宽稳定技术的高可调谐超低截止频率gm-c滤波器

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-03 DOI: 10.1007/s10470-026-02570-w

Morteza Mahdi Sasan, Hassan Faraji Baghtash

{"title":"A highly tunable ultra-low cut-off frequency gm-c filter with bandwidth stabilization technique","authors":"Morteza Mahdi Sasan, Hassan Faraji Baghtash","doi":"10.1007/s10470-026-02570-w","DOIUrl":"10.1007/s10470-026-02570-w","url":null,"abstract":"<div><p>In this paper, an efficient technique for stabilizing the bandwidth of ultra-low-frequency biomedical gm-C filters is proposed. With the proposed method, the bandwidth becomes much less dependent on variations in circuit elements caused by process shifts, temperature changes, or supply fluctuations, thereby allowing more effective and accurate tuning. The dependency of the cutoff frequency on circuit parameters is first analyzed theoretically, and then a symmetrical current-difference generation circuit is introduced to mitigate this effect. A 4th-order gm-C filter was designed and implemented in TSMC 180 nm CMOS technology, achieving a tunable bandwidth from 50 mHz to 20 Hz with a power consumption of 0.73 µW. Post-layout simulations with extracted parasitics confirm the robustness of the design, showing less than ± 14% variation under temperature changes (0–65 °C), less than 1% deviation for ± 10% supply fluctuations, and less than 0.7% statistical variation in Monte Carlo analysis. The cutoff frequency also remains stable across different process corners. These results, supported by both theoretical analysis and extensive post-layout simulations, demonstrate that the proposed filter provides high tunability, excellent bandwidth stability, and practical feasibility, making it highly suitable for low-frequency biomedical applications such as ECG and EEG signal processing.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147336657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive analysis of CNTFET-based low-power SRAM cell 基于cntfet的低功耗SRAM电池的综合分析

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-03-02 DOI: 10.1007/s10470-026-02577-3

Ekta Jolly, Vijay Kumar Sharma, Anil Kumar Bhardwaj

{"title":"Comprehensive analysis of CNTFET-based low-power SRAM cell","authors":"Ekta Jolly, Vijay Kumar Sharma, Anil Kumar Bhardwaj","doi":"10.1007/s10470-026-02577-3","DOIUrl":"10.1007/s10470-026-02577-3","url":null,"abstract":"<div>\u0000 \u0000 <p>Carbon nanotube field-effect transistor (CNTFET) technology has evolved as a promising substitute to metal oxide semiconductor field-effect transistor (MOSFET) technology. CNTFET technology provides excellent electrical properties like greater carrier mobility, ballistic transport, and variable threshold. In MOSFET, the short-channel effects become dominant at lower technology nodes due to continuous device scaling, which degrades the various performance metrics. In this work, a CNTFET-based static random-access memory (SRAM) cell is designed using the low-power input-controlled stack (ICS) technique. The proposed SRAM (ICS-SRAM) cell exhibits enhanced performance and stability when compared to existing designs. The proposed ICS-SRAM is simulated using the Stanford 32 nm CNTFET model at a supply voltage of 0.7 V to evaluate the different performance metrics. The simulation results indicate that the ICS-SRAM cell achieves improvement in average power dissipation and energy efficiency compared to existing designs. The speed of SRAM cell is also improved with ICS technique. The stability analysis is conducted for the ICS-SRAM cell using the butterfly and the N-curve methods. The variability analysis of the ICS-SRAM cell is performed for the static noise margin (SNM) metric under process, voltage, and temperature (PVT) variations to evaluate its reliability for 1000 samples using Monte Carlo simulations. The Kolmogorov-Smirnov (K-S) test for the Monte Carlo results has been performed using MATLAB.</p>\u0000 </div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147335771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FinFET-based fully differential Butterworth filter using a multiple-input dynamic threshold OTA for low-power biomedical signal processing 基于finfet的全差分巴特沃斯滤波器，采用多输入动态阈值OTA用于低功耗生物医学信号处理

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-02-24 DOI: 10.1007/s10470-026-02565-7

M. Venkata Sudhakar, Y. Ravi Sankaraiah, B. Bhaskar Reddy, P. Raghava Reddy

{"title":"FinFET-based fully differential Butterworth filter using a multiple-input dynamic threshold OTA for low-power biomedical signal processing","authors":"M. Venkata Sudhakar, Y. Ravi Sankaraiah, B. Bhaskar Reddy, P. Raghava Reddy","doi":"10.1007/s10470-026-02565-7","DOIUrl":"10.1007/s10470-026-02565-7","url":null,"abstract":"<div><p>Wearable biomedical applications, such as electrocardiogram (ECG) monitors, have begun to employ Butterworth filters as anti-aliasing filters. In both analog and mixed-signal circuits, the operational transconductance amplifier (OTA) plays an essential role. Nevertheless, higher-order filters realized via OTA-based active filters consume more power due to the improved amount of active devices required. Additionally, at lower technology nodes, the leakage currents of conventional complementary metal-oxide semiconductor (CMOS) transistors are higher than those of fin-shaped field-effect transistors (FinFETs). This work proposes new fully differential Butterworth filters (FDBFs) that use FinFET technology and are based on multiple input and multiple output dynamic threshold OTA (MIMO-DT-OTA). One inverter-based OTA and five MIMO-DT-OTAs are cascaded to create an FDB-LPF, or fully differential Butterworth Low pass filter. A universal Butterworth filter (UBF) with five unity gain filtering functions, an all-pass function (APF), low-pass function (LPF), band-pass function (BPF), a high-pass function (HPF), and a band-stop function (BSF) was built to further illustrate the effectiveness of the proposed MIMO-DT-OTA. With a power consumption of 43 nW at 0.5 V supply voltage, the proposed universal filter is constructed utilizing 14 nm FinFET technology. In addition, for a sine input signal up to 300 mV pp, the proposed filter drops the total harmonic distortion (THD) below 1%.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147341718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel device-to-device integration method using minimal impedance optimization for internet of things (IoT) sensing devices 基于最小阻抗优化的物联网（IoT）传感设备的新型设备到设备集成方法

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-02-23 DOI: 10.1007/s10470-026-02578-2

Muralidharan J, Suresh Kumar Pittala, Suresh Balanethiram

{"title":"A novel device-to-device integration method using minimal impedance optimization for internet of things (IoT) sensing devices","authors":"Muralidharan J, Suresh Kumar Pittala, Suresh Balanethiram","doi":"10.1007/s10470-026-02578-2","DOIUrl":"10.1007/s10470-026-02578-2","url":null,"abstract":"<div><p>Low-power sensing Internet of Things (IoT) devices rely on filtering noise and interference in any impedance network applications. The sensing device’s high-performance is identified based on their utilization, maximum interference impedance and signal gain. However, due to large device integration, the above-mentioned features are distorted in IoT platforms. To address this problem, a novel Minimal Impedance Optimization Method (MIOM) is introduced in this paper. The proposed method incorporates high-impedance filters with a half-adder design for filtering noises between different frequency devices. This is exclusive for heterogeneous integrations in IoT for filtering noise and increasing signal gain. The verification of increasing or sustaining gain is computed using Deep Recurrent Learning (DRL) for impedance and utilization. Based on the failures in impedance and utilization (low) the adder design is replaced with alternate gates that handle minimal signal inputs. Therefore, the change in further utilization and interference impedance is validated from the new adder design by the neural learning. This learning output is used for determining the Device-To-Device (D2D) integration and communication modeling in the IoT platform. Besides, the above recurrent verifications are pursued by IoT devices across various applications in a distributed manner.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147341143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and development of low noise transimpedance amplifier for low intensity light level detection applications for UV range 低噪声跨阻放大器的设计与开发，用于紫外范围内的低强度光水平检测

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-02-23 DOI: 10.1007/s10470-026-02573-7

Nikhil Deep Gupta, Ch. V. S. Krishna Shanmukh, N. Akshitha, A. Revant, K. Raghunath, Ashwani Kumar

{"title":"Design and development of low noise transimpedance amplifier for low intensity light level detection applications for UV range","authors":"Nikhil Deep Gupta, Ch. V. S. Krishna Shanmukh, N. Akshitha, A. Revant, K. Raghunath, Ashwani Kumar","doi":"10.1007/s10470-026-02573-7","DOIUrl":"10.1007/s10470-026-02573-7","url":null,"abstract":"<div><p>It is always challenging to detect a low intensity UV radiation coming from an atmospheric phenomenon using a simple photodetector based conventional circuits. Gain and noise both are required to be carefully controlled and there is a need for a trade-off between these two parameters for detecting such an input radiation. In such cases, transimpedance amplifier (TIA) can play a crucial role, which is an electronic device that converts input current into an output voltage. It is widely used in applications like photodetector signal processing, optical communication, and remote sensing. However, there is still a need to better the performances of TIAs, especially for ultra-low current levels, in nano and pico-ampere ranges, coming from photodetectors due to weak inputs. These low levels are highly susceptible to noise, if not controlled, will also be amplified along with the signal. The present work demonstrates the design and analysis of a three-stage TIA, optimized for the detection of low intensity signals in UV and low wavelength applications. The proposed design has achieved an optimal gain-bandwidth tradeoff while maintaining a high signal-to-noise ratio (SNR) and optimal stability. The experimental PCB results have shown that for the input current of 100 pA corresponding to off state, an SNR of 46 dB with a bandwidth of 29 kHz has been achieved, while for an input current of 161.74 nA, corresponding to on state, the circuit achieves an SNR of 86.84 dB over 1 kHz with an extended bandwidth of 256.19 kHz and 1 pA/√Hz input-referred noise current at 100 kHz. This wide range of detection can make this design highly useful for various applications including low-light detection and biomedical instrumentation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147341147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Microstrip-to-WR5 transition loaded with parasitically capacitive array for mm-wave and lower THz applications 在毫米波和更低太赫兹应用中，负载寄生电容阵列的微带到wr5转换

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2026-02-21 DOI: 10.1007/s10470-026-02575-5

Atul Varshney

{"title":"Microstrip-to-WR5 transition loaded with parasitically capacitive array for mm-wave and lower THz applications","authors":"Atul Varshney","doi":"10.1007/s10470-026-02575-5","DOIUrl":"10.1007/s10470-026-02575-5","url":null,"abstract":"<div><p>The design and analysis of an inline (0°) E-Plane microstrip line-to-WR5 transition using an antipodal dipole antenna at a frequency of 180 GHz for mm-wave and lower THz applications are presented in this article. The impedance matching between the MS-line and antipodal dipole antenna and mode matching between the MS-line and rectangular waveguide (RWG) are achieved using an impedance transformer. The excellent performance of transitions is obtained because of the parasitic loading of the transition with a 14-capacitive array. There is insertion loss (IL><span>(:-)</span>0.15 dB) and return loss (RL<<span>(:-)</span>19 dB) with the proposed change over a 44.44% relative bandwidth (39.5% fractional bandwidth) from 166.19 GHz to 203.46 GHz. The lowest values of IL and RL were − 0.17 dB and − 17.23 dB obtained at a frequency of 140 GHz, respectively. A double-sided high-permittivity of 12.4 and 50 μm thick InP-Substrate for Microstrip-Launcher reduces radiation loss while reducing the maximum fractional bandwidth (FBW). The design transition is simple, easy to manufacture, robust, compacted, and cost-effective since no ridge waveguide or waveguide back shorts are deployed in WR5. Also, it does not require any additional numbers of vias, fences, windows, screws, galvanic structures, posts, etc. Hence, the design transition is a suitable candidate for radio astronomy, amateur satellites, earth exploration satellites, radiolocation, and radio navigation satellites, suitable for direct integration with MMIC circuits and mm-wave, sub-mm-wave, and lower THz frequency mixers, amplifiers, and other applications. This transition is also applicable to the radiometric imaging system and G-band radiometer systems used to generate mm-wave images.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"126 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2026-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147340718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0