Analog Integrated Circuits and Signal Processing最新文献

{"title":"On the design of a level-crossing ADC with 1-bit DAC and rail-to-rail continuous-time comparator","authors":"Fereshte Shahbazi,&nbsp;Hossein Shamsi","doi":"10.1007/s10470-025-02344-w","DOIUrl":"10.1007/s10470-025-02344-w","url":null,"abstract":"<div><p>A level-crossing ADC, which includes a 1-bit DAC, a rail-to-rail continuous-time comparator and a 3-stage continuous-time comparator, has been simulated in 0.18 μm CMOS process with 0.8 V supply voltage. Interpolation between samples has been used to add more samples to the original signal and reconstruct ADC’s output signal. The ADC has SNDR of 47.2 dB (with polynomial interpolation), ENOB of 7.5-bit and power consumption of 460 nW for 1 kHz sinusoidal input signal with common-mode voltage of 400 mV and amplitude of 800 m<span>(:{text{V}}_{text{P}text{P}})</span>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143370045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PAPR reduction and low power-consumption LDO in OFDM transceiver","authors":"Liu Bing,&nbsp;Wu Hong","doi":"10.1007/s10470-025-02341-z","DOIUrl":"10.1007/s10470-025-02341-z","url":null,"abstract":"<div><p>The article mainly discusses the method of reducing PAPR of multi-carrier modulation transmitters in portable application. We firstly discussed the phase noise in OFDM system by power-supply disturbance, and some common algorithms to suppress PAPR. Further we propose an improved structural circuit of the non-capacitor LDO in the transmitter power supply, which can regulate the power load capacity to improve PAPR performance of OFDM transmitter. Based on the statistical information on sending data and precoder, we demonstrate that the power circuit can maintain a fast response and a lower average energy consumption. In addition, tests have shown that the proposed LDO circuit can maintain stable output voltage under conditions of rapid switches in load current values.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143370053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Metastability-based random number generator with current-controlled offset compensation","authors":"Yasin Talay","doi":"10.1007/s10470-024-02298-5","DOIUrl":"10.1007/s10470-024-02298-5","url":null,"abstract":"<div><p>The paper presents the design and measurement results of a metastability based true random number generator (TRNG) core, which was fabricated with HHGRACE 130-nm CMOS technology. Design and simulation results of a complete TRNG intended for hardware cryptographic systems, internet-of-things (IoT), smartcards and secure communication applications is also presented. Random numbers are generated from the differential noise occurring at the StrongARM comparator inputs. Tests were carried out at 0 <span>(^{circ })</span>C, 50 <span>(^{circ })</span>C and 70 <span>(^{circ })</span>C on two separate chips, which confirmed full compliance with NIST and AIS-31 randomness criteria. The proposed complete TRNG occupies 10000 <span>(upmu)</span>m<span>(^2)</span> area, and offers 30-Mbps throughput while consuming 1.35 mW for 1.5-V power supply voltage.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143369999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A compact quintuple band miniaturized elliptical planar monopole antenna for 5G/6G wireless systems","authors":"Digvijay Pandey,&nbsp;Manvinder Sharma,&nbsp;Rajneesh Talwar,&nbsp;Binay Kumar Pandey","doi":"10.1007/s10470-025-02310-6","DOIUrl":"10.1007/s10470-025-02310-6","url":null,"abstract":"<div><p>In the modern era of wireless communications, there is an ever increasing demand for compact antennas. The antennas that can operate across multiple frequency bands while effectively rejecting potential interfering signals. This need arises from the rapidly growing number of wireless systems and applications coexisting within the limited available spectrum. In this paper, elliptical monopole planar antenna with penta band notched characteristics is designed and fabricated for 5G/6G wireless system. The proposed antenna design incorporates two elliptical split ring resonators on the radiation patch to enable band rejection from 3.7 to 4.2 GHz for C band satellite communication along with 5.15–5.35 GHz for the lower WLAN band. A special metamaterial structure consisting of a two via double slot type EBG creates dual notches at 4.5–4.7 GHz for INSAT and 5.725–5.825 GHz for the upper band of WLAN. Additionally, In the vicinity of the feed line, a step impedance resonator suppresses the 7.95–8.55 GHz ITU band. This multi band notched characteristic makes the antenna suitable for applications requiring concurrent operation across multiple bands while mitigating interference from other co existing wireless services.The antenna is made with FR4 substrate and of a compact size of 38 × 38 × 0.8 mm³, making it suitable for integration into modern portable and wireless devices.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143370054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid fractal antenna design for UWB applications inspired by Giuseppe Peano and Sierpinski Carpet","authors":"Sanae Attioui,&nbsp;Asma Khabba,&nbsp;Lahcen Aguni,&nbsp;Saida Ibnyaich,&nbsp;Abdelouhab Zeroual","doi":"10.1007/s10470-025-02338-8","DOIUrl":"10.1007/s10470-025-02338-8","url":null,"abstract":"<div><p>This manuscript serves to introduce an ultra-wideband fractal antenna, which combines the Sierpinski carpet and Giuseppe Peano fractal structures along with a new developed ground geometry, intentionally created for ultra-wideband applications. The High Frequency Structure Simulator HFSS was employed to conduct a deep analysis on the suggested antenna, which is compact in size measuring <span>(30times 30times 1.6~textrm{mm}^{3})</span>. The proposed design can be employed for various purposes such as ultra-wideband applications, sub-6GHz 5 G applications, WIMAX, WLAN, C-Band, and X-Band for satellite communication, etc. The proposed fractal-based antenna has been carefully optimized through parametric study to function effectively across a frequency range spanning from 3.32 to 11.96 GHz and a maximum gain of 5.6 dB. To confirm the simulation outcomes and the operational bandwidth, The suggested fractal antenna prototype was fabricated utilizing the cost-effective FR4 substrate. The experimental and simulation results have shown a good concordance, which provides substantial evidence on the validity of the proposed design. Due to its wide impedance bandwidth good radiation performance and small footprint, the suggested antenna is highly recommended and considered as a good choice for ultra-wide band communication and other wireless applications.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143362015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An X-band high linearity rail-to-rail variable-gain LNA in 65 nm CMOS technology","authors":"Razieh Ghasemi,&nbsp;Hassan Daryanavard,&nbsp;Meisam Pourahmadi-Nakhli","doi":"10.1007/s10470-025-02311-5","DOIUrl":"10.1007/s10470-025-02311-5","url":null,"abstract":"<div><p>In this paper a low noise figure (NF) variable-gain low noise amplifier (VG-LNA) is presented. In the proposed circuit a gain cascaded branch is utilized to provide a rail-to-rail control voltage to vary the gain of LNA in a wide range and improve the dynamic range of the front-end receiver block. Besides, the gain of the proposed LNA is amplified by using a current reused technique with the rearrangement of its components, leading to an improvement of the total occupied area by more than 22%. The performance of the proposed VG-LNA is evaluated by the post-layout simulation results provided by TSMC 65 nm CMOS technology with a 1.2 V supply voltage. The simulation results demonstrate that the gain of the circuit is varied linearly from 15 to 24.2 dB by changing the control voltage from rail-to-rail. Besides, the proposed VG-LNA has an NF of less than 3.3 dB and S11 of better than − 23 dB in a wide temperature range while the power consumption is 9.3 mW @ 9.3 GHz center frequency. Also, the occupied area of the VG-LNA is 0.187 mm² (407 µm × 460 µm).</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ECRAAL: a high-performance multiplier design by efficient charge recovery asynchronous adiabatic logic","authors":"S. Nagaraj,&nbsp;G. M. Sreerama Reddy,&nbsp;S. Aruna Mastani","doi":"10.1007/s10470-025-02313-3","DOIUrl":"10.1007/s10470-025-02313-3","url":null,"abstract":"<div><p>Power consumption is one of the most important factors in modern digital signal processor (DSP) systems. A number of measures for minimizing power consumption, such as reducing supply voltage, switching activity, and capacitance, have been incorporated into the digital design of complementary metal oxide semiconductors (CMOS). However, these strategies don't work with the current CMOS design. As a result, this study concentrated on adiabatic logic, which has proven to be an outstanding way for developing low-power digital circuits. Adiabatic logic circuits return power to their source rather than release power as heat. So, in this research, novel and efficient charge recovery asynchronous adiabatic logic (ECRAAL)-based logic gates are developed to design a high-performance multiplier for high-speed digital circuits. The proposed adiabatic logic-based multiplier is designed using the Tanner EDA tool, and various performance metrics are used to assess the proposed multiplier's efficacy. The results analyzed show that the proposed 16-bit multiplier has a maximum propagation delay that is 38.46% and 16.46% less than Transmission Gate (TG) CMOS and Transmission-gate based Full Adder (TFA) designs, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Widely tunable THz source based on constructive wave oscillator in a 130-nm SiGe BiCMOS","authors":"Göker Ariyak","doi":"10.1007/s10470-025-02333-z","DOIUrl":"10.1007/s10470-025-02333-z","url":null,"abstract":"<div><p>This paper presents a novel tunable THz source based on a six-section Constructive Wave Oscillator (CWO) designed in a 130-nm SiGe BiCMOS process. Unlike traditional THz source designs that rely on VCOs and frequency multipliers, this approach offers a simple, compact, and yet power-efficient solution. The proposed architecture achieves a <span>(10 %)</span> tuning range and generates phasor signals beyond the conventional I/Q (<span>(0^{circ })</span>–<span>(90^{circ })</span>) type, enabling new possibilities for modulation schemes and harmonic cancellation. The design generates a 0.285 THz signal based on a tunable CWO operating at 95 GHz, with 95 GHz signals distributed along the ring with <span>(60^{circ })</span> phases. The THz source combines these signals to produce a signal at <span>(3f_0)</span> using a harmonic cancellation technique. The circuit occupies a compact area of 0.46 × 0.51 <span>(hbox {mm}^2)</span> and dissipates only 60 mW of DC power from a 2V supply. The tunable THz source demonstrates a simulated -22 dBm output power and a phase noise of -76 dBc/Hz at a 1 MHz offset, making it a significant advancement in the field of THz signal generation.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 512-ns conversion time 13-bit parallel two-step single-slope ADC for hundreds of mpxiel CMOS image sensors","authors":"Ruiming Xu,&nbsp;Zhongjie Guo,&nbsp;Changxu Su,&nbsp;Suiyang Liu,&nbsp;Ningmei Yu","doi":"10.1007/s10470-025-02314-2","DOIUrl":"10.1007/s10470-025-02314-2","url":null,"abstract":"<div><p>This paper proposes a 13-bit parallel two-step single slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be + 0.8/-0.8 LSB and + 2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 74.4% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143110115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A probabilistic approach to design inexact compressors for approximate booth multipliers","authors":"Bindu G Gowda,&nbsp;H C Prashanth,&nbsp;V N Muralidhara,&nbsp;Madhav Rao","doi":"10.1007/s10470-025-02327-x","DOIUrl":"10.1007/s10470-025-02327-x","url":null,"abstract":"<div><p>Approximate computing is accepted for error-tolerant tasks including image and signal processing applications, where execution time is more critical than accuracy. Approximation in the multiplier design is considered highly beneficial due to reduced hardware requirements and yet achieves acceptable inference from the rendered output. A probabilistic approach to build approximate compressors specifically for Radix-4 modified booth multiplier is designed to provide power and footprint savings, and at the same time offer performance benefits with lesser errors. The inexact compressor design when applied on the booth encoded reduced partial products (PP) offers a significant improvement over the existing approximate multiplier design. Five variants of inexact multiplier designs were derived by placing approximate compressors across the columns of the Booth multiplier generated partial product matrix (PPM). Two additional design variants including truncation on the lower significant part of the PPM in the multiplier design were also investigated. All the proposed multiplier design variants were synthesized and characterized for hardware parameters, and error metrics. Two design configurations: Design-1 with the conventional approach of sign extending each PP rows till the <span>((2n-1){th})</span> bit in an <span>(ntimes n)</span> multiplier, and Design-2 without sign extension with a modified PPM, are considered to evaluate all the seven proposed multiplier variants in each case. The <span>(9times 9)</span> Design-1 achieved the maximum benefit of 46.27%, 61.18%, 16.79%, and 66.18% in footprint, power, delay, and overall product of delay and power (PDP), while Design-2 achieved the maximum of 61.33%, 77.54%, 41.45%, and 86.8% footprint, power, delay, and PDP savings respectively over their exact versions. <span>(16times 16)</span> Design-2 variant exhibited the maximum of 11.29%, 32.01%, and 32.42% area, power and PDP improvements, respectively, among the evaluated design variants in comparison with the exact one. The proposed approximate multipliers also showcased superior Mean Relative Error Distance (MRED) and <span>(P_{textrm{RED}})</span> (Probability of getting an RED smaller than 2%) when compared with various existing works. The proposed design variants in this work were evaluated for the applications: image smoothing using the Gaussian filter, image segmentation using k-means clustering which is an unsupervised learning algorithm popularly used in computer vision systems, <span>(mu -law)</span> algorithm which is a standard companding algorithm mainly used in telecommunication systems, and Convolutional Neural Network (CNN) to present error-tolerant results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 2","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143110031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}