Analog Integrated Circuits and Signal Processing最新文献_第10页

Design analysis of advanced power amplifiers for 5G wireless applications: a survey 面向5G无线应用的先进功率放大器设计分析:调研

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-11-15 DOI: 10.1007/s10470-023-02193-5

Muhammad Noaman Zahid, Fayyaz Javeed, Gaofeng Zhu

引用次数: 0

A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display 宽范围、快速锁定的全数字 DLL，具有单周期动态同步功能，适用于舱内触控 LC 显示屏

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-11-10 DOI: 10.1007/s10470-023-02192-6

Zhen-Jie Hong, Yu-Lung Lo, Kuan-Yu Shen, Guan-Yu Chen, Wei-Ju Li

{"title":"A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display","authors":"Zhen-Jie Hong, Yu-Lung Lo, Kuan-Yu Shen, Guan-Yu Chen, Wei-Ju Li","doi":"10.1007/s10470-023-02192-6","DOIUrl":"10.1007/s10470-023-02192-6","url":null,"abstract":"<div>This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in 5 clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal. Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking. Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm2.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135093250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analog circuit diagnosis based on support vector machine with parameter optimization by improved NKCGWO 基于支持向量机的模拟电路诊断，通过改进的 NKCGWO 优化参数

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-11-10 DOI: 10.1007/s10470-023-02194-4

Ping Song, Lishun Chen, Kailong Cai, Ying Xiong, Tingkai Gong

{"title":"Analog circuit diagnosis based on support vector machine with parameter optimization by improved NKCGWO","authors":"Ping Song, Lishun Chen, Kailong Cai, Ying Xiong, Tingkai Gong","doi":"10.1007/s10470-023-02194-4","DOIUrl":"10.1007/s10470-023-02194-4","url":null,"abstract":"<div>Support vector machine (SVM) is a widely used machine learning method in analog circuit fault diagnosis. However, SVM parameters such as kernel parameters and penalty parameters can seriously affect the classification accuracy. The current parameter optimization methods have defects such as slow convergence speed, easy falling into local optimal solutions, and premature convergence. Because of this, an improved grey wolf optimization algorithm (GWO) based on the nonlinear control parameter strategy, the first Kepler’s law strategy, and chaotic search strategy (NKCGWO) is proposed to overcome the shortcomings of the traditional optimization methods in this paper. In the NKCGWO method, three strategies are developed to improve the performance of GWO. Thereafter, the optimal parameters of SVM are obtained using NKCGWO-SVM. To evaluate the performance of NKCGWO-SVM for analog circuit diagnosis, two analog circuits are employed for fault diagnosis. The proposed method is compared with GA-SVM, PSO-SVM and GWO-SVM. The experimental results show that the proposed method has higher diagnosis accuracy than the other compared methods for analog circuit diagnosis.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135138305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SBCCI 2022 special issue SBCCI 2022特刊

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-11-07 DOI: 10.1007/s10470-023-02191-7

Luciano Volcan Agostini, Jose Rodrigo Azambuja

引用次数: 0

Systematic design of stable high-order delta sigma modulators using genetic algorithm 利用遗传算法系统设计稳定的高阶三角Σ调制器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-11-05 DOI: 10.1007/s10470-023-02195-3

Ali Naderi Saatlo

引用次数: 0

Chronos-v: a many-core high-level model with support for management techniques Chronos-v:支持管理技术的多核高级模型

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-10-24 DOI: 10.1007/s10470-023-02190-8

Iaçanã Ianiski Weber, Angelo Elias Dal Zotto, Fernando Gehm Moraes

引用次数: 0

VVC decoder intra prediction using approximate storage: an error resilience evaluation 使用近似存储的VVC解码器内预测:一个错误恢复评估

IF 1.4 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-10-21 DOI: 10.1007/s10470-023-02189-1

Matheus Isquierdo, Renira Soares, Felipe Sampaio, Bruno Zatt, Daniel Palomino

{"title":"VVC decoder intra prediction using approximate storage: an error resilience evaluation","authors":"Matheus Isquierdo, Renira Soares, Felipe Sampaio, Bruno Zatt, Daniel Palomino","doi":"10.1007/s10470-023-02189-1","DOIUrl":"10.1007/s10470-023-02189-1","url":null,"abstract":"<div>This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used bit error rate (BER) values from literature for static random-access memory and dynamic random-access memory technologies. We perform an error resilience evaluation based on peak signal-to-noise ratio and structural similarity for twelve video sequences, considering different decoding settings, with four quantization parameters, two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2023-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134797101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A compact adderless feed-forward incremental (varDelta varSigma ) with multiple global references for CMOS image sensors 用于 CMOS 图像传感器的具有多个全局基准的紧凑型无加法器前馈增量（varDelta varSigma ）系统

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-10-08 DOI: 10.1007/s10470-023-02186-4

Nicolas Callens, Georges Gielen

{"title":"A compact adderless feed-forward incremental (varDelta varSigma ) with multiple global references for CMOS image sensors","authors":"Nicolas Callens, Georges Gielen","doi":"10.1007/s10470-023-02186-4","DOIUrl":"10.1007/s10470-023-02186-4","url":null,"abstract":"<div>This paper presents an adderless feed-forward incremental (varDelta varSigma ) (I(varDelta varSigma )) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed I(varDelta varSigma ) ADC is designed in 40 nm CMOS technology and is laid out compactly in a 5 (upmu )m × 466 (upmu )m column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 (upmu )V(_{ rms }), a conversion time of 3.2 (upmu )s (with DCDS) and a power consumption of 230 (upmu )W. This results in a Walden FoM(_{textrm{W}}) of 234 fJ/conv.step and a FoM(_{textrm{A}}) = FoM(_{textrm{W}} times text {A}_{text {ADC}}) of 0.54 fJ(cdot )mm(^2)/conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors.\u0000</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135197656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A sub-1V picowatt voltage reference with improved PSRR and line sensitivity for wearable biomedical applications 改进了 PSRR 和线路灵敏度的 1V 以下皮瓦电压基准，适用于可穿戴生物医学应用

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-10-01 DOI: 10.1007/s10470-023-02187-3

Yilun Jin, Yuhang Zhang, Lining Hu, Zhiwen Gu, Jian Zhao, Yan Liu, Yongwei Lou, Yongfu Li, Zhihong Luo, Yanhan Zeng

{"title":"A sub-1V picowatt voltage reference with improved PSRR and line sensitivity for wearable biomedical applications","authors":"Yilun Jin, Yuhang Zhang, Lining Hu, Zhiwen Gu, Jian Zhao, Yan Liu, Yongwei Lou, Yongfu Li, Zhihong Luo, Yanhan Zeng","doi":"10.1007/s10470-023-02187-3","DOIUrl":"10.1007/s10470-023-02187-3","url":null,"abstract":"<div>This paper presents a picowatt voltage reference circuit using a voltage regulation scheme consisting of a self-regulation native N-type transistor, a double regulation topology formed by a stacked structure of two native N-type transistors, and a P-type transistor-based self-biased current source, to feed a diode-connected P-type load and a PNP transistor load. This improves the line sensitivity and the power supply rejection ratio (PSRR) without the use of an on-chip capacitor. The circuit is designed in a 180 nm CMOS process with an area of 13,700 μm2 and operates with a minimum supply voltage of 0.8 V. Post layout simulation results show that the circuit provides a constant output voltage of 160.2 mV with a temperature coefficient (TC) of 151.6 ppm/(^{circ })C from 0 to 100 (^{circ })C, a line sensitivity of 0.00114%/V, a PSRR of (-)72.6 dB at 100 Hz, and an untrimmed voltage accuracy ((upsigma /upmu)) of 0.99%.</div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135407442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A modular programmable and linear charge pump with low current mismatch 低电流失配的模块化可编程线性电荷泵

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-09-30 DOI: 10.1007/s10470-023-02183-7

Dimitrios Samaras, Alkiviadis Hatzopoulos

引用次数: 0