High-speed and area efficient low-power dynamic parity generator and parity checker

The strategic detection of errors using a parity generator and checker is essential, compelling design engineers to refine and enhance system performance. Even in advanced modern communication systems, errors can still arise due to signal loss and noise, making robust error detection indispensable. This paper brings to light the design of the superior high-speed, low-power 3-bit dynamic parity generator and checker. Two, four, eight, and sixteen-bit XOR gates have been implemented using previous and proposed techniques. The proposed true single-phase dynamic XOR gate builds the parity checker and generator circuits. The proposed dynamic XOR gate, designed 3-bit parity generator, and checker circuits are compared with recently reported techniques. All circuits have been simulated using Cadence Specter on 90 nm technology parameters and tested up to 1 GHz of clock frequency. Comparison is made to showcase the superiority of the proposed design in terms of power consumption, propagation delay, PDP (93.8%), EDP (98.8%), number of transistors, the figure of merit, and unity noise gain. This new 3-bit dynamic parity generator and checker would add a colossal perspective for a design engineer.