A 6 bit and 500 MS/s hybrid ADC with energy efficient CDAC switching scheme

Abstract

We propose a 6-bit hybrid flash-successive approximation (SAR) analog-to-digital converter (ADC) with a switched capacitor digital-to-analog converter (CDAC). Compared to a conventional switching scheme, the dynamic switching energy of the proposed switching scheme is reduced by \(69\%\) for an m-bit/cycle ADC. The total area of the proposed CDAC is reduced by 87.5 and \(50.5\%\), when compared with the conventional binary weighted CDAC and the split capacitor CDAC, respectively. An inverter-based comparator with a common-mode-feedback (CMFB) is used to reduce the power consumption (\(\hbox {P}_{\text {avg}}\)) of the proposed design. The conversion time of the 6-bit ADC is reduced to 3 cycles by using a 3-bit/cycle architecture. The ADC is fabricated in a standard 130 nm CMOS technology with a sampling rate of 500 MS/s. Measured peak signal-to-noise distortion ratio (SNDR) is 31.36 dB with 2.96 mW average power consumption. Achieved effective-number-of-bits (ENOB) and Walden’s figure-of-merit (FOM) are 4.92 and 195 fJ/conversion-step, respectively.