Development of arithmetic optimized low-visibility image enhancement VLSI architecture with saturation-aware transmission map estimation

Abstract

Low light levels can cause a noticeable deterioration in the quality of photos. The visual quality of images and the execution of difficult visual tasks can both be effectively enhanced by resolving a number of low-light image degradation issues. One of the most difficult aspects of low-light enhancement is finding a balance between the three main aspects of image improvement: color integrity, detail presentation, and light intensity. The multi-distribution of spatial domain illumination characteristics in natural scenes complicates the balancing process and affects the effectiveness of such real-time systems. To address these issues, a real-time hardware simulation of an image improvement system is essential. Thus, the VLSI-based pixel-wise saturation-aware transmission map estimation unit is created in this study to eliminate halo artifacts and artefacts around depth discontinuities from the input low-quality images. Prior to that, the Arithmetic Optimized Atmospheric Light Estimation Unit module applies a 15 × 15 minimum filter to determine the atmospheric light by down sampling the input low-light image. In the end, an image restoration unit is created to transform low-visibility images into high-visibility ones. Furthermore, in each step of the proposed architecture, the optimized tree structured magnitude comparator, a reconfigurable unified adder and subtractor unit, and a Divide-and-Conquer based LUT oriented booth multiplier architectures are developed to replace the complexities while maintaining the image quality. At last, the VLSI architectures of the proposed low-visibility enhancement system are implemented in FPGA using Xilinx Verilog coding. The result analysis displayed that the proposed method consumes 0.254W power as well as 0.575 ns delay to complete the whole process, which is considerably lower than the existing methods.